tsiry-sandratraina.com
A modern Music Player Daemon based on Rockbox open source high quality audio player
libadwaita
audio
rust
zig
deno
mpris
rockbox
mpd
stm32h743: add intitial register definitions
Change-Id: I0c9f94103eedb333b2167a8ef49568c8e50c2218
authored by
Aidan MacDonald
and committed by
Solomon Peachy
bf689e9b
d68efd33
+49
firmware/target/arm/stm32/stm32h7/flash.h
+49
firmware/target/arm/stm32/stm32h7/flash.h
···
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stm32h743 version: 1.0
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* stm32h743 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_FLASH_H__
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#define __HEADERGEN_FLASH_H__
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#include "macro.h"
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#define STA_FLASH (0x52002000)
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#define REG_FLASH_ACR st_reg(FLASH_ACR)
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#define STA_FLASH_ACR (0x52002000 + 0x0)
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#define STO_FLASH_ACR (0x0)
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#define STT_FLASH_ACR STIO_32_RW
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#define STN_FLASH_ACR FLASH_ACR
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#define BP_FLASH_ACR_WRHIGHFREQ 3
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#define BM_FLASH_ACR_WRHIGHFREQ 0x38
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#define BF_FLASH_ACR_WRHIGHFREQ(v) (((v) & 0x7) << 3)
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#define BFM_FLASH_ACR_WRHIGHFREQ(v) BM_FLASH_ACR_WRHIGHFREQ
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#define BF_FLASH_ACR_WRHIGHFREQ_V(e) BF_FLASH_ACR_WRHIGHFREQ(BV_FLASH_ACR_WRHIGHFREQ__##e)
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#define BFM_FLASH_ACR_WRHIGHFREQ_V(v) BM_FLASH_ACR_WRHIGHFREQ
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#define BP_FLASH_ACR_LATENCY 0
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#define BM_FLASH_ACR_LATENCY 0xf
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#define BF_FLASH_ACR_LATENCY(v) (((v) & 0xf) << 0)
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#define BFM_FLASH_ACR_LATENCY(v) BM_FLASH_ACR_LATENCY
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#define BF_FLASH_ACR_LATENCY_V(e) BF_FLASH_ACR_LATENCY(BV_FLASH_ACR_LATENCY__##e)
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#define BFM_FLASH_ACR_LATENCY_V(v) BM_FLASH_ACR_LATENCY
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#endif /* __HEADERGEN_FLASH_H__*/
+247
firmware/target/arm/stm32/stm32h7/fmc.h
+247
firmware/target/arm/stm32/stm32h7/fmc.h
···
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stm32h743 version: 1.0
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* stm32h743 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_FMC_H__
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#define __HEADERGEN_FMC_H__
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#include "macro.h"
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#define STA_FMC (0x52004000)
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#define REG_FMC_BCR(_n1) st_reg(FMC_BCR(_n1))
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#define STA_FMC_BCR(_n1) (0x52004000 + 0x0 + (_n1) * 0x8)
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#define STO_FMC_BCR(_n1) (0x0 + (_n1) * 0x8)
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#define STT_FMC_BCR(_n1) STIO_32_RW
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#define STN_FMC_BCR(_n1) FMC_BCR
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#define BP_FMC_BCR_BMAP 24
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#define BM_FMC_BCR_BMAP 0x3000000
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#define BF_FMC_BCR_BMAP(v) (((v) & 0x3) << 24)
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#define BFM_FMC_BCR_BMAP(v) BM_FMC_BCR_BMAP
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#define BF_FMC_BCR_BMAP_V(e) BF_FMC_BCR_BMAP(BV_FMC_BCR_BMAP__##e)
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#define BFM_FMC_BCR_BMAP_V(v) BM_FMC_BCR_BMAP
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#define BP_FMC_BCR_FMCEN 31
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#define BM_FMC_BCR_FMCEN 0x80000000
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#define BF_FMC_BCR_FMCEN(v) (((v) & 0x1) << 31)
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#define BFM_FMC_BCR_FMCEN(v) BM_FMC_BCR_FMCEN
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#define BF_FMC_BCR_FMCEN_V(e) BF_FMC_BCR_FMCEN(BV_FMC_BCR_FMCEN__##e)
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#define BFM_FMC_BCR_FMCEN_V(v) BM_FMC_BCR_FMCEN
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#define BP_FMC_BCR_WFDIS 21
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#define BM_FMC_BCR_WFDIS 0x200000
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#define BF_FMC_BCR_WFDIS(v) (((v) & 0x1) << 21)
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#define BFM_FMC_BCR_WFDIS(v) BM_FMC_BCR_WFDIS
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#define BF_FMC_BCR_WFDIS_V(e) BF_FMC_BCR_WFDIS(BV_FMC_BCR_WFDIS__##e)
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#define BFM_FMC_BCR_WFDIS_V(v) BM_FMC_BCR_WFDIS
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#define REG_FMC_SDCR(_n1) st_reg(FMC_SDCR(_n1))
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#define STA_FMC_SDCR(_n1) (0x52004000 + 0x140 + (_n1) * 0x4)
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#define STO_FMC_SDCR(_n1) (0x140 + (_n1) * 0x4)
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#define STT_FMC_SDCR(_n1) STIO_32_RW
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#define STN_FMC_SDCR(_n1) FMC_SDCR
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#define BP_FMC_SDCR_RPIPE 13
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#define BM_FMC_SDCR_RPIPE 0x6000
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#define BF_FMC_SDCR_RPIPE(v) (((v) & 0x3) << 13)
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#define BFM_FMC_SDCR_RPIPE(v) BM_FMC_SDCR_RPIPE
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#define BF_FMC_SDCR_RPIPE_V(e) BF_FMC_SDCR_RPIPE(BV_FMC_SDCR_RPIPE__##e)
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#define BFM_FMC_SDCR_RPIPE_V(v) BM_FMC_SDCR_RPIPE
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#define BP_FMC_SDCR_SDCLK 10
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#define BM_FMC_SDCR_SDCLK 0xc00
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#define BF_FMC_SDCR_SDCLK(v) (((v) & 0x3) << 10)
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#define BFM_FMC_SDCR_SDCLK(v) BM_FMC_SDCR_SDCLK
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#define BF_FMC_SDCR_SDCLK_V(e) BF_FMC_SDCR_SDCLK(BV_FMC_SDCR_SDCLK__##e)
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#define BFM_FMC_SDCR_SDCLK_V(v) BM_FMC_SDCR_SDCLK
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#define BP_FMC_SDCR_CAS 7
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#define BM_FMC_SDCR_CAS 0x180
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#define BF_FMC_SDCR_CAS(v) (((v) & 0x3) << 7)
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#define BFM_FMC_SDCR_CAS(v) BM_FMC_SDCR_CAS
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#define BF_FMC_SDCR_CAS_V(e) BF_FMC_SDCR_CAS(BV_FMC_SDCR_CAS__##e)
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#define BFM_FMC_SDCR_CAS_V(v) BM_FMC_SDCR_CAS
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#define BP_FMC_SDCR_MWID 4
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#define BM_FMC_SDCR_MWID 0x30
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#define BF_FMC_SDCR_MWID(v) (((v) & 0x3) << 4)
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#define BFM_FMC_SDCR_MWID(v) BM_FMC_SDCR_MWID
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#define BF_FMC_SDCR_MWID_V(e) BF_FMC_SDCR_MWID(BV_FMC_SDCR_MWID__##e)
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#define BFM_FMC_SDCR_MWID_V(v) BM_FMC_SDCR_MWID
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#define BP_FMC_SDCR_NR 2
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#define BM_FMC_SDCR_NR 0xc
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#define BF_FMC_SDCR_NR(v) (((v) & 0x3) << 2)
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#define BFM_FMC_SDCR_NR(v) BM_FMC_SDCR_NR
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#define BF_FMC_SDCR_NR_V(e) BF_FMC_SDCR_NR(BV_FMC_SDCR_NR__##e)
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#define BFM_FMC_SDCR_NR_V(v) BM_FMC_SDCR_NR
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#define BP_FMC_SDCR_NC 0
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#define BM_FMC_SDCR_NC 0x3
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#define BF_FMC_SDCR_NC(v) (((v) & 0x3) << 0)
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#define BFM_FMC_SDCR_NC(v) BM_FMC_SDCR_NC
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#define BF_FMC_SDCR_NC_V(e) BF_FMC_SDCR_NC(BV_FMC_SDCR_NC__##e)
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#define BFM_FMC_SDCR_NC_V(v) BM_FMC_SDCR_NC
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#define BP_FMC_SDCR_RBURST 12
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#define BM_FMC_SDCR_RBURST 0x1000
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#define BF_FMC_SDCR_RBURST(v) (((v) & 0x1) << 12)
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#define BFM_FMC_SDCR_RBURST(v) BM_FMC_SDCR_RBURST
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#define BF_FMC_SDCR_RBURST_V(e) BF_FMC_SDCR_RBURST(BV_FMC_SDCR_RBURST__##e)
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#define BFM_FMC_SDCR_RBURST_V(v) BM_FMC_SDCR_RBURST
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#define BP_FMC_SDCR_WP 9
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#define BM_FMC_SDCR_WP 0x200
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#define BF_FMC_SDCR_WP(v) (((v) & 0x1) << 9)
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#define BFM_FMC_SDCR_WP(v) BM_FMC_SDCR_WP
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#define BF_FMC_SDCR_WP_V(e) BF_FMC_SDCR_WP(BV_FMC_SDCR_WP__##e)
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#define BFM_FMC_SDCR_WP_V(v) BM_FMC_SDCR_WP
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#define BP_FMC_SDCR_NB 6
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#define BM_FMC_SDCR_NB 0x40
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#define BF_FMC_SDCR_NB(v) (((v) & 0x1) << 6)
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#define BFM_FMC_SDCR_NB(v) BM_FMC_SDCR_NB
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#define BF_FMC_SDCR_NB_V(e) BF_FMC_SDCR_NB(BV_FMC_SDCR_NB__##e)
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#define BFM_FMC_SDCR_NB_V(v) BM_FMC_SDCR_NB
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#define REG_FMC_SDTR(_n1) st_reg(FMC_SDTR(_n1))
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#define STA_FMC_SDTR(_n1) (0x52004000 + 0x148 + (_n1) * 0x4)
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#define STO_FMC_SDTR(_n1) (0x148 + (_n1) * 0x4)
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#define STT_FMC_SDTR(_n1) STIO_32_RW
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#define STN_FMC_SDTR(_n1) FMC_SDTR
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#define BP_FMC_SDTR_TRCD 24
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#define BM_FMC_SDTR_TRCD 0xf000000
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#define BF_FMC_SDTR_TRCD(v) (((v) & 0xf) << 24)
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#define BFM_FMC_SDTR_TRCD(v) BM_FMC_SDTR_TRCD
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#define BF_FMC_SDTR_TRCD_V(e) BF_FMC_SDTR_TRCD(BV_FMC_SDTR_TRCD__##e)
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#define BFM_FMC_SDTR_TRCD_V(v) BM_FMC_SDTR_TRCD
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#define BP_FMC_SDTR_TRP 20
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#define BM_FMC_SDTR_TRP 0xf00000
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#define BF_FMC_SDTR_TRP(v) (((v) & 0xf) << 20)
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#define BFM_FMC_SDTR_TRP(v) BM_FMC_SDTR_TRP
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#define BF_FMC_SDTR_TRP_V(e) BF_FMC_SDTR_TRP(BV_FMC_SDTR_TRP__##e)
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#define BFM_FMC_SDTR_TRP_V(v) BM_FMC_SDTR_TRP
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#define BP_FMC_SDTR_TWR 16
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#define BM_FMC_SDTR_TWR 0xf0000
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#define BF_FMC_SDTR_TWR(v) (((v) & 0xf) << 16)
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#define BFM_FMC_SDTR_TWR(v) BM_FMC_SDTR_TWR
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#define BF_FMC_SDTR_TWR_V(e) BF_FMC_SDTR_TWR(BV_FMC_SDTR_TWR__##e)
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#define BFM_FMC_SDTR_TWR_V(v) BM_FMC_SDTR_TWR
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#define BP_FMC_SDTR_TRC 12
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#define BM_FMC_SDTR_TRC 0xf000
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#define BF_FMC_SDTR_TRC(v) (((v) & 0xf) << 12)
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#define BFM_FMC_SDTR_TRC(v) BM_FMC_SDTR_TRC
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#define BF_FMC_SDTR_TRC_V(e) BF_FMC_SDTR_TRC(BV_FMC_SDTR_TRC__##e)
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#define BFM_FMC_SDTR_TRC_V(v) BM_FMC_SDTR_TRC
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#define BP_FMC_SDTR_TRAS 8
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#define BM_FMC_SDTR_TRAS 0xf00
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#define BF_FMC_SDTR_TRAS(v) (((v) & 0xf) << 8)
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#define BFM_FMC_SDTR_TRAS(v) BM_FMC_SDTR_TRAS
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#define BF_FMC_SDTR_TRAS_V(e) BF_FMC_SDTR_TRAS(BV_FMC_SDTR_TRAS__##e)
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#define BFM_FMC_SDTR_TRAS_V(v) BM_FMC_SDTR_TRAS
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#define BP_FMC_SDTR_TXSR 4
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#define BM_FMC_SDTR_TXSR 0xf0
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#define BF_FMC_SDTR_TXSR(v) (((v) & 0xf) << 4)
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#define BFM_FMC_SDTR_TXSR(v) BM_FMC_SDTR_TXSR
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#define BF_FMC_SDTR_TXSR_V(e) BF_FMC_SDTR_TXSR(BV_FMC_SDTR_TXSR__##e)
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#define BFM_FMC_SDTR_TXSR_V(v) BM_FMC_SDTR_TXSR
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#define BP_FMC_SDTR_TMRD 0
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#define BM_FMC_SDTR_TMRD 0xf
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#define BF_FMC_SDTR_TMRD(v) (((v) & 0xf) << 0)
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#define BFM_FMC_SDTR_TMRD(v) BM_FMC_SDTR_TMRD
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#define BF_FMC_SDTR_TMRD_V(e) BF_FMC_SDTR_TMRD(BV_FMC_SDTR_TMRD__##e)
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#define BFM_FMC_SDTR_TMRD_V(v) BM_FMC_SDTR_TMRD
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#define REG_FMC_SDCMR st_reg(FMC_SDCMR)
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#define STA_FMC_SDCMR (0x52004000 + 0x150)
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#define STO_FMC_SDCMR (0x150)
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#define STT_FMC_SDCMR STIO_32_RW
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#define STN_FMC_SDCMR FMC_SDCMR
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#define BP_FMC_SDCMR_MRD 9
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#define BM_FMC_SDCMR_MRD 0x7ffe00
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#define BF_FMC_SDCMR_MRD(v) (((v) & 0x3fff) << 9)
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#define BFM_FMC_SDCMR_MRD(v) BM_FMC_SDCMR_MRD
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#define BF_FMC_SDCMR_MRD_V(e) BF_FMC_SDCMR_MRD(BV_FMC_SDCMR_MRD__##e)
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#define BFM_FMC_SDCMR_MRD_V(v) BM_FMC_SDCMR_MRD
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#define BP_FMC_SDCMR_NRFS 5
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#define BM_FMC_SDCMR_NRFS 0x1e0
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#define BF_FMC_SDCMR_NRFS(v) (((v) & 0xf) << 5)
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#define BFM_FMC_SDCMR_NRFS(v) BM_FMC_SDCMR_NRFS
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#define BF_FMC_SDCMR_NRFS_V(e) BF_FMC_SDCMR_NRFS(BV_FMC_SDCMR_NRFS__##e)
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#define BFM_FMC_SDCMR_NRFS_V(v) BM_FMC_SDCMR_NRFS
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#define BP_FMC_SDCMR_MODE 0
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#define BM_FMC_SDCMR_MODE 0x7
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#define BF_FMC_SDCMR_MODE(v) (((v) & 0x7) << 0)
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#define BFM_FMC_SDCMR_MODE(v) BM_FMC_SDCMR_MODE
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#define BF_FMC_SDCMR_MODE_V(e) BF_FMC_SDCMR_MODE(BV_FMC_SDCMR_MODE__##e)
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#define BFM_FMC_SDCMR_MODE_V(v) BM_FMC_SDCMR_MODE
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#define BP_FMC_SDCMR_CTB1 4
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#define BM_FMC_SDCMR_CTB1 0x10
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#define BF_FMC_SDCMR_CTB1(v) (((v) & 0x1) << 4)
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#define BFM_FMC_SDCMR_CTB1(v) BM_FMC_SDCMR_CTB1
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#define BF_FMC_SDCMR_CTB1_V(e) BF_FMC_SDCMR_CTB1(BV_FMC_SDCMR_CTB1__##e)
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#define BFM_FMC_SDCMR_CTB1_V(v) BM_FMC_SDCMR_CTB1
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#define BP_FMC_SDCMR_CTB2 3
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#define BM_FMC_SDCMR_CTB2 0x8
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#define BF_FMC_SDCMR_CTB2(v) (((v) & 0x1) << 3)
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#define BFM_FMC_SDCMR_CTB2(v) BM_FMC_SDCMR_CTB2
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#define BF_FMC_SDCMR_CTB2_V(e) BF_FMC_SDCMR_CTB2(BV_FMC_SDCMR_CTB2__##e)
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#define BFM_FMC_SDCMR_CTB2_V(v) BM_FMC_SDCMR_CTB2
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#define REG_FMC_SDRTR st_reg(FMC_SDRTR)
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#define STA_FMC_SDRTR (0x52004000 + 0x154)
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#define STO_FMC_SDRTR (0x154)
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#define STT_FMC_SDRTR STIO_32_RW
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#define STN_FMC_SDRTR FMC_SDRTR
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#define BP_FMC_SDRTR_COUNT 1
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#define BM_FMC_SDRTR_COUNT 0x3ffe
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#define BF_FMC_SDRTR_COUNT(v) (((v) & 0x1fff) << 1)
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#define BFM_FMC_SDRTR_COUNT(v) BM_FMC_SDRTR_COUNT
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#define BF_FMC_SDRTR_COUNT_V(e) BF_FMC_SDRTR_COUNT(BV_FMC_SDRTR_COUNT__##e)
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#define BFM_FMC_SDRTR_COUNT_V(v) BM_FMC_SDRTR_COUNT
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#define BP_FMC_SDRTR_REIE 14
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#define BM_FMC_SDRTR_REIE 0x4000
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#define BF_FMC_SDRTR_REIE(v) (((v) & 0x1) << 14)
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#define BFM_FMC_SDRTR_REIE(v) BM_FMC_SDRTR_REIE
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#define BF_FMC_SDRTR_REIE_V(e) BF_FMC_SDRTR_REIE(BV_FMC_SDRTR_REIE__##e)
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#define BFM_FMC_SDRTR_REIE_V(v) BM_FMC_SDRTR_REIE
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#define BP_FMC_SDRTR_CRE 0
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#define BM_FMC_SDRTR_CRE 0x1
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#define BF_FMC_SDRTR_CRE(v) (((v) & 0x1) << 0)
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#define BFM_FMC_SDRTR_CRE(v) BM_FMC_SDRTR_CRE
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#define BF_FMC_SDRTR_CRE_V(e) BF_FMC_SDRTR_CRE(BV_FMC_SDRTR_CRE__##e)
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#define BFM_FMC_SDRTR_CRE_V(v) BM_FMC_SDRTR_CRE
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#define REG_FMC_SDSR st_reg(FMC_SDSR)
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#define STA_FMC_SDSR (0x52004000 + 0x158)
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#define STO_FMC_SDSR (0x158)
226
+
#define STT_FMC_SDSR STIO_32_RW
227
+
#define STN_FMC_SDSR FMC_SDSR
228
+
#define BP_FMC_SDSR_MODES2 3
229
+
#define BM_FMC_SDSR_MODES2 0x18
230
+
#define BF_FMC_SDSR_MODES2(v) (((v) & 0x3) << 3)
231
+
#define BFM_FMC_SDSR_MODES2(v) BM_FMC_SDSR_MODES2
232
+
#define BF_FMC_SDSR_MODES2_V(e) BF_FMC_SDSR_MODES2(BV_FMC_SDSR_MODES2__##e)
233
+
#define BFM_FMC_SDSR_MODES2_V(v) BM_FMC_SDSR_MODES2
234
+
#define BP_FMC_SDSR_MODES1 1
235
+
#define BM_FMC_SDSR_MODES1 0x6
236
+
#define BF_FMC_SDSR_MODES1(v) (((v) & 0x3) << 1)
237
+
#define BFM_FMC_SDSR_MODES1(v) BM_FMC_SDSR_MODES1
238
+
#define BF_FMC_SDSR_MODES1_V(e) BF_FMC_SDSR_MODES1(BV_FMC_SDSR_MODES1__##e)
239
+
#define BFM_FMC_SDSR_MODES1_V(v) BM_FMC_SDSR_MODES1
240
+
#define BP_FMC_SDSR_RE 0
241
+
#define BM_FMC_SDSR_RE 0x1
242
+
#define BF_FMC_SDSR_RE(v) (((v) & 0x1) << 0)
243
+
#define BFM_FMC_SDSR_RE(v) BM_FMC_SDSR_RE
244
+
#define BF_FMC_SDSR_RE_V(e) BF_FMC_SDSR_RE(BV_FMC_SDSR_RE__##e)
245
+
#define BFM_FMC_SDSR_RE_V(v) BM_FMC_SDSR_RE
246
+
247
+
#endif /* __HEADERGEN_FMC_H__*/
+91
firmware/target/arm/stm32/stm32h7/gpio.h
+91
firmware/target/arm/stm32/stm32h7/gpio.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
* stm32h743 version: 1.0
11
+
* stm32h743 authors: Aidan MacDonald
12
+
*
13
+
* Copyright (C) 2015 by the authors
14
+
*
15
+
* This program is free software; you can redistribute it and/or
16
+
* modify it under the terms of the GNU General Public License
17
+
* as published by the Free Software Foundation; either version 2
18
+
* of the License, or (at your option) any later version.
19
+
*
20
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21
+
* KIND, either express or implied.
22
+
*
23
+
****************************************************************************/
24
+
#ifndef __HEADERGEN_GPIO_H__
25
+
#define __HEADERGEN_GPIO_H__
26
+
27
+
#include "macro.h"
28
+
29
+
#define STA_GPIO(_n1) (0x58020000 + (_n1) * 0x400)
30
+
31
+
#define REG_GPIO_MODER(_n1) st_reg(GPIO_MODER(_n1))
32
+
#define STA_GPIO_MODER(_n1) (0x58020000 + (_n1) * 0x400 + 0x0)
33
+
#define STO_GPIO_MODER (0x0)
34
+
#define STT_GPIO_MODER(_n1) STIO_32_RW
35
+
#define STN_GPIO_MODER(_n1) GPIO_MODER
36
+
37
+
#define REG_GPIO_OTYPER(_n1) st_reg(GPIO_OTYPER(_n1))
38
+
#define STA_GPIO_OTYPER(_n1) (0x58020000 + (_n1) * 0x400 + 0x4)
39
+
#define STO_GPIO_OTYPER (0x4)
40
+
#define STT_GPIO_OTYPER(_n1) STIO_32_RW
41
+
#define STN_GPIO_OTYPER(_n1) GPIO_OTYPER
42
+
43
+
#define REG_GPIO_OSPEEDR(_n1) st_reg(GPIO_OSPEEDR(_n1))
44
+
#define STA_GPIO_OSPEEDR(_n1) (0x58020000 + (_n1) * 0x400 + 0x8)
45
+
#define STO_GPIO_OSPEEDR (0x8)
46
+
#define STT_GPIO_OSPEEDR(_n1) STIO_32_RW
47
+
#define STN_GPIO_OSPEEDR(_n1) GPIO_OSPEEDR
48
+
49
+
#define REG_GPIO_PUPDR(_n1) st_reg(GPIO_PUPDR(_n1))
50
+
#define STA_GPIO_PUPDR(_n1) (0x58020000 + (_n1) * 0x400 + 0xc)
51
+
#define STO_GPIO_PUPDR (0xc)
52
+
#define STT_GPIO_PUPDR(_n1) STIO_32_RW
53
+
#define STN_GPIO_PUPDR(_n1) GPIO_PUPDR
54
+
55
+
#define REG_GPIO_IDR(_n1) st_reg(GPIO_IDR(_n1))
56
+
#define STA_GPIO_IDR(_n1) (0x58020000 + (_n1) * 0x400 + 0x10)
57
+
#define STO_GPIO_IDR (0x10)
58
+
#define STT_GPIO_IDR(_n1) STIO_32_RW
59
+
#define STN_GPIO_IDR(_n1) GPIO_IDR
60
+
61
+
#define REG_GPIO_ODR(_n1) st_reg(GPIO_ODR(_n1))
62
+
#define STA_GPIO_ODR(_n1) (0x58020000 + (_n1) * 0x400 + 0x14)
63
+
#define STO_GPIO_ODR (0x14)
64
+
#define STT_GPIO_ODR(_n1) STIO_32_RW
65
+
#define STN_GPIO_ODR(_n1) GPIO_ODR
66
+
67
+
#define REG_GPIO_BSRR(_n1) st_reg(GPIO_BSRR(_n1))
68
+
#define STA_GPIO_BSRR(_n1) (0x58020000 + (_n1) * 0x400 + 0x18)
69
+
#define STO_GPIO_BSRR (0x18)
70
+
#define STT_GPIO_BSRR(_n1) STIO_32_RW
71
+
#define STN_GPIO_BSRR(_n1) GPIO_BSRR
72
+
73
+
#define REG_GPIO_LCKR(_n1) st_reg(GPIO_LCKR(_n1))
74
+
#define STA_GPIO_LCKR(_n1) (0x58020000 + (_n1) * 0x400 + 0x1c)
75
+
#define STO_GPIO_LCKR (0x1c)
76
+
#define STT_GPIO_LCKR(_n1) STIO_32_RW
77
+
#define STN_GPIO_LCKR(_n1) GPIO_LCKR
78
+
79
+
#define REG_GPIO_AFRL(_n1) st_reg(GPIO_AFRL(_n1))
80
+
#define STA_GPIO_AFRL(_n1) (0x58020000 + (_n1) * 0x400 + 0x20)
81
+
#define STO_GPIO_AFRL (0x20)
82
+
#define STT_GPIO_AFRL(_n1) STIO_32_RW
83
+
#define STN_GPIO_AFRL(_n1) GPIO_AFRL
84
+
85
+
#define REG_GPIO_AFRH(_n1) st_reg(GPIO_AFRH(_n1))
86
+
#define STA_GPIO_AFRH(_n1) (0x58020000 + (_n1) * 0x400 + 0x24)
87
+
#define STO_GPIO_AFRH (0x24)
88
+
#define STT_GPIO_AFRH(_n1) STIO_32_RW
89
+
#define STN_GPIO_AFRH(_n1) GPIO_AFRH
90
+
91
+
#endif /* __HEADERGEN_GPIO_H__*/
+454
firmware/target/arm/stm32/stm32h7/macro.h
+454
firmware/target/arm/stm32/stm32h7/macro.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
*
11
+
* Copyright (C) 2015 by the authors
12
+
*
13
+
* This program is free software; you can redistribute it and/or
14
+
* modify it under the terms of the GNU General Public License
15
+
* as published by the Free Software Foundation; either version 2
16
+
* of the License, or (at your option) any later version.
17
+
*
18
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19
+
* KIND, either express or implied.
20
+
*
21
+
****************************************************************************/
22
+
#ifndef __HEADERGEN_MACRO_H__
23
+
#define __HEADERGEN_MACRO_H__
24
+
25
+
#include <stdint.h>
26
+
27
+
#define __VAR_OR1(prefix, suffix) \
28
+
(prefix##suffix)
29
+
#define __VAR_OR2(pre, s1, s2) \
30
+
(__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2))
31
+
#define __VAR_OR3(pre, s1, s2, s3) \
32
+
(__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3))
33
+
#define __VAR_OR4(pre, s1, s2, s3, s4) \
34
+
(__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4))
35
+
#define __VAR_OR5(pre, s1, s2, s3, s4, s5) \
36
+
(__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5))
37
+
#define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \
38
+
(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6))
39
+
#define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \
40
+
(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7))
41
+
#define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \
42
+
(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8))
43
+
#define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \
44
+
(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9))
45
+
#define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \
46
+
(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10))
47
+
#define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \
48
+
(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11))
49
+
#define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \
50
+
(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12))
51
+
#define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \
52
+
(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13))
53
+
#define __VAR_OR14(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14) \
54
+
(__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR7(pre, s8, s9, s10, s11, s12, s13, s14))
55
+
#define __VAR_OR15(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15) \
56
+
(__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR8(pre, s8, s9, s10, s11, s12, s13, s14, s15))
57
+
#define __VAR_OR16(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16) \
58
+
(__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR8(pre, s9, s10, s11, s12, s13, s14, s15, s16))
59
+
#define __VAR_OR17(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17) \
60
+
(__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR9(pre, s9, s10, s11, s12, s13, s14, s15, s16, s17))
61
+
#define __VAR_OR18(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18) \
62
+
(__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR9(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18))
63
+
#define __VAR_OR19(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19) \
64
+
(__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR10(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19))
65
+
#define __VAR_OR20(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20) \
66
+
(__VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) | __VAR_OR10(pre, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20))
67
+
68
+
#define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
69
+
#define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, N, ...) N
70
+
71
+
#define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__)
72
+
#define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__)
73
+
#define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__)
74
+
#define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__)
75
+
76
+
#define STIO_8_RO(op, name, ...) STIO_8_RO_##op(name, __VA_ARGS__)
77
+
#define STIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(STA_##name))
78
+
#define STIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only")
79
+
#define STIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
80
+
#define STIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(STA_##name))
81
+
#define STIO_8_RO_RDREL(name, base, ...) (*(const volatile uint8_t *)((base) + STO_##name))
82
+
#define STIO_8_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only")
83
+
#define STIO_8_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only")
84
+
#define STIO_8_RO_VARREL(name, base, ...) (*(const volatile uint8_t *)((base) + STO_##name))
85
+
86
+
#define STIO_16_RO(op, name, ...) STIO_16_RO_##op(name, __VA_ARGS__)
87
+
#define STIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(STA_##name))
88
+
#define STIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only")
89
+
#define STIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
90
+
#define STIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(STA_##name))
91
+
#define STIO_16_RO_RDREL(name, base, ...) (*(const volatile uint16_t *)((base) + STO_##name))
92
+
#define STIO_16_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only")
93
+
#define STIO_16_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only")
94
+
#define STIO_16_RO_VARREL(name, base, ...) (*(const volatile uint16_t *)((base) + STO_##name))
95
+
96
+
#define STIO_32_RO(op, name, ...) STIO_32_RO_##op(name, __VA_ARGS__)
97
+
#define STIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(STA_##name))
98
+
#define STIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only")
99
+
#define STIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
100
+
#define STIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(STA_##name))
101
+
#define STIO_32_RO_RDREL(name, base, ...) (*(const volatile uint32_t *)((base) + STO_##name))
102
+
#define STIO_32_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only")
103
+
#define STIO_32_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only")
104
+
#define STIO_32_RO_VARREL(name, base, ...) (*(const volatile uint32_t *)((base) + STO_##name))
105
+
106
+
#define STIO_8_RW(op, name, ...) STIO_8_RW_##op(name, __VA_ARGS__)
107
+
#define STIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(STA_##name))
108
+
#define STIO_8_RW_WR(name, val) (*(volatile uint8_t *)(STA_##name)) = (val)
109
+
#define STIO_8_RW_RMW(name, vand, vor) STIO_8_RW_WR(name, (STIO_8_RW_RD(name) & (vand)) | (vor))
110
+
#define STIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(STA_##name))
111
+
#define STIO_8_RW_RDREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name))
112
+
#define STIO_8_RW_WRREL(name, base, val) (*(volatile uint8_t *)((base) + STO_##name)) = (val)
113
+
#define STIO_8_RW_RMWREL(name, base, vand, vor) STIO_8_RW_WRREL(name, base, (STIO_8_RW_RDREL(name, base) & (vand)) | (vor))
114
+
#define STIO_8_RW_VARREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name))
115
+
116
+
#define STIO_16_RW(op, name, ...) STIO_16_RW_##op(name, __VA_ARGS__)
117
+
#define STIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(STA_##name))
118
+
#define STIO_16_RW_WR(name, val) (*(volatile uint16_t *)(STA_##name)) = (val)
119
+
#define STIO_16_RW_RMW(name, vand, vor) STIO_16_RW_WR(name, (STIO_16_RW_RD(name) & (vand)) | (vor))
120
+
#define STIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(STA_##name))
121
+
#define STIO_16_RW_RDREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name))
122
+
#define STIO_16_RW_WRREL(name, base, val) (*(volatile uint16_t *)((base) + STO_##name)) = (val)
123
+
#define STIO_16_RW_RMWREL(name, base, vand, vor) STIO_16_RW_WRREL(name, base, (STIO_16_RW_RDREL(name, base) & (vand)) | (vor))
124
+
#define STIO_16_RW_VARREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name))
125
+
126
+
#define STIO_32_RW(op, name, ...) STIO_32_RW_##op(name, __VA_ARGS__)
127
+
#define STIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(STA_##name))
128
+
#define STIO_32_RW_WR(name, val) (*(volatile uint32_t *)(STA_##name)) = (val)
129
+
#define STIO_32_RW_RMW(name, vand, vor) STIO_32_RW_WR(name, (STIO_32_RW_RD(name) & (vand)) | (vor))
130
+
#define STIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(STA_##name))
131
+
#define STIO_32_RW_RDREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name))
132
+
#define STIO_32_RW_WRREL(name, base, val) (*(volatile uint32_t *)((base) + STO_##name)) = (val)
133
+
#define STIO_32_RW_RMWREL(name, base, vand, vor) STIO_32_RW_WRREL(name, base, (STIO_32_RW_RDREL(name, base) & (vand)) | (vor))
134
+
#define STIO_32_RW_VARREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name))
135
+
136
+
#define STIO_8_WO(op, name, ...) STIO_8_WO_##op(name, __VA_ARGS__)
137
+
#define STIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
138
+
#define STIO_8_WO_WR(name, val) (*(volatile uint8_t *)(STA_##name)) = (val)
139
+
#define STIO_8_WO_RMW(name, vand, vor) STIO_8_WO_WR(name, vor)
140
+
#define STIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(STA_##name))
141
+
#define STIO_8_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;})
142
+
#define STIO_8_WO_WRREL(name, base, val) (*(volatile uint8_t *)((base) + STO_##name)) = (val)
143
+
#define STIO_8_WO_RMWREL(name, base, vand, vor) STIO_8_WO_WRREL(name, base, vor)
144
+
#define STIO_8_WO_VARREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name))
145
+
146
+
#define STIO_16_WO(op, name, ...) STIO_16_WO_##op(name, __VA_ARGS__)
147
+
#define STIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
148
+
#define STIO_16_WO_WR(name, val) (*(volatile uint16_t *)(STA_##name)) = (val)
149
+
#define STIO_16_WO_RMW(name, vand, vor) STIO_16_WO_WR(name, vor)
150
+
#define STIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(STA_##name))
151
+
#define STIO_16_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;})
152
+
#define STIO_16_WO_WRREL(name, base, val) (*(volatile uint16_t *)((base) + STO_##name)) = (val)
153
+
#define STIO_16_WO_RMWREL(name, base, vand, vor) STIO_16_WO_WRREL(name, base, vor)
154
+
#define STIO_16_WO_VARREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name))
155
+
156
+
#define STIO_32_WO(op, name, ...) STIO_32_WO_##op(name, __VA_ARGS__)
157
+
#define STIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
158
+
#define STIO_32_WO_WR(name, val) (*(volatile uint32_t *)(STA_##name)) = (val)
159
+
#define STIO_32_WO_RMW(name, vand, vor) STIO_32_WO_WR(name, vor)
160
+
#define STIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(STA_##name))
161
+
#define STIO_32_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;})
162
+
#define STIO_32_WO_WRREL(name, base, val) (*(volatile uint32_t *)((base) + STO_##name)) = (val)
163
+
#define STIO_32_WO_RMWREL(name, base, vand, vor) STIO_32_WO_WRREL(name, base, vor)
164
+
#define STIO_32_WO_VARREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name))
165
+
166
+
167
+
/** st_orf
168
+
*
169
+
* usage: st_orf(register, f1(v1), f2(v2), ...)
170
+
*
171
+
* effect: expands to the register value where each field fi has value vi.
172
+
* Informally: reg_f1(v1) | reg_f2(v2) | ...
173
+
* note: enumerated values for fields can be obtained by using the syntax:
174
+
* f1_V(name)
175
+
*
176
+
* example: st_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
177
+
*/
178
+
#define st_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__)
179
+
180
+
/** __st_orfm
181
+
*
182
+
* usage: __st_orfm(register, f1(v1), f2(v2), ...)
183
+
*
184
+
* effect: expands to the register value where each field fi has maximum value (vi is ignored).
185
+
* note: internal usage
186
+
*
187
+
* example: __st_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
188
+
*/
189
+
#define __st_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__)
190
+
191
+
/** st_orm
192
+
*
193
+
* usage: st_orm(register, f1, f2, ...)
194
+
*
195
+
* effect: expands to the register value where each field fi is set to its maximum value.
196
+
* Informally: reg_f1_mask | reg_f2_mask | ...
197
+
*
198
+
* example: st_orm(ICOLL_CTRL, SFTRST, CLKGATE)
199
+
*/
200
+
#define st_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__)
201
+
202
+
203
+
/** st_vreadf
204
+
*
205
+
* usage: st_vreadf(value, register, field)
206
+
*
207
+
* effect: given a register value, return the value of a particular field
208
+
* note: this macro does NOT read any register
209
+
*
210
+
* example: st_vreadf(0xc0000000, ICOLL_CTRL, SFTRST)
211
+
* st_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO)
212
+
*/
213
+
#define st_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field)
214
+
215
+
/** st_vwritef
216
+
*
217
+
* usage: st_vwritef(var, register, f1(v1), f2(v2), ...)
218
+
*
219
+
* effect: change the variable value so that field fi has value vi
220
+
* note: this macro will perform a read-modify-write
221
+
*
222
+
* example: st_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
223
+
* st_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
224
+
*/
225
+
#define st_vwritef(var, name, ...) (var) = st_orf(name, __VA_ARGS__) | (~__st_orfm(name, __VA_ARGS__) & (var))
226
+
227
+
/** st_read
228
+
*
229
+
* usage: st_read(register)
230
+
*
231
+
* effect: read the register and return its value
232
+
* note: register must be fully qualified if indexed
233
+
*
234
+
* example: st_read(ICOLL_STATUS)
235
+
* st_read(ICOLL_ENABLE(42))
236
+
*/
237
+
#define st_read(name) STT_##name(RD, name)
238
+
239
+
/** st_readf
240
+
*
241
+
* usage: st_readf(register, field)
242
+
*
243
+
* effect: read a register and return the value of a particular field
244
+
* note: register must be fully qualified if indexed
245
+
*
246
+
* example: st_readf(ICOLL_CTRL, SFTRST)
247
+
* st_readf(ICOLL_ENABLE(3), CPU0_PRIO)
248
+
*/
249
+
#define st_readf(name, field) st_readf_(st_read(name), STN_##name, field)
250
+
#define st_readf_(...) st_vreadf(__VA_ARGS__)
251
+
252
+
/** st_write
253
+
*
254
+
* usage: st_write(register, value)
255
+
*
256
+
* effect: write a register
257
+
* note: register must be fully qualified if indexed
258
+
*
259
+
* example: st_write(ICOLL_CTRL, 0x42)
260
+
* st_write(ICOLL_ENABLE_SET(3), 0x37)
261
+
*/
262
+
#define st_write(name, val) STT_##name(WR, name, val)
263
+
264
+
/** st_writef
265
+
*
266
+
* usage: st_writef(register, f1(v1), f2(v2), ...)
267
+
*
268
+
* effect: change the register value so that field fi has value vi
269
+
* note: register must be fully qualified if indexed
270
+
* note: this macro may perform a read-modify-write
271
+
*
272
+
* example: st_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
273
+
* st_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
274
+
*/
275
+
#define st_writef(name, ...) st_writef_(name, STN_##name, __VA_ARGS__)
276
+
#define st_writef_(name, name2, ...) STT_##name(RMW, name, ~__st_orfm(name2, __VA_ARGS__), st_orf(name2, __VA_ARGS__))
277
+
278
+
/** st_overwritef
279
+
*
280
+
* usage: st_overwritef(register, f1(v1), f2(v2), ...)
281
+
*
282
+
* effect: change the register value so that field fi has value vi and other fields have value zero
283
+
* thus this macro is equivalent to:
284
+
* st_write(register, st_orf(register, f1(v1), ...))
285
+
* note: register must be fully qualified if indexed
286
+
* note: this macro will overwrite the register (it is NOT a read-modify-write)
287
+
*
288
+
* example: st_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
289
+
* st_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
290
+
*/
291
+
#define st_overwritef(name, ...) st_overwritef_(name, STN_##name, __VA_ARGS__)
292
+
#define st_overwritef_(name, name2, ...) STT_##name(WR, name, st_orf(name2, __VA_ARGS__))
293
+
294
+
/** st_setf
295
+
*
296
+
* usage: st_setf(register, f1, f2, ...)
297
+
*
298
+
* effect: change the register value so that field fi has maximum value
299
+
* note: this macro will perform a read-modify-write
300
+
* note: register must be fully qualified if indexed
301
+
*
302
+
* example: st_setf(ICOLL_CTRL, SFTRST, CLKGATE)
303
+
* st_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
304
+
*/
305
+
#define st_setf(name, ...) st_setf_(name, STN_##name, __VA_ARGS__)
306
+
#define st_setf_(name, name2, ...) STT_##name(RMW, name, ~0,st_orm(name2, __VA_ARGS__))
307
+
308
+
/** st_clrf
309
+
*
310
+
* usage: st_clrf(register, f1, f2, ...)
311
+
*
312
+
* effect: change the register value so that field fi has value zero
313
+
* note: this macro will perform a read-modify-write
314
+
* note: register must be fully qualified if indexed
315
+
*
316
+
* example: st_clrf(ICOLL_CTRL, SFTRST, CLKGATE)
317
+
* st_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
318
+
*/
319
+
#define st_clrf(name, ...) st_clrf_(name, STN_##name, __VA_ARGS__)
320
+
#define st_clrf_(name, name2, ...) STT_##name(RMW, name, ~st_orm(name2, __VA_ARGS__), 0)
321
+
322
+
/** st_reg
323
+
*
324
+
* usage: st_reg(register)
325
+
*
326
+
* effect: return a variable-like expression that can be read/written
327
+
* note: register must be fully qualified if indexed
328
+
* note: read-only registers will yield a constant expression
329
+
*
330
+
* example: unsigned x = st_reg(ICOLL_STATUS)
331
+
* unsigned x = st_reg(ICOLL_ENABLE(42))
332
+
* st_reg(ICOLL_ENABLE(42)) = 64
333
+
*/
334
+
#define st_reg(name) STT_##name(VAR, name)
335
+
336
+
/** st_readl
337
+
*
338
+
* usage: st_readl(base, register)
339
+
*
340
+
* effect: read the register and return its value
341
+
* register address is calculated by offsetting from the base address
342
+
* note: register must be fully qualified if indexed
343
+
*
344
+
* example: st_readl(base, ICOLL_STATUS)
345
+
* st_readl(base, ICOLL_ENABLE(42))
346
+
*/
347
+
#define st_readl(base, name) STT_##name(RDREL, name, base)
348
+
349
+
/** st_readlf
350
+
*
351
+
* usage: st_readlf(base, register, field)
352
+
*
353
+
* effect: read a register and return the value of a particular field
354
+
* register address is calculated by offsetting from the base address
355
+
* note: register must be fully qualified if indexed
356
+
*
357
+
* example: st_readlf(base, ICOLL_CTRL, SFTRST)
358
+
* st_readlf(base, ICOLL_ENABLE(3), CPU0_PRIO)
359
+
*/
360
+
#define st_readlf(base, name, field) st_readlf_(st_readl(base, name), STN_##name, field)
361
+
#define st_readlf_(...) st_vreadf(__VA_ARGS__)
362
+
363
+
/** st_writel
364
+
*
365
+
* usage: st_writel(base, register, value)
366
+
*
367
+
* effect: write a register
368
+
* register address is calculated by offsetting from the base address
369
+
* note: register must be fully qualified if indexed
370
+
*
371
+
* example: st_writel(base, ICOLL_CTRL, 0x42)
372
+
* st_writel(base, ICOLL_ENABLE_SET(3), 0x37)
373
+
*/
374
+
#define st_writel(base, name, val) STT_##name(WRREL, name, base, val)
375
+
376
+
/** st_writelf
377
+
*
378
+
* usage: st_writelf(base, register, f1(v1), f2(v2), ...)
379
+
*
380
+
* effect: change the register value so that field fi has value vi
381
+
* register address is calculated by offsetting from the base address
382
+
* note: register must be fully qualified if indexed
383
+
* note: this macro may perform a read-modify-write
384
+
*
385
+
* example: st_writelf(base, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
386
+
* st_writelf(base, ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
387
+
*/
388
+
#define st_writelf(base, name, ...) st_writelf_(base, name, STN_##name, __VA_ARGS__)
389
+
#define st_writelf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~__st_orfm(name2, __VA_ARGS__), st_orf(name2, __VA_ARGS__))
390
+
391
+
/** st_overwritelf
392
+
*
393
+
* usage: st_overwritelf(base, register, f1(v1), f2(v2), ...)
394
+
*
395
+
* effect: change the register value so that field fi has value vi and other fields have value zero
396
+
* register address is calculated by offsetting from the base address
397
+
* thus this macro is equivalent to:
398
+
* st_writel(base, register, st_orf(register, f1(v1), ...))
399
+
* note: register must be fully qualified if indexed
400
+
* note: this macro will overwrite the register (it is NOT a read-modify-write)
401
+
*
402
+
* example: st_overwritelf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
403
+
* st_overwritelf(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
404
+
*/
405
+
#define st_overwritelf(base, name, ...) st_overwritelf_(base, name, STN_##name, __VA_ARGS__)
406
+
#define st_overwritelf_(base, name, name2, ...) STT_##name(WRREL, name, base, st_orf(name2, __VA_ARGS__))
407
+
408
+
/** st_setlf
409
+
*
410
+
* usage: st_setlf(base, register, f1, f2, ...)
411
+
*
412
+
* effect: change the register value so that field fi has maximum value
413
+
* register address is calculated by offsetting from the base address
414
+
* note: this macro will perform a read-modify-write
415
+
* note: register must be fully qualified if indexed
416
+
*
417
+
* example: st_setlf(base, ICOLL_CTRL, SFTRST, CLKGATE)
418
+
* st_setlf(base, ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
419
+
*/
420
+
#define st_setlf(base, name, ...) st_setlf_(base, name, STN_##name, __VA_ARGS__)
421
+
#define st_setlf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~0,st_orm(name2, __VA_ARGS__))
422
+
423
+
/** st_clrlf
424
+
*
425
+
* usage: st_clrlf(base, register, f1, f2, ...)
426
+
*
427
+
* effect: change the register value so that field fi has value zero
428
+
* register address is calculated by offsetting from the base address
429
+
* note: this macro will perform a read-modify-write
430
+
* note: register must be fully qualified if indexed
431
+
*
432
+
* example: st_clrlf(base, ICOLL_CTRL, SFTRST, CLKGATE)
433
+
* st_clrlf(base, ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
434
+
*/
435
+
#define st_clrlf(base, name, ...) st_clrlf_(base, name, STN_##name, __VA_ARGS__)
436
+
#define st_clrlf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~st_orm(name2, __VA_ARGS__), 0)
437
+
438
+
/** st_regl
439
+
*
440
+
* usage: st_regl(base, register)
441
+
*
442
+
* effect: return a variable-like expression that can be read/written
443
+
* register address is calculated by offsetting from the base address
444
+
* note: register must be fully qualified if indexed
445
+
* note: read-only registers will yield a constant expression
446
+
*
447
+
* example: unsigned x = st_regl(base, ICOLL_STATUS)
448
+
* unsigned x = st_regl(base, ICOLL_ENABLE(42))
449
+
* st_regl(base, ICOLL_ENABLE(42)) = 64
450
+
*/
451
+
#define st_regl(base, name) STT_##name(VARREL, base, name)
452
+
453
+
454
+
#endif /* __HEADERGEN_MACRO_H__*/
+190
firmware/target/arm/stm32/stm32h7/pwr.h
+190
firmware/target/arm/stm32/stm32h7/pwr.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
* stm32h743 version: 1.0
11
+
* stm32h743 authors: Aidan MacDonald
12
+
*
13
+
* Copyright (C) 2015 by the authors
14
+
*
15
+
* This program is free software; you can redistribute it and/or
16
+
* modify it under the terms of the GNU General Public License
17
+
* as published by the Free Software Foundation; either version 2
18
+
* of the License, or (at your option) any later version.
19
+
*
20
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21
+
* KIND, either express or implied.
22
+
*
23
+
****************************************************************************/
24
+
#ifndef __HEADERGEN_PWR_H__
25
+
#define __HEADERGEN_PWR_H__
26
+
27
+
#include "macro.h"
28
+
29
+
#define STA_PWR (0x58024800)
30
+
31
+
#define REG_PWR_CR1 st_reg(PWR_CR1)
32
+
#define STA_PWR_CR1 (0x58024800 + 0x0)
33
+
#define STO_PWR_CR1 (0x0)
34
+
#define STT_PWR_CR1 STIO_32_RW
35
+
#define STN_PWR_CR1 PWR_CR1
36
+
#define BP_PWR_CR1_ALS 17
37
+
#define BM_PWR_CR1_ALS 0x60000
38
+
#define BF_PWR_CR1_ALS(v) (((v) & 0x3) << 17)
39
+
#define BFM_PWR_CR1_ALS(v) BM_PWR_CR1_ALS
40
+
#define BF_PWR_CR1_ALS_V(e) BF_PWR_CR1_ALS(BV_PWR_CR1_ALS__##e)
41
+
#define BFM_PWR_CR1_ALS_V(v) BM_PWR_CR1_ALS
42
+
#define BP_PWR_CR1_SVOS 14
43
+
#define BM_PWR_CR1_SVOS 0xc000
44
+
#define BF_PWR_CR1_SVOS(v) (((v) & 0x3) << 14)
45
+
#define BFM_PWR_CR1_SVOS(v) BM_PWR_CR1_SVOS
46
+
#define BF_PWR_CR1_SVOS_V(e) BF_PWR_CR1_SVOS(BV_PWR_CR1_SVOS__##e)
47
+
#define BFM_PWR_CR1_SVOS_V(v) BM_PWR_CR1_SVOS
48
+
#define BP_PWR_CR1_PLS 5
49
+
#define BM_PWR_CR1_PLS 0xe0
50
+
#define BF_PWR_CR1_PLS(v) (((v) & 0x7) << 5)
51
+
#define BFM_PWR_CR1_PLS(v) BM_PWR_CR1_PLS
52
+
#define BF_PWR_CR1_PLS_V(e) BF_PWR_CR1_PLS(BV_PWR_CR1_PLS__##e)
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+
#define BFM_PWR_CR1_PLS_V(v) BM_PWR_CR1_PLS
54
+
#define BP_PWR_CR1_AVDEN 16
55
+
#define BM_PWR_CR1_AVDEN 0x10000
56
+
#define BF_PWR_CR1_AVDEN(v) (((v) & 0x1) << 16)
57
+
#define BFM_PWR_CR1_AVDEN(v) BM_PWR_CR1_AVDEN
58
+
#define BF_PWR_CR1_AVDEN_V(e) BF_PWR_CR1_AVDEN(BV_PWR_CR1_AVDEN__##e)
59
+
#define BFM_PWR_CR1_AVDEN_V(v) BM_PWR_CR1_AVDEN
60
+
#define BP_PWR_CR1_FLPS 9
61
+
#define BM_PWR_CR1_FLPS 0x200
62
+
#define BF_PWR_CR1_FLPS(v) (((v) & 0x1) << 9)
63
+
#define BFM_PWR_CR1_FLPS(v) BM_PWR_CR1_FLPS
64
+
#define BF_PWR_CR1_FLPS_V(e) BF_PWR_CR1_FLPS(BV_PWR_CR1_FLPS__##e)
65
+
#define BFM_PWR_CR1_FLPS_V(v) BM_PWR_CR1_FLPS
66
+
#define BP_PWR_CR1_DBP 8
67
+
#define BM_PWR_CR1_DBP 0x100
68
+
#define BF_PWR_CR1_DBP(v) (((v) & 0x1) << 8)
69
+
#define BFM_PWR_CR1_DBP(v) BM_PWR_CR1_DBP
70
+
#define BF_PWR_CR1_DBP_V(e) BF_PWR_CR1_DBP(BV_PWR_CR1_DBP__##e)
71
+
#define BFM_PWR_CR1_DBP_V(v) BM_PWR_CR1_DBP
72
+
#define BP_PWR_CR1_PVDE 4
73
+
#define BM_PWR_CR1_PVDE 0x10
74
+
#define BF_PWR_CR1_PVDE(v) (((v) & 0x1) << 4)
75
+
#define BFM_PWR_CR1_PVDE(v) BM_PWR_CR1_PVDE
76
+
#define BF_PWR_CR1_PVDE_V(e) BF_PWR_CR1_PVDE(BV_PWR_CR1_PVDE__##e)
77
+
#define BFM_PWR_CR1_PVDE_V(v) BM_PWR_CR1_PVDE
78
+
#define BP_PWR_CR1_LPDS 0
79
+
#define BM_PWR_CR1_LPDS 0x1
80
+
#define BF_PWR_CR1_LPDS(v) (((v) & 0x1) << 0)
81
+
#define BFM_PWR_CR1_LPDS(v) BM_PWR_CR1_LPDS
82
+
#define BF_PWR_CR1_LPDS_V(e) BF_PWR_CR1_LPDS(BV_PWR_CR1_LPDS__##e)
83
+
#define BFM_PWR_CR1_LPDS_V(v) BM_PWR_CR1_LPDS
84
+
85
+
#define REG_PWR_CSR1 st_reg(PWR_CSR1)
86
+
#define STA_PWR_CSR1 (0x58024800 + 0x4)
87
+
#define STO_PWR_CSR1 (0x4)
88
+
#define STT_PWR_CSR1 STIO_32_RW
89
+
#define STN_PWR_CSR1 PWR_CSR1
90
+
#define BP_PWR_CSR1_ACTVOS 14
91
+
#define BM_PWR_CSR1_ACTVOS 0xc000
92
+
#define BF_PWR_CSR1_ACTVOS(v) (((v) & 0x3) << 14)
93
+
#define BFM_PWR_CSR1_ACTVOS(v) BM_PWR_CSR1_ACTVOS
94
+
#define BF_PWR_CSR1_ACTVOS_V(e) BF_PWR_CSR1_ACTVOS(BV_PWR_CSR1_ACTVOS__##e)
95
+
#define BFM_PWR_CSR1_ACTVOS_V(v) BM_PWR_CSR1_ACTVOS
96
+
#define BP_PWR_CSR1_AVDO 16
97
+
#define BM_PWR_CSR1_AVDO 0x10000
98
+
#define BF_PWR_CSR1_AVDO(v) (((v) & 0x1) << 16)
99
+
#define BFM_PWR_CSR1_AVDO(v) BM_PWR_CSR1_AVDO
100
+
#define BF_PWR_CSR1_AVDO_V(e) BF_PWR_CSR1_AVDO(BV_PWR_CSR1_AVDO__##e)
101
+
#define BFM_PWR_CSR1_AVDO_V(v) BM_PWR_CSR1_AVDO
102
+
#define BP_PWR_CSR1_ACTVOSRDY 13
103
+
#define BM_PWR_CSR1_ACTVOSRDY 0x2000
104
+
#define BF_PWR_CSR1_ACTVOSRDY(v) (((v) & 0x1) << 13)
105
+
#define BFM_PWR_CSR1_ACTVOSRDY(v) BM_PWR_CSR1_ACTVOSRDY
106
+
#define BF_PWR_CSR1_ACTVOSRDY_V(e) BF_PWR_CSR1_ACTVOSRDY(BV_PWR_CSR1_ACTVOSRDY__##e)
107
+
#define BFM_PWR_CSR1_ACTVOSRDY_V(v) BM_PWR_CSR1_ACTVOSRDY
108
+
#define BP_PWR_CSR1_PVDO 4
109
+
#define BM_PWR_CSR1_PVDO 0x10
110
+
#define BF_PWR_CSR1_PVDO(v) (((v) & 0x1) << 4)
111
+
#define BFM_PWR_CSR1_PVDO(v) BM_PWR_CSR1_PVDO
112
+
#define BF_PWR_CSR1_PVDO_V(e) BF_PWR_CSR1_PVDO(BV_PWR_CSR1_PVDO__##e)
113
+
#define BFM_PWR_CSR1_PVDO_V(v) BM_PWR_CSR1_PVDO
114
+
115
+
#define REG_PWR_CR3 st_reg(PWR_CR3)
116
+
#define STA_PWR_CR3 (0x58024800 + 0xc)
117
+
#define STO_PWR_CR3 (0xc)
118
+
#define STT_PWR_CR3 STIO_32_RW
119
+
#define STN_PWR_CR3 PWR_CR3
120
+
#define BP_PWR_CR3_USB33RDY 26
121
+
#define BM_PWR_CR3_USB33RDY 0x4000000
122
+
#define BF_PWR_CR3_USB33RDY(v) (((v) & 0x1) << 26)
123
+
#define BFM_PWR_CR3_USB33RDY(v) BM_PWR_CR3_USB33RDY
124
+
#define BF_PWR_CR3_USB33RDY_V(e) BF_PWR_CR3_USB33RDY(BV_PWR_CR3_USB33RDY__##e)
125
+
#define BFM_PWR_CR3_USB33RDY_V(v) BM_PWR_CR3_USB33RDY
126
+
#define BP_PWR_CR3_USBREGEN 25
127
+
#define BM_PWR_CR3_USBREGEN 0x2000000
128
+
#define BF_PWR_CR3_USBREGEN(v) (((v) & 0x1) << 25)
129
+
#define BFM_PWR_CR3_USBREGEN(v) BM_PWR_CR3_USBREGEN
130
+
#define BF_PWR_CR3_USBREGEN_V(e) BF_PWR_CR3_USBREGEN(BV_PWR_CR3_USBREGEN__##e)
131
+
#define BFM_PWR_CR3_USBREGEN_V(v) BM_PWR_CR3_USBREGEN
132
+
#define BP_PWR_CR3_USB33DEN 24
133
+
#define BM_PWR_CR3_USB33DEN 0x1000000
134
+
#define BF_PWR_CR3_USB33DEN(v) (((v) & 0x1) << 24)
135
+
#define BFM_PWR_CR3_USB33DEN(v) BM_PWR_CR3_USB33DEN
136
+
#define BF_PWR_CR3_USB33DEN_V(e) BF_PWR_CR3_USB33DEN(BV_PWR_CR3_USB33DEN__##e)
137
+
#define BFM_PWR_CR3_USB33DEN_V(v) BM_PWR_CR3_USB33DEN
138
+
#define BP_PWR_CR3_VBRS 9
139
+
#define BM_PWR_CR3_VBRS 0x200
140
+
#define BF_PWR_CR3_VBRS(v) (((v) & 0x1) << 9)
141
+
#define BFM_PWR_CR3_VBRS(v) BM_PWR_CR3_VBRS
142
+
#define BF_PWR_CR3_VBRS_V(e) BF_PWR_CR3_VBRS(BV_PWR_CR3_VBRS__##e)
143
+
#define BFM_PWR_CR3_VBRS_V(v) BM_PWR_CR3_VBRS
144
+
#define BP_PWR_CR3_VBE 8
145
+
#define BM_PWR_CR3_VBE 0x100
146
+
#define BF_PWR_CR3_VBE(v) (((v) & 0x1) << 8)
147
+
#define BFM_PWR_CR3_VBE(v) BM_PWR_CR3_VBE
148
+
#define BF_PWR_CR3_VBE_V(e) BF_PWR_CR3_VBE(BV_PWR_CR3_VBE__##e)
149
+
#define BFM_PWR_CR3_VBE_V(v) BM_PWR_CR3_VBE
150
+
#define BP_PWR_CR3_SCUEN 2
151
+
#define BM_PWR_CR3_SCUEN 0x4
152
+
#define BF_PWR_CR3_SCUEN(v) (((v) & 0x1) << 2)
153
+
#define BFM_PWR_CR3_SCUEN(v) BM_PWR_CR3_SCUEN
154
+
#define BF_PWR_CR3_SCUEN_V(e) BF_PWR_CR3_SCUEN(BV_PWR_CR3_SCUEN__##e)
155
+
#define BFM_PWR_CR3_SCUEN_V(v) BM_PWR_CR3_SCUEN
156
+
#define BP_PWR_CR3_LDOEN 1
157
+
#define BM_PWR_CR3_LDOEN 0x2
158
+
#define BF_PWR_CR3_LDOEN(v) (((v) & 0x1) << 1)
159
+
#define BFM_PWR_CR3_LDOEN(v) BM_PWR_CR3_LDOEN
160
+
#define BF_PWR_CR3_LDOEN_V(e) BF_PWR_CR3_LDOEN(BV_PWR_CR3_LDOEN__##e)
161
+
#define BFM_PWR_CR3_LDOEN_V(v) BM_PWR_CR3_LDOEN
162
+
#define BP_PWR_CR3_BYPASS 0
163
+
#define BM_PWR_CR3_BYPASS 0x1
164
+
#define BF_PWR_CR3_BYPASS(v) (((v) & 0x1) << 0)
165
+
#define BFM_PWR_CR3_BYPASS(v) BM_PWR_CR3_BYPASS
166
+
#define BF_PWR_CR3_BYPASS_V(e) BF_PWR_CR3_BYPASS(BV_PWR_CR3_BYPASS__##e)
167
+
#define BFM_PWR_CR3_BYPASS_V(v) BM_PWR_CR3_BYPASS
168
+
169
+
#define REG_PWR_D3CR st_reg(PWR_D3CR)
170
+
#define STA_PWR_D3CR (0x58024800 + 0x18)
171
+
#define STO_PWR_D3CR (0x18)
172
+
#define STT_PWR_D3CR STIO_32_RW
173
+
#define STN_PWR_D3CR PWR_D3CR
174
+
#define BP_PWR_D3CR_VOS 14
175
+
#define BM_PWR_D3CR_VOS 0xc000
176
+
#define BV_PWR_D3CR_VOS__VOS3 0x1
177
+
#define BV_PWR_D3CR_VOS__VOS2 0x2
178
+
#define BV_PWR_D3CR_VOS__VOS1 0x3
179
+
#define BF_PWR_D3CR_VOS(v) (((v) & 0x3) << 14)
180
+
#define BFM_PWR_D3CR_VOS(v) BM_PWR_D3CR_VOS
181
+
#define BF_PWR_D3CR_VOS_V(e) BF_PWR_D3CR_VOS(BV_PWR_D3CR_VOS__##e)
182
+
#define BFM_PWR_D3CR_VOS_V(v) BM_PWR_D3CR_VOS
183
+
#define BP_PWR_D3CR_VOSRDY 13
184
+
#define BM_PWR_D3CR_VOSRDY 0x2000
185
+
#define BF_PWR_D3CR_VOSRDY(v) (((v) & 0x1) << 13)
186
+
#define BFM_PWR_D3CR_VOSRDY(v) BM_PWR_D3CR_VOSRDY
187
+
#define BF_PWR_D3CR_VOSRDY_V(e) BF_PWR_D3CR_VOSRDY(BV_PWR_D3CR_VOSRDY__##e)
188
+
#define BFM_PWR_D3CR_VOSRDY_V(v) BM_PWR_D3CR_VOSRDY
189
+
190
+
#endif /* __HEADERGEN_PWR_H__*/
+2109
firmware/target/arm/stm32/stm32h7/rcc.h
+2109
firmware/target/arm/stm32/stm32h7/rcc.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
* stm32h743 version: 1.0
11
+
* stm32h743 authors: Aidan MacDonald
12
+
*
13
+
* Copyright (C) 2015 by the authors
14
+
*
15
+
* This program is free software; you can redistribute it and/or
16
+
* modify it under the terms of the GNU General Public License
17
+
* as published by the Free Software Foundation; either version 2
18
+
* of the License, or (at your option) any later version.
19
+
*
20
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21
+
* KIND, either express or implied.
22
+
*
23
+
****************************************************************************/
24
+
#ifndef __HEADERGEN_RCC_H__
25
+
#define __HEADERGEN_RCC_H__
26
+
27
+
#include "macro.h"
28
+
29
+
#define STA_RCC (0x58024400)
30
+
31
+
#define REG_RCC_CR st_reg(RCC_CR)
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+
#define STA_RCC_CR (0x58024400 + 0x0)
33
+
#define STO_RCC_CR (0x0)
34
+
#define STT_RCC_CR STIO_32_RW
35
+
#define STN_RCC_CR RCC_CR
36
+
#define BP_RCC_CR_HSIDIV 3
37
+
#define BM_RCC_CR_HSIDIV 0x18
38
+
#define BF_RCC_CR_HSIDIV(v) (((v) & 0x3) << 3)
39
+
#define BFM_RCC_CR_HSIDIV(v) BM_RCC_CR_HSIDIV
40
+
#define BF_RCC_CR_HSIDIV_V(e) BF_RCC_CR_HSIDIV(BV_RCC_CR_HSIDIV__##e)
41
+
#define BFM_RCC_CR_HSIDIV_V(v) BM_RCC_CR_HSIDIV
42
+
#define BP_RCC_CR_PLL3RDY 29
43
+
#define BM_RCC_CR_PLL3RDY 0x20000000
44
+
#define BF_RCC_CR_PLL3RDY(v) (((v) & 0x1) << 29)
45
+
#define BFM_RCC_CR_PLL3RDY(v) BM_RCC_CR_PLL3RDY
46
+
#define BF_RCC_CR_PLL3RDY_V(e) BF_RCC_CR_PLL3RDY(BV_RCC_CR_PLL3RDY__##e)
47
+
#define BFM_RCC_CR_PLL3RDY_V(v) BM_RCC_CR_PLL3RDY
48
+
#define BP_RCC_CR_PLL3ON 28
49
+
#define BM_RCC_CR_PLL3ON 0x10000000
50
+
#define BF_RCC_CR_PLL3ON(v) (((v) & 0x1) << 28)
51
+
#define BFM_RCC_CR_PLL3ON(v) BM_RCC_CR_PLL3ON
52
+
#define BF_RCC_CR_PLL3ON_V(e) BF_RCC_CR_PLL3ON(BV_RCC_CR_PLL3ON__##e)
53
+
#define BFM_RCC_CR_PLL3ON_V(v) BM_RCC_CR_PLL3ON
54
+
#define BP_RCC_CR_PLL2RDY 27
55
+
#define BM_RCC_CR_PLL2RDY 0x8000000
56
+
#define BF_RCC_CR_PLL2RDY(v) (((v) & 0x1) << 27)
57
+
#define BFM_RCC_CR_PLL2RDY(v) BM_RCC_CR_PLL2RDY
58
+
#define BF_RCC_CR_PLL2RDY_V(e) BF_RCC_CR_PLL2RDY(BV_RCC_CR_PLL2RDY__##e)
59
+
#define BFM_RCC_CR_PLL2RDY_V(v) BM_RCC_CR_PLL2RDY
60
+
#define BP_RCC_CR_PLL2ON 26
61
+
#define BM_RCC_CR_PLL2ON 0x4000000
62
+
#define BF_RCC_CR_PLL2ON(v) (((v) & 0x1) << 26)
63
+
#define BFM_RCC_CR_PLL2ON(v) BM_RCC_CR_PLL2ON
64
+
#define BF_RCC_CR_PLL2ON_V(e) BF_RCC_CR_PLL2ON(BV_RCC_CR_PLL2ON__##e)
65
+
#define BFM_RCC_CR_PLL2ON_V(v) BM_RCC_CR_PLL2ON
66
+
#define BP_RCC_CR_PLL1RDY 25
67
+
#define BM_RCC_CR_PLL1RDY 0x2000000
68
+
#define BF_RCC_CR_PLL1RDY(v) (((v) & 0x1) << 25)
69
+
#define BFM_RCC_CR_PLL1RDY(v) BM_RCC_CR_PLL1RDY
70
+
#define BF_RCC_CR_PLL1RDY_V(e) BF_RCC_CR_PLL1RDY(BV_RCC_CR_PLL1RDY__##e)
71
+
#define BFM_RCC_CR_PLL1RDY_V(v) BM_RCC_CR_PLL1RDY
72
+
#define BP_RCC_CR_PLL1ON 24
73
+
#define BM_RCC_CR_PLL1ON 0x1000000
74
+
#define BF_RCC_CR_PLL1ON(v) (((v) & 0x1) << 24)
75
+
#define BFM_RCC_CR_PLL1ON(v) BM_RCC_CR_PLL1ON
76
+
#define BF_RCC_CR_PLL1ON_V(e) BF_RCC_CR_PLL1ON(BV_RCC_CR_PLL1ON__##e)
77
+
#define BFM_RCC_CR_PLL1ON_V(v) BM_RCC_CR_PLL1ON
78
+
#define BP_RCC_CR_HSECSSON 19
79
+
#define BM_RCC_CR_HSECSSON 0x80000
80
+
#define BF_RCC_CR_HSECSSON(v) (((v) & 0x1) << 19)
81
+
#define BFM_RCC_CR_HSECSSON(v) BM_RCC_CR_HSECSSON
82
+
#define BF_RCC_CR_HSECSSON_V(e) BF_RCC_CR_HSECSSON(BV_RCC_CR_HSECSSON__##e)
83
+
#define BFM_RCC_CR_HSECSSON_V(v) BM_RCC_CR_HSECSSON
84
+
#define BP_RCC_CR_HSEBYP 18
85
+
#define BM_RCC_CR_HSEBYP 0x40000
86
+
#define BF_RCC_CR_HSEBYP(v) (((v) & 0x1) << 18)
87
+
#define BFM_RCC_CR_HSEBYP(v) BM_RCC_CR_HSEBYP
88
+
#define BF_RCC_CR_HSEBYP_V(e) BF_RCC_CR_HSEBYP(BV_RCC_CR_HSEBYP__##e)
89
+
#define BFM_RCC_CR_HSEBYP_V(v) BM_RCC_CR_HSEBYP
90
+
#define BP_RCC_CR_HSERDY 17
91
+
#define BM_RCC_CR_HSERDY 0x20000
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+
#define BF_RCC_CR_HSERDY(v) (((v) & 0x1) << 17)
93
+
#define BFM_RCC_CR_HSERDY(v) BM_RCC_CR_HSERDY
94
+
#define BF_RCC_CR_HSERDY_V(e) BF_RCC_CR_HSERDY(BV_RCC_CR_HSERDY__##e)
95
+
#define BFM_RCC_CR_HSERDY_V(v) BM_RCC_CR_HSERDY
96
+
#define BP_RCC_CR_HSEON 16
97
+
#define BM_RCC_CR_HSEON 0x10000
98
+
#define BF_RCC_CR_HSEON(v) (((v) & 0x1) << 16)
99
+
#define BFM_RCC_CR_HSEON(v) BM_RCC_CR_HSEON
100
+
#define BF_RCC_CR_HSEON_V(e) BF_RCC_CR_HSEON(BV_RCC_CR_HSEON__##e)
101
+
#define BFM_RCC_CR_HSEON_V(v) BM_RCC_CR_HSEON
102
+
#define BP_RCC_CR_D2CKRDY 15
103
+
#define BM_RCC_CR_D2CKRDY 0x8000
104
+
#define BF_RCC_CR_D2CKRDY(v) (((v) & 0x1) << 15)
105
+
#define BFM_RCC_CR_D2CKRDY(v) BM_RCC_CR_D2CKRDY
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+
#define BF_RCC_CR_D2CKRDY_V(e) BF_RCC_CR_D2CKRDY(BV_RCC_CR_D2CKRDY__##e)
107
+
#define BFM_RCC_CR_D2CKRDY_V(v) BM_RCC_CR_D2CKRDY
108
+
#define BP_RCC_CR_D1CKRDY 14
109
+
#define BM_RCC_CR_D1CKRDY 0x4000
110
+
#define BF_RCC_CR_D1CKRDY(v) (((v) & 0x1) << 14)
111
+
#define BFM_RCC_CR_D1CKRDY(v) BM_RCC_CR_D1CKRDY
112
+
#define BF_RCC_CR_D1CKRDY_V(e) BF_RCC_CR_D1CKRDY(BV_RCC_CR_D1CKRDY__##e)
113
+
#define BFM_RCC_CR_D1CKRDY_V(v) BM_RCC_CR_D1CKRDY
114
+
#define BP_RCC_CR_HSI48RDY 13
115
+
#define BM_RCC_CR_HSI48RDY 0x2000
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+
#define BF_RCC_CR_HSI48RDY(v) (((v) & 0x1) << 13)
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+
#define BFM_RCC_CR_HSI48RDY(v) BM_RCC_CR_HSI48RDY
118
+
#define BF_RCC_CR_HSI48RDY_V(e) BF_RCC_CR_HSI48RDY(BV_RCC_CR_HSI48RDY__##e)
119
+
#define BFM_RCC_CR_HSI48RDY_V(v) BM_RCC_CR_HSI48RDY
120
+
#define BP_RCC_CR_HSI48ON 12
121
+
#define BM_RCC_CR_HSI48ON 0x1000
122
+
#define BF_RCC_CR_HSI48ON(v) (((v) & 0x1) << 12)
123
+
#define BFM_RCC_CR_HSI48ON(v) BM_RCC_CR_HSI48ON
124
+
#define BF_RCC_CR_HSI48ON_V(e) BF_RCC_CR_HSI48ON(BV_RCC_CR_HSI48ON__##e)
125
+
#define BFM_RCC_CR_HSI48ON_V(v) BM_RCC_CR_HSI48ON
126
+
#define BP_RCC_CR_CSIKERON 9
127
+
#define BM_RCC_CR_CSIKERON 0x200
128
+
#define BF_RCC_CR_CSIKERON(v) (((v) & 0x1) << 9)
129
+
#define BFM_RCC_CR_CSIKERON(v) BM_RCC_CR_CSIKERON
130
+
#define BF_RCC_CR_CSIKERON_V(e) BF_RCC_CR_CSIKERON(BV_RCC_CR_CSIKERON__##e)
131
+
#define BFM_RCC_CR_CSIKERON_V(v) BM_RCC_CR_CSIKERON
132
+
#define BP_RCC_CR_CSIRDY 8
133
+
#define BM_RCC_CR_CSIRDY 0x100
134
+
#define BF_RCC_CR_CSIRDY(v) (((v) & 0x1) << 8)
135
+
#define BFM_RCC_CR_CSIRDY(v) BM_RCC_CR_CSIRDY
136
+
#define BF_RCC_CR_CSIRDY_V(e) BF_RCC_CR_CSIRDY(BV_RCC_CR_CSIRDY__##e)
137
+
#define BFM_RCC_CR_CSIRDY_V(v) BM_RCC_CR_CSIRDY
138
+
#define BP_RCC_CR_CSION 7
139
+
#define BM_RCC_CR_CSION 0x80
140
+
#define BF_RCC_CR_CSION(v) (((v) & 0x1) << 7)
141
+
#define BFM_RCC_CR_CSION(v) BM_RCC_CR_CSION
142
+
#define BF_RCC_CR_CSION_V(e) BF_RCC_CR_CSION(BV_RCC_CR_CSION__##e)
143
+
#define BFM_RCC_CR_CSION_V(v) BM_RCC_CR_CSION
144
+
#define BP_RCC_CR_HSIDIVF 5
145
+
#define BM_RCC_CR_HSIDIVF 0x20
146
+
#define BF_RCC_CR_HSIDIVF(v) (((v) & 0x1) << 5)
147
+
#define BFM_RCC_CR_HSIDIVF(v) BM_RCC_CR_HSIDIVF
148
+
#define BF_RCC_CR_HSIDIVF_V(e) BF_RCC_CR_HSIDIVF(BV_RCC_CR_HSIDIVF__##e)
149
+
#define BFM_RCC_CR_HSIDIVF_V(v) BM_RCC_CR_HSIDIVF
150
+
#define BP_RCC_CR_HSIRDY 2
151
+
#define BM_RCC_CR_HSIRDY 0x4
152
+
#define BF_RCC_CR_HSIRDY(v) (((v) & 0x1) << 2)
153
+
#define BFM_RCC_CR_HSIRDY(v) BM_RCC_CR_HSIRDY
154
+
#define BF_RCC_CR_HSIRDY_V(e) BF_RCC_CR_HSIRDY(BV_RCC_CR_HSIRDY__##e)
155
+
#define BFM_RCC_CR_HSIRDY_V(v) BM_RCC_CR_HSIRDY
156
+
#define BP_RCC_CR_HSIKERON 1
157
+
#define BM_RCC_CR_HSIKERON 0x2
158
+
#define BF_RCC_CR_HSIKERON(v) (((v) & 0x1) << 1)
159
+
#define BFM_RCC_CR_HSIKERON(v) BM_RCC_CR_HSIKERON
160
+
#define BF_RCC_CR_HSIKERON_V(e) BF_RCC_CR_HSIKERON(BV_RCC_CR_HSIKERON__##e)
161
+
#define BFM_RCC_CR_HSIKERON_V(v) BM_RCC_CR_HSIKERON
162
+
#define BP_RCC_CR_HSION 0
163
+
#define BM_RCC_CR_HSION 0x1
164
+
#define BF_RCC_CR_HSION(v) (((v) & 0x1) << 0)
165
+
#define BFM_RCC_CR_HSION(v) BM_RCC_CR_HSION
166
+
#define BF_RCC_CR_HSION_V(e) BF_RCC_CR_HSION(BV_RCC_CR_HSION__##e)
167
+
#define BFM_RCC_CR_HSION_V(v) BM_RCC_CR_HSION
168
+
169
+
#define REG_RCC_CFGR st_reg(RCC_CFGR)
170
+
#define STA_RCC_CFGR (0x58024400 + 0x10)
171
+
#define STO_RCC_CFGR (0x10)
172
+
#define STT_RCC_CFGR STIO_32_RW
173
+
#define STN_RCC_CFGR RCC_CFGR
174
+
#define BP_RCC_CFGR_MCO2 29
175
+
#define BM_RCC_CFGR_MCO2 0xe0000000
176
+
#define BV_RCC_CFGR_MCO2__SYSCLK 0x0
177
+
#define BV_RCC_CFGR_MCO2__PLL2P 0x1
178
+
#define BV_RCC_CFGR_MCO2__HSE 0x2
179
+
#define BV_RCC_CFGR_MCO2__PLL1P 0x3
180
+
#define BV_RCC_CFGR_MCO2__CSI 0x4
181
+
#define BV_RCC_CFGR_MCO2__LSI 0x5
182
+
#define BF_RCC_CFGR_MCO2(v) (((v) & 0x7) << 29)
183
+
#define BFM_RCC_CFGR_MCO2(v) BM_RCC_CFGR_MCO2
184
+
#define BF_RCC_CFGR_MCO2_V(e) BF_RCC_CFGR_MCO2(BV_RCC_CFGR_MCO2__##e)
185
+
#define BFM_RCC_CFGR_MCO2_V(v) BM_RCC_CFGR_MCO2
186
+
#define BP_RCC_CFGR_MCO2PRE 25
187
+
#define BM_RCC_CFGR_MCO2PRE 0x1e000000
188
+
#define BF_RCC_CFGR_MCO2PRE(v) (((v) & 0xf) << 25)
189
+
#define BFM_RCC_CFGR_MCO2PRE(v) BM_RCC_CFGR_MCO2PRE
190
+
#define BF_RCC_CFGR_MCO2PRE_V(e) BF_RCC_CFGR_MCO2PRE(BV_RCC_CFGR_MCO2PRE__##e)
191
+
#define BFM_RCC_CFGR_MCO2PRE_V(v) BM_RCC_CFGR_MCO2PRE
192
+
#define BP_RCC_CFGR_MCO1 22
193
+
#define BM_RCC_CFGR_MCO1 0x1c00000
194
+
#define BV_RCC_CFGR_MCO1__HSI 0x0
195
+
#define BV_RCC_CFGR_MCO1__LSE 0x1
196
+
#define BV_RCC_CFGR_MCO1__HSE 0x2
197
+
#define BV_RCC_CFGR_MCO1__PLL1Q 0x3
198
+
#define BV_RCC_CFGR_MCO1__HSI48 0x4
199
+
#define BF_RCC_CFGR_MCO1(v) (((v) & 0x7) << 22)
200
+
#define BFM_RCC_CFGR_MCO1(v) BM_RCC_CFGR_MCO1
201
+
#define BF_RCC_CFGR_MCO1_V(e) BF_RCC_CFGR_MCO1(BV_RCC_CFGR_MCO1__##e)
202
+
#define BFM_RCC_CFGR_MCO1_V(v) BM_RCC_CFGR_MCO1
203
+
#define BP_RCC_CFGR_MCO1PRE 18
204
+
#define BM_RCC_CFGR_MCO1PRE 0x3c0000
205
+
#define BF_RCC_CFGR_MCO1PRE(v) (((v) & 0xf) << 18)
206
+
#define BFM_RCC_CFGR_MCO1PRE(v) BM_RCC_CFGR_MCO1PRE
207
+
#define BF_RCC_CFGR_MCO1PRE_V(e) BF_RCC_CFGR_MCO1PRE(BV_RCC_CFGR_MCO1PRE__##e)
208
+
#define BFM_RCC_CFGR_MCO1PRE_V(v) BM_RCC_CFGR_MCO1PRE
209
+
#define BP_RCC_CFGR_RTCPRE 8
210
+
#define BM_RCC_CFGR_RTCPRE 0x3f00
211
+
#define BF_RCC_CFGR_RTCPRE(v) (((v) & 0x3f) << 8)
212
+
#define BFM_RCC_CFGR_RTCPRE(v) BM_RCC_CFGR_RTCPRE
213
+
#define BF_RCC_CFGR_RTCPRE_V(e) BF_RCC_CFGR_RTCPRE(BV_RCC_CFGR_RTCPRE__##e)
214
+
#define BFM_RCC_CFGR_RTCPRE_V(v) BM_RCC_CFGR_RTCPRE
215
+
#define BP_RCC_CFGR_SWS 3
216
+
#define BM_RCC_CFGR_SWS 0x38
217
+
#define BF_RCC_CFGR_SWS(v) (((v) & 0x7) << 3)
218
+
#define BFM_RCC_CFGR_SWS(v) BM_RCC_CFGR_SWS
219
+
#define BF_RCC_CFGR_SWS_V(e) BF_RCC_CFGR_SWS(BV_RCC_CFGR_SWS__##e)
220
+
#define BFM_RCC_CFGR_SWS_V(v) BM_RCC_CFGR_SWS
221
+
#define BP_RCC_CFGR_SW 0
222
+
#define BM_RCC_CFGR_SW 0x7
223
+
#define BV_RCC_CFGR_SW__HSI 0x0
224
+
#define BV_RCC_CFGR_SW__CSI 0x1
225
+
#define BV_RCC_CFGR_SW__HSE 0x2
226
+
#define BV_RCC_CFGR_SW__PLL1P 0x3
227
+
#define BF_RCC_CFGR_SW(v) (((v) & 0x7) << 0)
228
+
#define BFM_RCC_CFGR_SW(v) BM_RCC_CFGR_SW
229
+
#define BF_RCC_CFGR_SW_V(e) BF_RCC_CFGR_SW(BV_RCC_CFGR_SW__##e)
230
+
#define BFM_RCC_CFGR_SW_V(v) BM_RCC_CFGR_SW
231
+
#define BP_RCC_CFGR_TIMPRE 15
232
+
#define BM_RCC_CFGR_TIMPRE 0x8000
233
+
#define BF_RCC_CFGR_TIMPRE(v) (((v) & 0x1) << 15)
234
+
#define BFM_RCC_CFGR_TIMPRE(v) BM_RCC_CFGR_TIMPRE
235
+
#define BF_RCC_CFGR_TIMPRE_V(e) BF_RCC_CFGR_TIMPRE(BV_RCC_CFGR_TIMPRE__##e)
236
+
#define BFM_RCC_CFGR_TIMPRE_V(v) BM_RCC_CFGR_TIMPRE
237
+
#define BP_RCC_CFGR_HRTIMSEL 14
238
+
#define BM_RCC_CFGR_HRTIMSEL 0x4000
239
+
#define BF_RCC_CFGR_HRTIMSEL(v) (((v) & 0x1) << 14)
240
+
#define BFM_RCC_CFGR_HRTIMSEL(v) BM_RCC_CFGR_HRTIMSEL
241
+
#define BF_RCC_CFGR_HRTIMSEL_V(e) BF_RCC_CFGR_HRTIMSEL(BV_RCC_CFGR_HRTIMSEL__##e)
242
+
#define BFM_RCC_CFGR_HRTIMSEL_V(v) BM_RCC_CFGR_HRTIMSEL
243
+
#define BP_RCC_CFGR_STOPKERWUCK 7
244
+
#define BM_RCC_CFGR_STOPKERWUCK 0x80
245
+
#define BF_RCC_CFGR_STOPKERWUCK(v) (((v) & 0x1) << 7)
246
+
#define BFM_RCC_CFGR_STOPKERWUCK(v) BM_RCC_CFGR_STOPKERWUCK
247
+
#define BF_RCC_CFGR_STOPKERWUCK_V(e) BF_RCC_CFGR_STOPKERWUCK(BV_RCC_CFGR_STOPKERWUCK__##e)
248
+
#define BFM_RCC_CFGR_STOPKERWUCK_V(v) BM_RCC_CFGR_STOPKERWUCK
249
+
#define BP_RCC_CFGR_STOPWUCK 6
250
+
#define BM_RCC_CFGR_STOPWUCK 0x40
251
+
#define BF_RCC_CFGR_STOPWUCK(v) (((v) & 0x1) << 6)
252
+
#define BFM_RCC_CFGR_STOPWUCK(v) BM_RCC_CFGR_STOPWUCK
253
+
#define BF_RCC_CFGR_STOPWUCK_V(e) BF_RCC_CFGR_STOPWUCK(BV_RCC_CFGR_STOPWUCK__##e)
254
+
#define BFM_RCC_CFGR_STOPWUCK_V(v) BM_RCC_CFGR_STOPWUCK
255
+
256
+
#define REG_RCC_D1CFGR st_reg(RCC_D1CFGR)
257
+
#define STA_RCC_D1CFGR (0x58024400 + 0x18)
258
+
#define STO_RCC_D1CFGR (0x18)
259
+
#define STT_RCC_D1CFGR STIO_32_RW
260
+
#define STN_RCC_D1CFGR RCC_D1CFGR
261
+
#define BP_RCC_D1CFGR_D1CPRE 8
262
+
#define BM_RCC_D1CFGR_D1CPRE 0xf00
263
+
#define BF_RCC_D1CFGR_D1CPRE(v) (((v) & 0xf) << 8)
264
+
#define BFM_RCC_D1CFGR_D1CPRE(v) BM_RCC_D1CFGR_D1CPRE
265
+
#define BF_RCC_D1CFGR_D1CPRE_V(e) BF_RCC_D1CFGR_D1CPRE(BV_RCC_D1CFGR_D1CPRE__##e)
266
+
#define BFM_RCC_D1CFGR_D1CPRE_V(v) BM_RCC_D1CFGR_D1CPRE
267
+
#define BP_RCC_D1CFGR_D1PPRE 4
268
+
#define BM_RCC_D1CFGR_D1PPRE 0x70
269
+
#define BF_RCC_D1CFGR_D1PPRE(v) (((v) & 0x7) << 4)
270
+
#define BFM_RCC_D1CFGR_D1PPRE(v) BM_RCC_D1CFGR_D1PPRE
271
+
#define BF_RCC_D1CFGR_D1PPRE_V(e) BF_RCC_D1CFGR_D1PPRE(BV_RCC_D1CFGR_D1PPRE__##e)
272
+
#define BFM_RCC_D1CFGR_D1PPRE_V(v) BM_RCC_D1CFGR_D1PPRE
273
+
#define BP_RCC_D1CFGR_HPRE 0
274
+
#define BM_RCC_D1CFGR_HPRE 0x1f
275
+
#define BF_RCC_D1CFGR_HPRE(v) (((v) & 0x1f) << 0)
276
+
#define BFM_RCC_D1CFGR_HPRE(v) BM_RCC_D1CFGR_HPRE
277
+
#define BF_RCC_D1CFGR_HPRE_V(e) BF_RCC_D1CFGR_HPRE(BV_RCC_D1CFGR_HPRE__##e)
278
+
#define BFM_RCC_D1CFGR_HPRE_V(v) BM_RCC_D1CFGR_HPRE
279
+
280
+
#define REG_RCC_D2CFGR st_reg(RCC_D2CFGR)
281
+
#define STA_RCC_D2CFGR (0x58024400 + 0x1c)
282
+
#define STO_RCC_D2CFGR (0x1c)
283
+
#define STT_RCC_D2CFGR STIO_32_RW
284
+
#define STN_RCC_D2CFGR RCC_D2CFGR
285
+
#define BP_RCC_D2CFGR_D2PPRE2 8
286
+
#define BM_RCC_D2CFGR_D2PPRE2 0x700
287
+
#define BF_RCC_D2CFGR_D2PPRE2(v) (((v) & 0x7) << 8)
288
+
#define BFM_RCC_D2CFGR_D2PPRE2(v) BM_RCC_D2CFGR_D2PPRE2
289
+
#define BF_RCC_D2CFGR_D2PPRE2_V(e) BF_RCC_D2CFGR_D2PPRE2(BV_RCC_D2CFGR_D2PPRE2__##e)
290
+
#define BFM_RCC_D2CFGR_D2PPRE2_V(v) BM_RCC_D2CFGR_D2PPRE2
291
+
#define BP_RCC_D2CFGR_D2PPRE1 4
292
+
#define BM_RCC_D2CFGR_D2PPRE1 0x70
293
+
#define BF_RCC_D2CFGR_D2PPRE1(v) (((v) & 0x7) << 4)
294
+
#define BFM_RCC_D2CFGR_D2PPRE1(v) BM_RCC_D2CFGR_D2PPRE1
295
+
#define BF_RCC_D2CFGR_D2PPRE1_V(e) BF_RCC_D2CFGR_D2PPRE1(BV_RCC_D2CFGR_D2PPRE1__##e)
296
+
#define BFM_RCC_D2CFGR_D2PPRE1_V(v) BM_RCC_D2CFGR_D2PPRE1
297
+
298
+
#define REG_RCC_D3CFGR st_reg(RCC_D3CFGR)
299
+
#define STA_RCC_D3CFGR (0x58024400 + 0x20)
300
+
#define STO_RCC_D3CFGR (0x20)
301
+
#define STT_RCC_D3CFGR STIO_32_RW
302
+
#define STN_RCC_D3CFGR RCC_D3CFGR
303
+
#define BP_RCC_D3CFGR_D3PPRE 4
304
+
#define BM_RCC_D3CFGR_D3PPRE 0x70
305
+
#define BF_RCC_D3CFGR_D3PPRE(v) (((v) & 0x7) << 4)
306
+
#define BFM_RCC_D3CFGR_D3PPRE(v) BM_RCC_D3CFGR_D3PPRE
307
+
#define BF_RCC_D3CFGR_D3PPRE_V(e) BF_RCC_D3CFGR_D3PPRE(BV_RCC_D3CFGR_D3PPRE__##e)
308
+
#define BFM_RCC_D3CFGR_D3PPRE_V(v) BM_RCC_D3CFGR_D3PPRE
309
+
310
+
#define REG_RCC_PLLCKSELR st_reg(RCC_PLLCKSELR)
311
+
#define STA_RCC_PLLCKSELR (0x58024400 + 0x28)
312
+
#define STO_RCC_PLLCKSELR (0x28)
313
+
#define STT_RCC_PLLCKSELR STIO_32_RW
314
+
#define STN_RCC_PLLCKSELR RCC_PLLCKSELR
315
+
#define BP_RCC_PLLCKSELR_DIVM3 20
316
+
#define BM_RCC_PLLCKSELR_DIVM3 0x3f00000
317
+
#define BF_RCC_PLLCKSELR_DIVM3(v) (((v) & 0x3f) << 20)
318
+
#define BFM_RCC_PLLCKSELR_DIVM3(v) BM_RCC_PLLCKSELR_DIVM3
319
+
#define BF_RCC_PLLCKSELR_DIVM3_V(e) BF_RCC_PLLCKSELR_DIVM3(BV_RCC_PLLCKSELR_DIVM3__##e)
320
+
#define BFM_RCC_PLLCKSELR_DIVM3_V(v) BM_RCC_PLLCKSELR_DIVM3
321
+
#define BP_RCC_PLLCKSELR_DIVM2 12
322
+
#define BM_RCC_PLLCKSELR_DIVM2 0x3f000
323
+
#define BF_RCC_PLLCKSELR_DIVM2(v) (((v) & 0x3f) << 12)
324
+
#define BFM_RCC_PLLCKSELR_DIVM2(v) BM_RCC_PLLCKSELR_DIVM2
325
+
#define BF_RCC_PLLCKSELR_DIVM2_V(e) BF_RCC_PLLCKSELR_DIVM2(BV_RCC_PLLCKSELR_DIVM2__##e)
326
+
#define BFM_RCC_PLLCKSELR_DIVM2_V(v) BM_RCC_PLLCKSELR_DIVM2
327
+
#define BP_RCC_PLLCKSELR_DIVM1 4
328
+
#define BM_RCC_PLLCKSELR_DIVM1 0x3f0
329
+
#define BF_RCC_PLLCKSELR_DIVM1(v) (((v) & 0x3f) << 4)
330
+
#define BFM_RCC_PLLCKSELR_DIVM1(v) BM_RCC_PLLCKSELR_DIVM1
331
+
#define BF_RCC_PLLCKSELR_DIVM1_V(e) BF_RCC_PLLCKSELR_DIVM1(BV_RCC_PLLCKSELR_DIVM1__##e)
332
+
#define BFM_RCC_PLLCKSELR_DIVM1_V(v) BM_RCC_PLLCKSELR_DIVM1
333
+
#define BP_RCC_PLLCKSELR_PLLSRC 0
334
+
#define BM_RCC_PLLCKSELR_PLLSRC 0x3
335
+
#define BV_RCC_PLLCKSELR_PLLSRC__HSI 0x0
336
+
#define BV_RCC_PLLCKSELR_PLLSRC__CSI 0x1
337
+
#define BV_RCC_PLLCKSELR_PLLSRC__HSE 0x2
338
+
#define BV_RCC_PLLCKSELR_PLLSRC__NONE 0x3
339
+
#define BF_RCC_PLLCKSELR_PLLSRC(v) (((v) & 0x3) << 0)
340
+
#define BFM_RCC_PLLCKSELR_PLLSRC(v) BM_RCC_PLLCKSELR_PLLSRC
341
+
#define BF_RCC_PLLCKSELR_PLLSRC_V(e) BF_RCC_PLLCKSELR_PLLSRC(BV_RCC_PLLCKSELR_PLLSRC__##e)
342
+
#define BFM_RCC_PLLCKSELR_PLLSRC_V(v) BM_RCC_PLLCKSELR_PLLSRC
343
+
344
+
#define REG_RCC_PLLCFGR st_reg(RCC_PLLCFGR)
345
+
#define STA_RCC_PLLCFGR (0x58024400 + 0x2c)
346
+
#define STO_RCC_PLLCFGR (0x2c)
347
+
#define STT_RCC_PLLCFGR STIO_32_RW
348
+
#define STN_RCC_PLLCFGR RCC_PLLCFGR
349
+
#define BP_RCC_PLLCFGR_PLL3RGE 10
350
+
#define BM_RCC_PLLCFGR_PLL3RGE 0xc00
351
+
#define BV_RCC_PLLCFGR_PLL3RGE__1_2MHZ 0x0
352
+
#define BV_RCC_PLLCFGR_PLL3RGE__2_4MHz 0x1
353
+
#define BV_RCC_PLLCFGR_PLL3RGE__4_8MHz 0x2
354
+
#define BV_RCC_PLLCFGR_PLL3RGE__8_16MHz 0x3
355
+
#define BF_RCC_PLLCFGR_PLL3RGE(v) (((v) & 0x3) << 10)
356
+
#define BFM_RCC_PLLCFGR_PLL3RGE(v) BM_RCC_PLLCFGR_PLL3RGE
357
+
#define BF_RCC_PLLCFGR_PLL3RGE_V(e) BF_RCC_PLLCFGR_PLL3RGE(BV_RCC_PLLCFGR_PLL3RGE__##e)
358
+
#define BFM_RCC_PLLCFGR_PLL3RGE_V(v) BM_RCC_PLLCFGR_PLL3RGE
359
+
#define BP_RCC_PLLCFGR_PLL2RGE 6
360
+
#define BM_RCC_PLLCFGR_PLL2RGE 0xc0
361
+
#define BV_RCC_PLLCFGR_PLL2RGE__1_2MHZ 0x0
362
+
#define BV_RCC_PLLCFGR_PLL2RGE__2_4MHz 0x1
363
+
#define BV_RCC_PLLCFGR_PLL2RGE__4_8MHz 0x2
364
+
#define BV_RCC_PLLCFGR_PLL2RGE__8_16MHz 0x3
365
+
#define BF_RCC_PLLCFGR_PLL2RGE(v) (((v) & 0x3) << 6)
366
+
#define BFM_RCC_PLLCFGR_PLL2RGE(v) BM_RCC_PLLCFGR_PLL2RGE
367
+
#define BF_RCC_PLLCFGR_PLL2RGE_V(e) BF_RCC_PLLCFGR_PLL2RGE(BV_RCC_PLLCFGR_PLL2RGE__##e)
368
+
#define BFM_RCC_PLLCFGR_PLL2RGE_V(v) BM_RCC_PLLCFGR_PLL2RGE
369
+
#define BP_RCC_PLLCFGR_PLL1RGE 2
370
+
#define BM_RCC_PLLCFGR_PLL1RGE 0xc
371
+
#define BV_RCC_PLLCFGR_PLL1RGE__1_2MHZ 0x0
372
+
#define BV_RCC_PLLCFGR_PLL1RGE__2_4MHz 0x1
373
+
#define BV_RCC_PLLCFGR_PLL1RGE__4_8MHz 0x2
374
+
#define BV_RCC_PLLCFGR_PLL1RGE__8_16MHz 0x3
375
+
#define BF_RCC_PLLCFGR_PLL1RGE(v) (((v) & 0x3) << 2)
376
+
#define BFM_RCC_PLLCFGR_PLL1RGE(v) BM_RCC_PLLCFGR_PLL1RGE
377
+
#define BF_RCC_PLLCFGR_PLL1RGE_V(e) BF_RCC_PLLCFGR_PLL1RGE(BV_RCC_PLLCFGR_PLL1RGE__##e)
378
+
#define BFM_RCC_PLLCFGR_PLL1RGE_V(v) BM_RCC_PLLCFGR_PLL1RGE
379
+
#define BP_RCC_PLLCFGR_DIVR3EN 24
380
+
#define BM_RCC_PLLCFGR_DIVR3EN 0x1000000
381
+
#define BF_RCC_PLLCFGR_DIVR3EN(v) (((v) & 0x1) << 24)
382
+
#define BFM_RCC_PLLCFGR_DIVR3EN(v) BM_RCC_PLLCFGR_DIVR3EN
383
+
#define BF_RCC_PLLCFGR_DIVR3EN_V(e) BF_RCC_PLLCFGR_DIVR3EN(BV_RCC_PLLCFGR_DIVR3EN__##e)
384
+
#define BFM_RCC_PLLCFGR_DIVR3EN_V(v) BM_RCC_PLLCFGR_DIVR3EN
385
+
#define BP_RCC_PLLCFGR_DIVQ3EN 23
386
+
#define BM_RCC_PLLCFGR_DIVQ3EN 0x800000
387
+
#define BF_RCC_PLLCFGR_DIVQ3EN(v) (((v) & 0x1) << 23)
388
+
#define BFM_RCC_PLLCFGR_DIVQ3EN(v) BM_RCC_PLLCFGR_DIVQ3EN
389
+
#define BF_RCC_PLLCFGR_DIVQ3EN_V(e) BF_RCC_PLLCFGR_DIVQ3EN(BV_RCC_PLLCFGR_DIVQ3EN__##e)
390
+
#define BFM_RCC_PLLCFGR_DIVQ3EN_V(v) BM_RCC_PLLCFGR_DIVQ3EN
391
+
#define BP_RCC_PLLCFGR_DIVP3EN 22
392
+
#define BM_RCC_PLLCFGR_DIVP3EN 0x400000
393
+
#define BF_RCC_PLLCFGR_DIVP3EN(v) (((v) & 0x1) << 22)
394
+
#define BFM_RCC_PLLCFGR_DIVP3EN(v) BM_RCC_PLLCFGR_DIVP3EN
395
+
#define BF_RCC_PLLCFGR_DIVP3EN_V(e) BF_RCC_PLLCFGR_DIVP3EN(BV_RCC_PLLCFGR_DIVP3EN__##e)
396
+
#define BFM_RCC_PLLCFGR_DIVP3EN_V(v) BM_RCC_PLLCFGR_DIVP3EN
397
+
#define BP_RCC_PLLCFGR_DIVR2EN 21
398
+
#define BM_RCC_PLLCFGR_DIVR2EN 0x200000
399
+
#define BF_RCC_PLLCFGR_DIVR2EN(v) (((v) & 0x1) << 21)
400
+
#define BFM_RCC_PLLCFGR_DIVR2EN(v) BM_RCC_PLLCFGR_DIVR2EN
401
+
#define BF_RCC_PLLCFGR_DIVR2EN_V(e) BF_RCC_PLLCFGR_DIVR2EN(BV_RCC_PLLCFGR_DIVR2EN__##e)
402
+
#define BFM_RCC_PLLCFGR_DIVR2EN_V(v) BM_RCC_PLLCFGR_DIVR2EN
403
+
#define BP_RCC_PLLCFGR_DIVQ2EN 20
404
+
#define BM_RCC_PLLCFGR_DIVQ2EN 0x100000
405
+
#define BF_RCC_PLLCFGR_DIVQ2EN(v) (((v) & 0x1) << 20)
406
+
#define BFM_RCC_PLLCFGR_DIVQ2EN(v) BM_RCC_PLLCFGR_DIVQ2EN
407
+
#define BF_RCC_PLLCFGR_DIVQ2EN_V(e) BF_RCC_PLLCFGR_DIVQ2EN(BV_RCC_PLLCFGR_DIVQ2EN__##e)
408
+
#define BFM_RCC_PLLCFGR_DIVQ2EN_V(v) BM_RCC_PLLCFGR_DIVQ2EN
409
+
#define BP_RCC_PLLCFGR_DIVP2EN 19
410
+
#define BM_RCC_PLLCFGR_DIVP2EN 0x80000
411
+
#define BF_RCC_PLLCFGR_DIVP2EN(v) (((v) & 0x1) << 19)
412
+
#define BFM_RCC_PLLCFGR_DIVP2EN(v) BM_RCC_PLLCFGR_DIVP2EN
413
+
#define BF_RCC_PLLCFGR_DIVP2EN_V(e) BF_RCC_PLLCFGR_DIVP2EN(BV_RCC_PLLCFGR_DIVP2EN__##e)
414
+
#define BFM_RCC_PLLCFGR_DIVP2EN_V(v) BM_RCC_PLLCFGR_DIVP2EN
415
+
#define BP_RCC_PLLCFGR_DIVR1EN 18
416
+
#define BM_RCC_PLLCFGR_DIVR1EN 0x40000
417
+
#define BF_RCC_PLLCFGR_DIVR1EN(v) (((v) & 0x1) << 18)
418
+
#define BFM_RCC_PLLCFGR_DIVR1EN(v) BM_RCC_PLLCFGR_DIVR1EN
419
+
#define BF_RCC_PLLCFGR_DIVR1EN_V(e) BF_RCC_PLLCFGR_DIVR1EN(BV_RCC_PLLCFGR_DIVR1EN__##e)
420
+
#define BFM_RCC_PLLCFGR_DIVR1EN_V(v) BM_RCC_PLLCFGR_DIVR1EN
421
+
#define BP_RCC_PLLCFGR_DIVQ1EN 17
422
+
#define BM_RCC_PLLCFGR_DIVQ1EN 0x20000
423
+
#define BF_RCC_PLLCFGR_DIVQ1EN(v) (((v) & 0x1) << 17)
424
+
#define BFM_RCC_PLLCFGR_DIVQ1EN(v) BM_RCC_PLLCFGR_DIVQ1EN
425
+
#define BF_RCC_PLLCFGR_DIVQ1EN_V(e) BF_RCC_PLLCFGR_DIVQ1EN(BV_RCC_PLLCFGR_DIVQ1EN__##e)
426
+
#define BFM_RCC_PLLCFGR_DIVQ1EN_V(v) BM_RCC_PLLCFGR_DIVQ1EN
427
+
#define BP_RCC_PLLCFGR_DIVP1EN 16
428
+
#define BM_RCC_PLLCFGR_DIVP1EN 0x10000
429
+
#define BF_RCC_PLLCFGR_DIVP1EN(v) (((v) & 0x1) << 16)
430
+
#define BFM_RCC_PLLCFGR_DIVP1EN(v) BM_RCC_PLLCFGR_DIVP1EN
431
+
#define BF_RCC_PLLCFGR_DIVP1EN_V(e) BF_RCC_PLLCFGR_DIVP1EN(BV_RCC_PLLCFGR_DIVP1EN__##e)
432
+
#define BFM_RCC_PLLCFGR_DIVP1EN_V(v) BM_RCC_PLLCFGR_DIVP1EN
433
+
#define BP_RCC_PLLCFGR_PLL3VCOSEL 9
434
+
#define BM_RCC_PLLCFGR_PLL3VCOSEL 0x200
435
+
#define BV_RCC_PLLCFGR_PLL3VCOSEL__WIDE 0x0
436
+
#define BV_RCC_PLLCFGR_PLL3VCOSEL__MEDIUM 0x1
437
+
#define BF_RCC_PLLCFGR_PLL3VCOSEL(v) (((v) & 0x1) << 9)
438
+
#define BFM_RCC_PLLCFGR_PLL3VCOSEL(v) BM_RCC_PLLCFGR_PLL3VCOSEL
439
+
#define BF_RCC_PLLCFGR_PLL3VCOSEL_V(e) BF_RCC_PLLCFGR_PLL3VCOSEL(BV_RCC_PLLCFGR_PLL3VCOSEL__##e)
440
+
#define BFM_RCC_PLLCFGR_PLL3VCOSEL_V(v) BM_RCC_PLLCFGR_PLL3VCOSEL
441
+
#define BP_RCC_PLLCFGR_PLL3FRACEN 8
442
+
#define BM_RCC_PLLCFGR_PLL3FRACEN 0x100
443
+
#define BF_RCC_PLLCFGR_PLL3FRACEN(v) (((v) & 0x1) << 8)
444
+
#define BFM_RCC_PLLCFGR_PLL3FRACEN(v) BM_RCC_PLLCFGR_PLL3FRACEN
445
+
#define BF_RCC_PLLCFGR_PLL3FRACEN_V(e) BF_RCC_PLLCFGR_PLL3FRACEN(BV_RCC_PLLCFGR_PLL3FRACEN__##e)
446
+
#define BFM_RCC_PLLCFGR_PLL3FRACEN_V(v) BM_RCC_PLLCFGR_PLL3FRACEN
447
+
#define BP_RCC_PLLCFGR_PLL2VCOSEL 5
448
+
#define BM_RCC_PLLCFGR_PLL2VCOSEL 0x20
449
+
#define BV_RCC_PLLCFGR_PLL2VCOSEL__WIDE 0x0
450
+
#define BV_RCC_PLLCFGR_PLL2VCOSEL__MEDIUM 0x1
451
+
#define BF_RCC_PLLCFGR_PLL2VCOSEL(v) (((v) & 0x1) << 5)
452
+
#define BFM_RCC_PLLCFGR_PLL2VCOSEL(v) BM_RCC_PLLCFGR_PLL2VCOSEL
453
+
#define BF_RCC_PLLCFGR_PLL2VCOSEL_V(e) BF_RCC_PLLCFGR_PLL2VCOSEL(BV_RCC_PLLCFGR_PLL2VCOSEL__##e)
454
+
#define BFM_RCC_PLLCFGR_PLL2VCOSEL_V(v) BM_RCC_PLLCFGR_PLL2VCOSEL
455
+
#define BP_RCC_PLLCFGR_PLL2FRACEN 4
456
+
#define BM_RCC_PLLCFGR_PLL2FRACEN 0x10
457
+
#define BF_RCC_PLLCFGR_PLL2FRACEN(v) (((v) & 0x1) << 4)
458
+
#define BFM_RCC_PLLCFGR_PLL2FRACEN(v) BM_RCC_PLLCFGR_PLL2FRACEN
459
+
#define BF_RCC_PLLCFGR_PLL2FRACEN_V(e) BF_RCC_PLLCFGR_PLL2FRACEN(BV_RCC_PLLCFGR_PLL2FRACEN__##e)
460
+
#define BFM_RCC_PLLCFGR_PLL2FRACEN_V(v) BM_RCC_PLLCFGR_PLL2FRACEN
461
+
#define BP_RCC_PLLCFGR_PLL1VCOSEL 1
462
+
#define BM_RCC_PLLCFGR_PLL1VCOSEL 0x2
463
+
#define BV_RCC_PLLCFGR_PLL1VCOSEL__WIDE 0x0
464
+
#define BV_RCC_PLLCFGR_PLL1VCOSEL__MEDIUM 0x1
465
+
#define BF_RCC_PLLCFGR_PLL1VCOSEL(v) (((v) & 0x1) << 1)
466
+
#define BFM_RCC_PLLCFGR_PLL1VCOSEL(v) BM_RCC_PLLCFGR_PLL1VCOSEL
467
+
#define BF_RCC_PLLCFGR_PLL1VCOSEL_V(e) BF_RCC_PLLCFGR_PLL1VCOSEL(BV_RCC_PLLCFGR_PLL1VCOSEL__##e)
468
+
#define BFM_RCC_PLLCFGR_PLL1VCOSEL_V(v) BM_RCC_PLLCFGR_PLL1VCOSEL
469
+
#define BP_RCC_PLLCFGR_PLL1FRACEN 0
470
+
#define BM_RCC_PLLCFGR_PLL1FRACEN 0x1
471
+
#define BF_RCC_PLLCFGR_PLL1FRACEN(v) (((v) & 0x1) << 0)
472
+
#define BFM_RCC_PLLCFGR_PLL1FRACEN(v) BM_RCC_PLLCFGR_PLL1FRACEN
473
+
#define BF_RCC_PLLCFGR_PLL1FRACEN_V(e) BF_RCC_PLLCFGR_PLL1FRACEN(BV_RCC_PLLCFGR_PLL1FRACEN__##e)
474
+
#define BFM_RCC_PLLCFGR_PLL1FRACEN_V(v) BM_RCC_PLLCFGR_PLL1FRACEN
475
+
476
+
#define REG_RCC_PLL1DIVR st_reg(RCC_PLL1DIVR)
477
+
#define STA_RCC_PLL1DIVR (0x58024400 + 0x30)
478
+
#define STO_RCC_PLL1DIVR (0x30)
479
+
#define STT_RCC_PLL1DIVR STIO_32_RW
480
+
#define STN_RCC_PLL1DIVR RCC_PLL1DIVR
481
+
#define BP_RCC_PLL1DIVR_DIVR 24
482
+
#define BM_RCC_PLL1DIVR_DIVR 0x7f000000
483
+
#define BF_RCC_PLL1DIVR_DIVR(v) (((v) & 0x7f) << 24)
484
+
#define BFM_RCC_PLL1DIVR_DIVR(v) BM_RCC_PLL1DIVR_DIVR
485
+
#define BF_RCC_PLL1DIVR_DIVR_V(e) BF_RCC_PLL1DIVR_DIVR(BV_RCC_PLL1DIVR_DIVR__##e)
486
+
#define BFM_RCC_PLL1DIVR_DIVR_V(v) BM_RCC_PLL1DIVR_DIVR
487
+
#define BP_RCC_PLL1DIVR_DIVQ 16
488
+
#define BM_RCC_PLL1DIVR_DIVQ 0x7f0000
489
+
#define BF_RCC_PLL1DIVR_DIVQ(v) (((v) & 0x7f) << 16)
490
+
#define BFM_RCC_PLL1DIVR_DIVQ(v) BM_RCC_PLL1DIVR_DIVQ
491
+
#define BF_RCC_PLL1DIVR_DIVQ_V(e) BF_RCC_PLL1DIVR_DIVQ(BV_RCC_PLL1DIVR_DIVQ__##e)
492
+
#define BFM_RCC_PLL1DIVR_DIVQ_V(v) BM_RCC_PLL1DIVR_DIVQ
493
+
#define BP_RCC_PLL1DIVR_DIVP 9
494
+
#define BM_RCC_PLL1DIVR_DIVP 0xfe00
495
+
#define BF_RCC_PLL1DIVR_DIVP(v) (((v) & 0x7f) << 9)
496
+
#define BFM_RCC_PLL1DIVR_DIVP(v) BM_RCC_PLL1DIVR_DIVP
497
+
#define BF_RCC_PLL1DIVR_DIVP_V(e) BF_RCC_PLL1DIVR_DIVP(BV_RCC_PLL1DIVR_DIVP__##e)
498
+
#define BFM_RCC_PLL1DIVR_DIVP_V(v) BM_RCC_PLL1DIVR_DIVP
499
+
#define BP_RCC_PLL1DIVR_DIVN 0
500
+
#define BM_RCC_PLL1DIVR_DIVN 0x1ff
501
+
#define BF_RCC_PLL1DIVR_DIVN(v) (((v) & 0x1ff) << 0)
502
+
#define BFM_RCC_PLL1DIVR_DIVN(v) BM_RCC_PLL1DIVR_DIVN
503
+
#define BF_RCC_PLL1DIVR_DIVN_V(e) BF_RCC_PLL1DIVR_DIVN(BV_RCC_PLL1DIVR_DIVN__##e)
504
+
#define BFM_RCC_PLL1DIVR_DIVN_V(v) BM_RCC_PLL1DIVR_DIVN
505
+
506
+
#define REG_RCC_PLL2DIVR st_reg(RCC_PLL2DIVR)
507
+
#define STA_RCC_PLL2DIVR (0x58024400 + 0x38)
508
+
#define STO_RCC_PLL2DIVR (0x38)
509
+
#define STT_RCC_PLL2DIVR STIO_32_RW
510
+
#define STN_RCC_PLL2DIVR RCC_PLL2DIVR
511
+
#define BP_RCC_PLL2DIVR_DIVR 24
512
+
#define BM_RCC_PLL2DIVR_DIVR 0x7f000000
513
+
#define BF_RCC_PLL2DIVR_DIVR(v) (((v) & 0x7f) << 24)
514
+
#define BFM_RCC_PLL2DIVR_DIVR(v) BM_RCC_PLL2DIVR_DIVR
515
+
#define BF_RCC_PLL2DIVR_DIVR_V(e) BF_RCC_PLL2DIVR_DIVR(BV_RCC_PLL2DIVR_DIVR__##e)
516
+
#define BFM_RCC_PLL2DIVR_DIVR_V(v) BM_RCC_PLL2DIVR_DIVR
517
+
#define BP_RCC_PLL2DIVR_DIVQ 16
518
+
#define BM_RCC_PLL2DIVR_DIVQ 0x7f0000
519
+
#define BF_RCC_PLL2DIVR_DIVQ(v) (((v) & 0x7f) << 16)
520
+
#define BFM_RCC_PLL2DIVR_DIVQ(v) BM_RCC_PLL2DIVR_DIVQ
521
+
#define BF_RCC_PLL2DIVR_DIVQ_V(e) BF_RCC_PLL2DIVR_DIVQ(BV_RCC_PLL2DIVR_DIVQ__##e)
522
+
#define BFM_RCC_PLL2DIVR_DIVQ_V(v) BM_RCC_PLL2DIVR_DIVQ
523
+
#define BP_RCC_PLL2DIVR_DIVP 9
524
+
#define BM_RCC_PLL2DIVR_DIVP 0xfe00
525
+
#define BF_RCC_PLL2DIVR_DIVP(v) (((v) & 0x7f) << 9)
526
+
#define BFM_RCC_PLL2DIVR_DIVP(v) BM_RCC_PLL2DIVR_DIVP
527
+
#define BF_RCC_PLL2DIVR_DIVP_V(e) BF_RCC_PLL2DIVR_DIVP(BV_RCC_PLL2DIVR_DIVP__##e)
528
+
#define BFM_RCC_PLL2DIVR_DIVP_V(v) BM_RCC_PLL2DIVR_DIVP
529
+
#define BP_RCC_PLL2DIVR_DIVN 0
530
+
#define BM_RCC_PLL2DIVR_DIVN 0x1ff
531
+
#define BF_RCC_PLL2DIVR_DIVN(v) (((v) & 0x1ff) << 0)
532
+
#define BFM_RCC_PLL2DIVR_DIVN(v) BM_RCC_PLL2DIVR_DIVN
533
+
#define BF_RCC_PLL2DIVR_DIVN_V(e) BF_RCC_PLL2DIVR_DIVN(BV_RCC_PLL2DIVR_DIVN__##e)
534
+
#define BFM_RCC_PLL2DIVR_DIVN_V(v) BM_RCC_PLL2DIVR_DIVN
535
+
536
+
#define REG_RCC_PLL3DIVR st_reg(RCC_PLL3DIVR)
537
+
#define STA_RCC_PLL3DIVR (0x58024400 + 0x40)
538
+
#define STO_RCC_PLL3DIVR (0x40)
539
+
#define STT_RCC_PLL3DIVR STIO_32_RW
540
+
#define STN_RCC_PLL3DIVR RCC_PLL3DIVR
541
+
#define BP_RCC_PLL3DIVR_DIVR 24
542
+
#define BM_RCC_PLL3DIVR_DIVR 0x7f000000
543
+
#define BF_RCC_PLL3DIVR_DIVR(v) (((v) & 0x7f) << 24)
544
+
#define BFM_RCC_PLL3DIVR_DIVR(v) BM_RCC_PLL3DIVR_DIVR
545
+
#define BF_RCC_PLL3DIVR_DIVR_V(e) BF_RCC_PLL3DIVR_DIVR(BV_RCC_PLL3DIVR_DIVR__##e)
546
+
#define BFM_RCC_PLL3DIVR_DIVR_V(v) BM_RCC_PLL3DIVR_DIVR
547
+
#define BP_RCC_PLL3DIVR_DIVQ 16
548
+
#define BM_RCC_PLL3DIVR_DIVQ 0x7f0000
549
+
#define BF_RCC_PLL3DIVR_DIVQ(v) (((v) & 0x7f) << 16)
550
+
#define BFM_RCC_PLL3DIVR_DIVQ(v) BM_RCC_PLL3DIVR_DIVQ
551
+
#define BF_RCC_PLL3DIVR_DIVQ_V(e) BF_RCC_PLL3DIVR_DIVQ(BV_RCC_PLL3DIVR_DIVQ__##e)
552
+
#define BFM_RCC_PLL3DIVR_DIVQ_V(v) BM_RCC_PLL3DIVR_DIVQ
553
+
#define BP_RCC_PLL3DIVR_DIVP 9
554
+
#define BM_RCC_PLL3DIVR_DIVP 0xfe00
555
+
#define BF_RCC_PLL3DIVR_DIVP(v) (((v) & 0x7f) << 9)
556
+
#define BFM_RCC_PLL3DIVR_DIVP(v) BM_RCC_PLL3DIVR_DIVP
557
+
#define BF_RCC_PLL3DIVR_DIVP_V(e) BF_RCC_PLL3DIVR_DIVP(BV_RCC_PLL3DIVR_DIVP__##e)
558
+
#define BFM_RCC_PLL3DIVR_DIVP_V(v) BM_RCC_PLL3DIVR_DIVP
559
+
#define BP_RCC_PLL3DIVR_DIVN 0
560
+
#define BM_RCC_PLL3DIVR_DIVN 0x1ff
561
+
#define BF_RCC_PLL3DIVR_DIVN(v) (((v) & 0x1ff) << 0)
562
+
#define BFM_RCC_PLL3DIVR_DIVN(v) BM_RCC_PLL3DIVR_DIVN
563
+
#define BF_RCC_PLL3DIVR_DIVN_V(e) BF_RCC_PLL3DIVR_DIVN(BV_RCC_PLL3DIVR_DIVN__##e)
564
+
#define BFM_RCC_PLL3DIVR_DIVN_V(v) BM_RCC_PLL3DIVR_DIVN
565
+
566
+
#define REG_RCC_PLL1FRACR st_reg(RCC_PLL1FRACR)
567
+
#define STA_RCC_PLL1FRACR (0x58024400 + 0x34)
568
+
#define STO_RCC_PLL1FRACR (0x34)
569
+
#define STT_RCC_PLL1FRACR STIO_32_RW
570
+
#define STN_RCC_PLL1FRACR RCC_PLL1FRACR
571
+
#define BP_RCC_PLL1FRACR_FRACN 3
572
+
#define BM_RCC_PLL1FRACR_FRACN 0xfff8
573
+
#define BF_RCC_PLL1FRACR_FRACN(v) (((v) & 0x1fff) << 3)
574
+
#define BFM_RCC_PLL1FRACR_FRACN(v) BM_RCC_PLL1FRACR_FRACN
575
+
#define BF_RCC_PLL1FRACR_FRACN_V(e) BF_RCC_PLL1FRACR_FRACN(BV_RCC_PLL1FRACR_FRACN__##e)
576
+
#define BFM_RCC_PLL1FRACR_FRACN_V(v) BM_RCC_PLL1FRACR_FRACN
577
+
578
+
#define REG_RCC_PLL2FRACR st_reg(RCC_PLL2FRACR)
579
+
#define STA_RCC_PLL2FRACR (0x58024400 + 0x3c)
580
+
#define STO_RCC_PLL2FRACR (0x3c)
581
+
#define STT_RCC_PLL2FRACR STIO_32_RW
582
+
#define STN_RCC_PLL2FRACR RCC_PLL2FRACR
583
+
#define BP_RCC_PLL2FRACR_FRACN 3
584
+
#define BM_RCC_PLL2FRACR_FRACN 0xfff8
585
+
#define BF_RCC_PLL2FRACR_FRACN(v) (((v) & 0x1fff) << 3)
586
+
#define BFM_RCC_PLL2FRACR_FRACN(v) BM_RCC_PLL2FRACR_FRACN
587
+
#define BF_RCC_PLL2FRACR_FRACN_V(e) BF_RCC_PLL2FRACR_FRACN(BV_RCC_PLL2FRACR_FRACN__##e)
588
+
#define BFM_RCC_PLL2FRACR_FRACN_V(v) BM_RCC_PLL2FRACR_FRACN
589
+
590
+
#define REG_RCC_PLL3FRACR st_reg(RCC_PLL3FRACR)
591
+
#define STA_RCC_PLL3FRACR (0x58024400 + 0x44)
592
+
#define STO_RCC_PLL3FRACR (0x44)
593
+
#define STT_RCC_PLL3FRACR STIO_32_RW
594
+
#define STN_RCC_PLL3FRACR RCC_PLL3FRACR
595
+
#define BP_RCC_PLL3FRACR_FRACN 3
596
+
#define BM_RCC_PLL3FRACR_FRACN 0xfff8
597
+
#define BF_RCC_PLL3FRACR_FRACN(v) (((v) & 0x1fff) << 3)
598
+
#define BFM_RCC_PLL3FRACR_FRACN(v) BM_RCC_PLL3FRACR_FRACN
599
+
#define BF_RCC_PLL3FRACR_FRACN_V(e) BF_RCC_PLL3FRACR_FRACN(BV_RCC_PLL3FRACR_FRACN__##e)
600
+
#define BFM_RCC_PLL3FRACR_FRACN_V(v) BM_RCC_PLL3FRACR_FRACN
601
+
602
+
#define REG_RCC_D1CCIPR st_reg(RCC_D1CCIPR)
603
+
#define STA_RCC_D1CCIPR (0x58024400 + 0x4c)
604
+
#define STO_RCC_D1CCIPR (0x4c)
605
+
#define STT_RCC_D1CCIPR STIO_32_RW
606
+
#define STN_RCC_D1CCIPR RCC_D1CCIPR
607
+
#define BP_RCC_D1CCIPR_CKPERSEL 28
608
+
#define BM_RCC_D1CCIPR_CKPERSEL 0x30000000
609
+
#define BV_RCC_D1CCIPR_CKPERSEL__HSI 0x0
610
+
#define BV_RCC_D1CCIPR_CKPERSEL__CSI 0x1
611
+
#define BV_RCC_D1CCIPR_CKPERSEL__HSE 0x2
612
+
#define BF_RCC_D1CCIPR_CKPERSEL(v) (((v) & 0x3) << 28)
613
+
#define BFM_RCC_D1CCIPR_CKPERSEL(v) BM_RCC_D1CCIPR_CKPERSEL
614
+
#define BF_RCC_D1CCIPR_CKPERSEL_V(e) BF_RCC_D1CCIPR_CKPERSEL(BV_RCC_D1CCIPR_CKPERSEL__##e)
615
+
#define BFM_RCC_D1CCIPR_CKPERSEL_V(v) BM_RCC_D1CCIPR_CKPERSEL
616
+
#define BP_RCC_D1CCIPR_QSPISEL 4
617
+
#define BM_RCC_D1CCIPR_QSPISEL 0x30
618
+
#define BV_RCC_D1CCIPR_QSPISEL__AHB 0x0
619
+
#define BV_RCC_D1CCIPR_QSPISEL__PLL1Q 0x1
620
+
#define BV_RCC_D1CCIPR_QSPISEL__PLL2R 0x2
621
+
#define BV_RCC_D1CCIPR_QSPISEL__PER 0x3
622
+
#define BF_RCC_D1CCIPR_QSPISEL(v) (((v) & 0x3) << 4)
623
+
#define BFM_RCC_D1CCIPR_QSPISEL(v) BM_RCC_D1CCIPR_QSPISEL
624
+
#define BF_RCC_D1CCIPR_QSPISEL_V(e) BF_RCC_D1CCIPR_QSPISEL(BV_RCC_D1CCIPR_QSPISEL__##e)
625
+
#define BFM_RCC_D1CCIPR_QSPISEL_V(v) BM_RCC_D1CCIPR_QSPISEL
626
+
#define BP_RCC_D1CCIPR_FMCSEL 0
627
+
#define BM_RCC_D1CCIPR_FMCSEL 0x3
628
+
#define BV_RCC_D1CCIPR_FMCSEL__AHB 0x0
629
+
#define BV_RCC_D1CCIPR_FMCSEL__PLL1Q 0x1
630
+
#define BV_RCC_D1CCIPR_FMCSEL__PLL2R 0x2
631
+
#define BV_RCC_D1CCIPR_FMCSEL__PER 0x3
632
+
#define BF_RCC_D1CCIPR_FMCSEL(v) (((v) & 0x3) << 0)
633
+
#define BFM_RCC_D1CCIPR_FMCSEL(v) BM_RCC_D1CCIPR_FMCSEL
634
+
#define BF_RCC_D1CCIPR_FMCSEL_V(e) BF_RCC_D1CCIPR_FMCSEL(BV_RCC_D1CCIPR_FMCSEL__##e)
635
+
#define BFM_RCC_D1CCIPR_FMCSEL_V(v) BM_RCC_D1CCIPR_FMCSEL
636
+
#define BP_RCC_D1CCIPR_SDMMCSEL 16
637
+
#define BM_RCC_D1CCIPR_SDMMCSEL 0x10000
638
+
#define BV_RCC_D1CCIPR_SDMMCSEL__PLL1Q 0x0
639
+
#define BV_RCC_D1CCIPR_SDMMCSEL__PLL2R 0x1
640
+
#define BF_RCC_D1CCIPR_SDMMCSEL(v) (((v) & 0x1) << 16)
641
+
#define BFM_RCC_D1CCIPR_SDMMCSEL(v) BM_RCC_D1CCIPR_SDMMCSEL
642
+
#define BF_RCC_D1CCIPR_SDMMCSEL_V(e) BF_RCC_D1CCIPR_SDMMCSEL(BV_RCC_D1CCIPR_SDMMCSEL__##e)
643
+
#define BFM_RCC_D1CCIPR_SDMMCSEL_V(v) BM_RCC_D1CCIPR_SDMMCSEL
644
+
645
+
#define REG_RCC_D2CCIP1R st_reg(RCC_D2CCIP1R)
646
+
#define STA_RCC_D2CCIP1R (0x58024400 + 0x50)
647
+
#define STO_RCC_D2CCIP1R (0x50)
648
+
#define STT_RCC_D2CCIP1R STIO_32_RW
649
+
#define STN_RCC_D2CCIP1R RCC_D2CCIP1R
650
+
#define BP_RCC_D2CCIP1R_FDCANSEL 28
651
+
#define BM_RCC_D2CCIP1R_FDCANSEL 0x30000000
652
+
#define BV_RCC_D2CCIP1R_FDCANSEL__HSE 0x0
653
+
#define BV_RCC_D2CCIP1R_FDCANSEL__PLL1Q 0x1
654
+
#define BV_RCC_D2CCIP1R_FDCANSEL__PLL2Q 0x1
655
+
#define BF_RCC_D2CCIP1R_FDCANSEL(v) (((v) & 0x3) << 28)
656
+
#define BFM_RCC_D2CCIP1R_FDCANSEL(v) BM_RCC_D2CCIP1R_FDCANSEL
657
+
#define BF_RCC_D2CCIP1R_FDCANSEL_V(e) BF_RCC_D2CCIP1R_FDCANSEL(BV_RCC_D2CCIP1R_FDCANSEL__##e)
658
+
#define BFM_RCC_D2CCIP1R_FDCANSEL_V(v) BM_RCC_D2CCIP1R_FDCANSEL
659
+
#define BP_RCC_D2CCIP1R_SPDIFSEL 20
660
+
#define BM_RCC_D2CCIP1R_SPDIFSEL 0x300000
661
+
#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL1Q 0x0
662
+
#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL2R 0x1
663
+
#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL3R 0x2
664
+
#define BV_RCC_D2CCIP1R_SPDIFSEL__HSI 0x3
665
+
#define BF_RCC_D2CCIP1R_SPDIFSEL(v) (((v) & 0x3) << 20)
666
+
#define BFM_RCC_D2CCIP1R_SPDIFSEL(v) BM_RCC_D2CCIP1R_SPDIFSEL
667
+
#define BF_RCC_D2CCIP1R_SPDIFSEL_V(e) BF_RCC_D2CCIP1R_SPDIFSEL(BV_RCC_D2CCIP1R_SPDIFSEL__##e)
668
+
#define BFM_RCC_D2CCIP1R_SPDIFSEL_V(v) BM_RCC_D2CCIP1R_SPDIFSEL
669
+
#define BP_RCC_D2CCIP1R_SPI45SEL 16
670
+
#define BM_RCC_D2CCIP1R_SPI45SEL 0x70000
671
+
#define BV_RCC_D2CCIP1R_SPI45SEL__APB2 0x0
672
+
#define BV_RCC_D2CCIP1R_SPI45SEL__PLL2Q 0x1
673
+
#define BV_RCC_D2CCIP1R_SPI45SEL__PLL3Q 0x2
674
+
#define BV_RCC_D2CCIP1R_SPI45SEL__HSI 0x3
675
+
#define BV_RCC_D2CCIP1R_SPI45SEL__CSI 0x4
676
+
#define BV_RCC_D2CCIP1R_SPI45SEL__HSE 0x5
677
+
#define BF_RCC_D2CCIP1R_SPI45SEL(v) (((v) & 0x7) << 16)
678
+
#define BFM_RCC_D2CCIP1R_SPI45SEL(v) BM_RCC_D2CCIP1R_SPI45SEL
679
+
#define BF_RCC_D2CCIP1R_SPI45SEL_V(e) BF_RCC_D2CCIP1R_SPI45SEL(BV_RCC_D2CCIP1R_SPI45SEL__##e)
680
+
#define BFM_RCC_D2CCIP1R_SPI45SEL_V(v) BM_RCC_D2CCIP1R_SPI45SEL
681
+
#define BP_RCC_D2CCIP1R_SPI123SEL 12
682
+
#define BM_RCC_D2CCIP1R_SPI123SEL 0x7000
683
+
#define BV_RCC_D2CCIP1R_SPI123SEL__PLL1Q 0x0
684
+
#define BV_RCC_D2CCIP1R_SPI123SEL__PLL2P 0x1
685
+
#define BV_RCC_D2CCIP1R_SPI123SEL__PLL3P 0x2
686
+
#define BV_RCC_D2CCIP1R_SPI123SEL__I2SCKIN 0x3
687
+
#define BV_RCC_D2CCIP1R_SPI123SEL__PER 0x4
688
+
#define BF_RCC_D2CCIP1R_SPI123SEL(v) (((v) & 0x7) << 12)
689
+
#define BFM_RCC_D2CCIP1R_SPI123SEL(v) BM_RCC_D2CCIP1R_SPI123SEL
690
+
#define BF_RCC_D2CCIP1R_SPI123SEL_V(e) BF_RCC_D2CCIP1R_SPI123SEL(BV_RCC_D2CCIP1R_SPI123SEL__##e)
691
+
#define BFM_RCC_D2CCIP1R_SPI123SEL_V(v) BM_RCC_D2CCIP1R_SPI123SEL
692
+
#define BP_RCC_D2CCIP1R_SAI23SEL 6
693
+
#define BM_RCC_D2CCIP1R_SAI23SEL 0x1c0
694
+
#define BV_RCC_D2CCIP1R_SAI23SEL__PLL1Q 0x0
695
+
#define BV_RCC_D2CCIP1R_SAI23SEL__PLL2P 0x1
696
+
#define BV_RCC_D2CCIP1R_SAI23SEL__PLL3P 0x2
697
+
#define BV_RCC_D2CCIP1R_SAI23SEL__I2SCKIN 0x4
698
+
#define BV_RCC_D2CCIP1R_SAI23SEL__PER 0x4
699
+
#define BF_RCC_D2CCIP1R_SAI23SEL(v) (((v) & 0x7) << 6)
700
+
#define BFM_RCC_D2CCIP1R_SAI23SEL(v) BM_RCC_D2CCIP1R_SAI23SEL
701
+
#define BF_RCC_D2CCIP1R_SAI23SEL_V(e) BF_RCC_D2CCIP1R_SAI23SEL(BV_RCC_D2CCIP1R_SAI23SEL__##e)
702
+
#define BFM_RCC_D2CCIP1R_SAI23SEL_V(v) BM_RCC_D2CCIP1R_SAI23SEL
703
+
#define BP_RCC_D2CCIP1R_SAI1SEL 0
704
+
#define BM_RCC_D2CCIP1R_SAI1SEL 0x7
705
+
#define BV_RCC_D2CCIP1R_SAI1SEL__PLL1Q 0x0
706
+
#define BV_RCC_D2CCIP1R_SAI1SEL__PLL2P 0x1
707
+
#define BV_RCC_D2CCIP1R_SAI1SEL__PLL3P 0x2
708
+
#define BV_RCC_D2CCIP1R_SAI1SEL__I2SCKIN 0x4
709
+
#define BV_RCC_D2CCIP1R_SAI1SEL__PER 0x4
710
+
#define BF_RCC_D2CCIP1R_SAI1SEL(v) (((v) & 0x7) << 0)
711
+
#define BFM_RCC_D2CCIP1R_SAI1SEL(v) BM_RCC_D2CCIP1R_SAI1SEL
712
+
#define BF_RCC_D2CCIP1R_SAI1SEL_V(e) BF_RCC_D2CCIP1R_SAI1SEL(BV_RCC_D2CCIP1R_SAI1SEL__##e)
713
+
#define BFM_RCC_D2CCIP1R_SAI1SEL_V(v) BM_RCC_D2CCIP1R_SAI1SEL
714
+
#define BP_RCC_D2CCIP1R_SWPSEL 31
715
+
#define BM_RCC_D2CCIP1R_SWPSEL 0x80000000
716
+
#define BV_RCC_D2CCIP1R_SWPSEL__APB1 0x0
717
+
#define BV_RCC_D2CCIP1R_SWPSEL__HSI 0x1
718
+
#define BF_RCC_D2CCIP1R_SWPSEL(v) (((v) & 0x1) << 31)
719
+
#define BFM_RCC_D2CCIP1R_SWPSEL(v) BM_RCC_D2CCIP1R_SWPSEL
720
+
#define BF_RCC_D2CCIP1R_SWPSEL_V(e) BF_RCC_D2CCIP1R_SWPSEL(BV_RCC_D2CCIP1R_SWPSEL__##e)
721
+
#define BFM_RCC_D2CCIP1R_SWPSEL_V(v) BM_RCC_D2CCIP1R_SWPSEL
722
+
#define BP_RCC_D2CCIP1R_DFSDM1SEL 24
723
+
#define BM_RCC_D2CCIP1R_DFSDM1SEL 0x1000000
724
+
#define BV_RCC_D2CCIP1R_DFSDM1SEL__APB2 0x0
725
+
#define BV_RCC_D2CCIP1R_DFSDM1SEL__SYSCLK 0x1
726
+
#define BF_RCC_D2CCIP1R_DFSDM1SEL(v) (((v) & 0x1) << 24)
727
+
#define BFM_RCC_D2CCIP1R_DFSDM1SEL(v) BM_RCC_D2CCIP1R_DFSDM1SEL
728
+
#define BF_RCC_D2CCIP1R_DFSDM1SEL_V(e) BF_RCC_D2CCIP1R_DFSDM1SEL(BV_RCC_D2CCIP1R_DFSDM1SEL__##e)
729
+
#define BFM_RCC_D2CCIP1R_DFSDM1SEL_V(v) BM_RCC_D2CCIP1R_DFSDM1SEL
730
+
731
+
#define REG_RCC_D2CCIP2R st_reg(RCC_D2CCIP2R)
732
+
#define STA_RCC_D2CCIP2R (0x58024400 + 0x54)
733
+
#define STO_RCC_D2CCIP2R (0x54)
734
+
#define STT_RCC_D2CCIP2R STIO_32_RW
735
+
#define STN_RCC_D2CCIP2R RCC_D2CCIP2R
736
+
#define BP_RCC_D2CCIP2R_LPTIM1SEL 28
737
+
#define BM_RCC_D2CCIP2R_LPTIM1SEL 0x70000000
738
+
#define BV_RCC_D2CCIP2R_LPTIM1SEL__APB1 0x0
739
+
#define BV_RCC_D2CCIP2R_LPTIM1SEL__PLL2P 0x1
740
+
#define BV_RCC_D2CCIP2R_LPTIM1SEL__PLL3R 0x2
741
+
#define BV_RCC_D2CCIP2R_LPTIM1SEL__LSE 0x3
742
+
#define BV_RCC_D2CCIP2R_LPTIM1SEL__LSI 0x4
743
+
#define BV_RCC_D2CCIP2R_LPTIM1SEL__PER 0x5
744
+
#define BF_RCC_D2CCIP2R_LPTIM1SEL(v) (((v) & 0x7) << 28)
745
+
#define BFM_RCC_D2CCIP2R_LPTIM1SEL(v) BM_RCC_D2CCIP2R_LPTIM1SEL
746
+
#define BF_RCC_D2CCIP2R_LPTIM1SEL_V(e) BF_RCC_D2CCIP2R_LPTIM1SEL(BV_RCC_D2CCIP2R_LPTIM1SEL__##e)
747
+
#define BFM_RCC_D2CCIP2R_LPTIM1SEL_V(v) BM_RCC_D2CCIP2R_LPTIM1SEL
748
+
#define BP_RCC_D2CCIP2R_CECSEL 22
749
+
#define BM_RCC_D2CCIP2R_CECSEL 0xc00000
750
+
#define BV_RCC_D2CCIP2R_CECSEL__LSE 0x0
751
+
#define BV_RCC_D2CCIP2R_CECSEL__LSI 0x1
752
+
#define BV_RCC_D2CCIP2R_CECSEL__CSI 0x2
753
+
#define BF_RCC_D2CCIP2R_CECSEL(v) (((v) & 0x3) << 22)
754
+
#define BFM_RCC_D2CCIP2R_CECSEL(v) BM_RCC_D2CCIP2R_CECSEL
755
+
#define BF_RCC_D2CCIP2R_CECSEL_V(e) BF_RCC_D2CCIP2R_CECSEL(BV_RCC_D2CCIP2R_CECSEL__##e)
756
+
#define BFM_RCC_D2CCIP2R_CECSEL_V(v) BM_RCC_D2CCIP2R_CECSEL
757
+
#define BP_RCC_D2CCIP2R_USBSEL 20
758
+
#define BM_RCC_D2CCIP2R_USBSEL 0x300000
759
+
#define BV_RCC_D2CCIP2R_USBSEL__DISABLE 0x0
760
+
#define BV_RCC_D2CCIP2R_USBSEL__PLL1Q 0x1
761
+
#define BV_RCC_D2CCIP2R_USBSEL__PLL3Q 0x2
762
+
#define BV_RCC_D2CCIP2R_USBSEL__HSI48 0x3
763
+
#define BF_RCC_D2CCIP2R_USBSEL(v) (((v) & 0x3) << 20)
764
+
#define BFM_RCC_D2CCIP2R_USBSEL(v) BM_RCC_D2CCIP2R_USBSEL
765
+
#define BF_RCC_D2CCIP2R_USBSEL_V(e) BF_RCC_D2CCIP2R_USBSEL(BV_RCC_D2CCIP2R_USBSEL__##e)
766
+
#define BFM_RCC_D2CCIP2R_USBSEL_V(v) BM_RCC_D2CCIP2R_USBSEL
767
+
#define BP_RCC_D2CCIP2R_I2C123SEL 12
768
+
#define BM_RCC_D2CCIP2R_I2C123SEL 0x3000
769
+
#define BV_RCC_D2CCIP2R_I2C123SEL__APB1 0x0
770
+
#define BV_RCC_D2CCIP2R_I2C123SEL__PLL3R 0x1
771
+
#define BV_RCC_D2CCIP2R_I2C123SEL__HSI 0x2
772
+
#define BV_RCC_D2CCIP2R_I2C123SEL__CSI 0x3
773
+
#define BF_RCC_D2CCIP2R_I2C123SEL(v) (((v) & 0x3) << 12)
774
+
#define BFM_RCC_D2CCIP2R_I2C123SEL(v) BM_RCC_D2CCIP2R_I2C123SEL
775
+
#define BF_RCC_D2CCIP2R_I2C123SEL_V(e) BF_RCC_D2CCIP2R_I2C123SEL(BV_RCC_D2CCIP2R_I2C123SEL__##e)
776
+
#define BFM_RCC_D2CCIP2R_I2C123SEL_V(v) BM_RCC_D2CCIP2R_I2C123SEL
777
+
#define BP_RCC_D2CCIP2R_RNGSEL 8
778
+
#define BM_RCC_D2CCIP2R_RNGSEL 0x300
779
+
#define BV_RCC_D2CCIP2R_RNGSEL__HSI 0x0
780
+
#define BV_RCC_D2CCIP2R_RNGSEL__PLL1Q 0x1
781
+
#define BV_RCC_D2CCIP2R_RNGSEL__LSE 0x2
782
+
#define BV_RCC_D2CCIP2R_RNGSEL__LSI 0x3
783
+
#define BF_RCC_D2CCIP2R_RNGSEL(v) (((v) & 0x3) << 8)
784
+
#define BFM_RCC_D2CCIP2R_RNGSEL(v) BM_RCC_D2CCIP2R_RNGSEL
785
+
#define BF_RCC_D2CCIP2R_RNGSEL_V(e) BF_RCC_D2CCIP2R_RNGSEL(BV_RCC_D2CCIP2R_RNGSEL__##e)
786
+
#define BFM_RCC_D2CCIP2R_RNGSEL_V(v) BM_RCC_D2CCIP2R_RNGSEL
787
+
#define BP_RCC_D2CCIP2R_USART16SEL 3
788
+
#define BM_RCC_D2CCIP2R_USART16SEL 0x38
789
+
#define BV_RCC_D2CCIP2R_USART16SEL__APB2 0x0
790
+
#define BV_RCC_D2CCIP2R_USART16SEL__PLL2Q 0x1
791
+
#define BV_RCC_D2CCIP2R_USART16SEL__PLL3Q 0x2
792
+
#define BV_RCC_D2CCIP2R_USART16SEL__HSI 0x3
793
+
#define BV_RCC_D2CCIP2R_USART16SEL__CSI 0x4
794
+
#define BV_RCC_D2CCIP2R_USART16SEL__LSE 0x5
795
+
#define BF_RCC_D2CCIP2R_USART16SEL(v) (((v) & 0x7) << 3)
796
+
#define BFM_RCC_D2CCIP2R_USART16SEL(v) BM_RCC_D2CCIP2R_USART16SEL
797
+
#define BF_RCC_D2CCIP2R_USART16SEL_V(e) BF_RCC_D2CCIP2R_USART16SEL(BV_RCC_D2CCIP2R_USART16SEL__##e)
798
+
#define BFM_RCC_D2CCIP2R_USART16SEL_V(v) BM_RCC_D2CCIP2R_USART16SEL
799
+
#define BP_RCC_D2CCIP2R_USART234578SEL 0
800
+
#define BM_RCC_D2CCIP2R_USART234578SEL 0x7
801
+
#define BV_RCC_D2CCIP2R_USART234578SEL__APB1 0x0
802
+
#define BV_RCC_D2CCIP2R_USART234578SEL__PLL2Q 0x1
803
+
#define BV_RCC_D2CCIP2R_USART234578SEL__PLL3Q 0x2
804
+
#define BV_RCC_D2CCIP2R_USART234578SEL__HSI 0x3
805
+
#define BV_RCC_D2CCIP2R_USART234578SEL__CSI 0x4
806
+
#define BV_RCC_D2CCIP2R_USART234578SEL__LSE 0x5
807
+
#define BF_RCC_D2CCIP2R_USART234578SEL(v) (((v) & 0x7) << 0)
808
+
#define BFM_RCC_D2CCIP2R_USART234578SEL(v) BM_RCC_D2CCIP2R_USART234578SEL
809
+
#define BF_RCC_D2CCIP2R_USART234578SEL_V(e) BF_RCC_D2CCIP2R_USART234578SEL(BV_RCC_D2CCIP2R_USART234578SEL__##e)
810
+
#define BFM_RCC_D2CCIP2R_USART234578SEL_V(v) BM_RCC_D2CCIP2R_USART234578SEL
811
+
812
+
#define REG_RCC_D3CCIPR st_reg(RCC_D3CCIPR)
813
+
#define STA_RCC_D3CCIPR (0x58024400 + 0x58)
814
+
#define STO_RCC_D3CCIPR (0x58)
815
+
#define STT_RCC_D3CCIPR STIO_32_RW
816
+
#define STN_RCC_D3CCIPR RCC_D3CCIPR
817
+
#define BP_RCC_D3CCIPR_SPI6SEL 28
818
+
#define BM_RCC_D3CCIPR_SPI6SEL 0x70000000
819
+
#define BV_RCC_D3CCIPR_SPI6SEL__APB4 0x0
820
+
#define BV_RCC_D3CCIPR_SPI6SEL__PLL2Q 0x1
821
+
#define BV_RCC_D3CCIPR_SPI6SEL__PLL3Q 0x2
822
+
#define BV_RCC_D3CCIPR_SPI6SEL__HSI 0x3
823
+
#define BV_RCC_D3CCIPR_SPI6SEL__CSI 0x4
824
+
#define BV_RCC_D3CCIPR_SPI6SEL__HSE 0x5
825
+
#define BF_RCC_D3CCIPR_SPI6SEL(v) (((v) & 0x7) << 28)
826
+
#define BFM_RCC_D3CCIPR_SPI6SEL(v) BM_RCC_D3CCIPR_SPI6SEL
827
+
#define BF_RCC_D3CCIPR_SPI6SEL_V(e) BF_RCC_D3CCIPR_SPI6SEL(BV_RCC_D3CCIPR_SPI6SEL__##e)
828
+
#define BFM_RCC_D3CCIPR_SPI6SEL_V(v) BM_RCC_D3CCIPR_SPI6SEL
829
+
#define BP_RCC_D3CCIPR_SAI4BSEL 24
830
+
#define BM_RCC_D3CCIPR_SAI4BSEL 0x7000000
831
+
#define BV_RCC_D3CCIPR_SAI4BSEL__PLL1Q 0x0
832
+
#define BV_RCC_D3CCIPR_SAI4BSEL__PLL2P 0x1
833
+
#define BV_RCC_D3CCIPR_SAI4BSEL__PLL3P 0x2
834
+
#define BV_RCC_D3CCIPR_SAI4BSEL__I2S_CKIN 0x3
835
+
#define BV_RCC_D3CCIPR_SAI4BSEL__PER 0x4
836
+
#define BF_RCC_D3CCIPR_SAI4BSEL(v) (((v) & 0x7) << 24)
837
+
#define BFM_RCC_D3CCIPR_SAI4BSEL(v) BM_RCC_D3CCIPR_SAI4BSEL
838
+
#define BF_RCC_D3CCIPR_SAI4BSEL_V(e) BF_RCC_D3CCIPR_SAI4BSEL(BV_RCC_D3CCIPR_SAI4BSEL__##e)
839
+
#define BFM_RCC_D3CCIPR_SAI4BSEL_V(v) BM_RCC_D3CCIPR_SAI4BSEL
840
+
#define BP_RCC_D3CCIPR_SAI4ASEL 21
841
+
#define BM_RCC_D3CCIPR_SAI4ASEL 0xe00000
842
+
#define BV_RCC_D3CCIPR_SAI4ASEL__PLL1Q 0x0
843
+
#define BV_RCC_D3CCIPR_SAI4ASEL__PLL2P 0x1
844
+
#define BV_RCC_D3CCIPR_SAI4ASEL__PLL3P 0x2
845
+
#define BV_RCC_D3CCIPR_SAI4ASEL__I2S_CKIN 0x3
846
+
#define BV_RCC_D3CCIPR_SAI4ASEL__PER 0x4
847
+
#define BF_RCC_D3CCIPR_SAI4ASEL(v) (((v) & 0x7) << 21)
848
+
#define BFM_RCC_D3CCIPR_SAI4ASEL(v) BM_RCC_D3CCIPR_SAI4ASEL
849
+
#define BF_RCC_D3CCIPR_SAI4ASEL_V(e) BF_RCC_D3CCIPR_SAI4ASEL(BV_RCC_D3CCIPR_SAI4ASEL__##e)
850
+
#define BFM_RCC_D3CCIPR_SAI4ASEL_V(v) BM_RCC_D3CCIPR_SAI4ASEL
851
+
#define BP_RCC_D3CCIPR_ADCSEL 16
852
+
#define BM_RCC_D3CCIPR_ADCSEL 0x30000
853
+
#define BV_RCC_D3CCIPR_ADCSEL__PLL2P 0x0
854
+
#define BV_RCC_D3CCIPR_ADCSEL__PLL3R 0x1
855
+
#define BV_RCC_D3CCIPR_ADCSEL__PER 0x2
856
+
#define BF_RCC_D3CCIPR_ADCSEL(v) (((v) & 0x3) << 16)
857
+
#define BFM_RCC_D3CCIPR_ADCSEL(v) BM_RCC_D3CCIPR_ADCSEL
858
+
#define BF_RCC_D3CCIPR_ADCSEL_V(e) BF_RCC_D3CCIPR_ADCSEL(BV_RCC_D3CCIPR_ADCSEL__##e)
859
+
#define BFM_RCC_D3CCIPR_ADCSEL_V(v) BM_RCC_D3CCIPR_ADCSEL
860
+
#define BP_RCC_D3CCIPR_LPTIM345SEL 13
861
+
#define BM_RCC_D3CCIPR_LPTIM345SEL 0xe000
862
+
#define BV_RCC_D3CCIPR_LPTIM345SEL__APB4 0x0
863
+
#define BV_RCC_D3CCIPR_LPTIM345SEL__PLL2P 0x1
864
+
#define BV_RCC_D3CCIPR_LPTIM345SEL__PLL3R 0x2
865
+
#define BV_RCC_D3CCIPR_LPTIM345SEL__LSE 0x3
866
+
#define BV_RCC_D3CCIPR_LPTIM345SEL__LSI 0x4
867
+
#define BV_RCC_D3CCIPR_LPTIM345SEL__PER 0x5
868
+
#define BF_RCC_D3CCIPR_LPTIM345SEL(v) (((v) & 0x7) << 13)
869
+
#define BFM_RCC_D3CCIPR_LPTIM345SEL(v) BM_RCC_D3CCIPR_LPTIM345SEL
870
+
#define BF_RCC_D3CCIPR_LPTIM345SEL_V(e) BF_RCC_D3CCIPR_LPTIM345SEL(BV_RCC_D3CCIPR_LPTIM345SEL__##e)
871
+
#define BFM_RCC_D3CCIPR_LPTIM345SEL_V(v) BM_RCC_D3CCIPR_LPTIM345SEL
872
+
#define BP_RCC_D3CCIPR_LPTIM2SEL 10
873
+
#define BM_RCC_D3CCIPR_LPTIM2SEL 0x1c00
874
+
#define BV_RCC_D3CCIPR_LPTIM2SEL__APB4 0x0
875
+
#define BV_RCC_D3CCIPR_LPTIM2SEL__PLL2P 0x1
876
+
#define BV_RCC_D3CCIPR_LPTIM2SEL__PLL3R 0x2
877
+
#define BV_RCC_D3CCIPR_LPTIM2SEL__LSE 0x3
878
+
#define BV_RCC_D3CCIPR_LPTIM2SEL__LSI 0x4
879
+
#define BV_RCC_D3CCIPR_LPTIM2SEL__PER 0x5
880
+
#define BF_RCC_D3CCIPR_LPTIM2SEL(v) (((v) & 0x7) << 10)
881
+
#define BFM_RCC_D3CCIPR_LPTIM2SEL(v) BM_RCC_D3CCIPR_LPTIM2SEL
882
+
#define BF_RCC_D3CCIPR_LPTIM2SEL_V(e) BF_RCC_D3CCIPR_LPTIM2SEL(BV_RCC_D3CCIPR_LPTIM2SEL__##e)
883
+
#define BFM_RCC_D3CCIPR_LPTIM2SEL_V(v) BM_RCC_D3CCIPR_LPTIM2SEL
884
+
#define BP_RCC_D3CCIPR_I2C4SEL 8
885
+
#define BM_RCC_D3CCIPR_I2C4SEL 0x300
886
+
#define BV_RCC_D3CCIPR_I2C4SEL__APB4 0x0
887
+
#define BV_RCC_D3CCIPR_I2C4SEL__PLL3R 0x1
888
+
#define BV_RCC_D3CCIPR_I2C4SEL__HSI 0x2
889
+
#define BV_RCC_D3CCIPR_I2C4SEL__CSI 0x3
890
+
#define BF_RCC_D3CCIPR_I2C4SEL(v) (((v) & 0x3) << 8)
891
+
#define BFM_RCC_D3CCIPR_I2C4SEL(v) BM_RCC_D3CCIPR_I2C4SEL
892
+
#define BF_RCC_D3CCIPR_I2C4SEL_V(e) BF_RCC_D3CCIPR_I2C4SEL(BV_RCC_D3CCIPR_I2C4SEL__##e)
893
+
#define BFM_RCC_D3CCIPR_I2C4SEL_V(v) BM_RCC_D3CCIPR_I2C4SEL
894
+
#define BP_RCC_D3CCIPR_LPUART1SEL 0
895
+
#define BM_RCC_D3CCIPR_LPUART1SEL 0x7
896
+
#define BV_RCC_D3CCIPR_LPUART1SEL__APB4 0x0
897
+
#define BV_RCC_D3CCIPR_LPUART1SEL__PLL2Q 0x1
898
+
#define BV_RCC_D3CCIPR_LPUART1SEL__PLL3Q 0x2
899
+
#define BV_RCC_D3CCIPR_LPUART1SEL__HSI 0x3
900
+
#define BV_RCC_D3CCIPR_LPUART1SEL__CSI 0x4
901
+
#define BV_RCC_D3CCIPR_LPUART1SEL__LSE 0x5
902
+
#define BF_RCC_D3CCIPR_LPUART1SEL(v) (((v) & 0x7) << 0)
903
+
#define BFM_RCC_D3CCIPR_LPUART1SEL(v) BM_RCC_D3CCIPR_LPUART1SEL
904
+
#define BF_RCC_D3CCIPR_LPUART1SEL_V(e) BF_RCC_D3CCIPR_LPUART1SEL(BV_RCC_D3CCIPR_LPUART1SEL__##e)
905
+
#define BFM_RCC_D3CCIPR_LPUART1SEL_V(v) BM_RCC_D3CCIPR_LPUART1SEL
906
+
907
+
#define REG_RCC_BDCR st_reg(RCC_BDCR)
908
+
#define STA_RCC_BDCR (0x58024400 + 0x70)
909
+
#define STO_RCC_BDCR (0x70)
910
+
#define STT_RCC_BDCR STIO_32_RW
911
+
#define STN_RCC_BDCR RCC_BDCR
912
+
#define BP_RCC_BDCR_RTCSEL 8
913
+
#define BM_RCC_BDCR_RTCSEL 0x300
914
+
#define BV_RCC_BDCR_RTCSEL__NONE 0x0
915
+
#define BV_RCC_BDCR_RTCSEL__LSE 0x1
916
+
#define BV_RCC_BDCR_RTCSEL__LSI 0x2
917
+
#define BV_RCC_BDCR_RTCSEL__HSE 0x3
918
+
#define BF_RCC_BDCR_RTCSEL(v) (((v) & 0x3) << 8)
919
+
#define BFM_RCC_BDCR_RTCSEL(v) BM_RCC_BDCR_RTCSEL
920
+
#define BF_RCC_BDCR_RTCSEL_V(e) BF_RCC_BDCR_RTCSEL(BV_RCC_BDCR_RTCSEL__##e)
921
+
#define BFM_RCC_BDCR_RTCSEL_V(v) BM_RCC_BDCR_RTCSEL
922
+
#define BP_RCC_BDCR_LSEDRV 3
923
+
#define BM_RCC_BDCR_LSEDRV 0x18
924
+
#define BV_RCC_BDCR_LSEDRV__LOW 0x0
925
+
#define BV_RCC_BDCR_LSEDRV__MED_LOW 0x1
926
+
#define BV_RCC_BDCR_LSEDRV__MED_HIGH 0x2
927
+
#define BV_RCC_BDCR_LSEDRV__HIGH 0x3
928
+
#define BF_RCC_BDCR_LSEDRV(v) (((v) & 0x3) << 3)
929
+
#define BFM_RCC_BDCR_LSEDRV(v) BM_RCC_BDCR_LSEDRV
930
+
#define BF_RCC_BDCR_LSEDRV_V(e) BF_RCC_BDCR_LSEDRV(BV_RCC_BDCR_LSEDRV__##e)
931
+
#define BFM_RCC_BDCR_LSEDRV_V(v) BM_RCC_BDCR_LSEDRV
932
+
#define BP_RCC_BDCR_BDRST 16
933
+
#define BM_RCC_BDCR_BDRST 0x10000
934
+
#define BF_RCC_BDCR_BDRST(v) (((v) & 0x1) << 16)
935
+
#define BFM_RCC_BDCR_BDRST(v) BM_RCC_BDCR_BDRST
936
+
#define BF_RCC_BDCR_BDRST_V(e) BF_RCC_BDCR_BDRST(BV_RCC_BDCR_BDRST__##e)
937
+
#define BFM_RCC_BDCR_BDRST_V(v) BM_RCC_BDCR_BDRST
938
+
#define BP_RCC_BDCR_RTCEN 15
939
+
#define BM_RCC_BDCR_RTCEN 0x8000
940
+
#define BF_RCC_BDCR_RTCEN(v) (((v) & 0x1) << 15)
941
+
#define BFM_RCC_BDCR_RTCEN(v) BM_RCC_BDCR_RTCEN
942
+
#define BF_RCC_BDCR_RTCEN_V(e) BF_RCC_BDCR_RTCEN(BV_RCC_BDCR_RTCEN__##e)
943
+
#define BFM_RCC_BDCR_RTCEN_V(v) BM_RCC_BDCR_RTCEN
944
+
#define BP_RCC_BDCR_LSECSSD 6
945
+
#define BM_RCC_BDCR_LSECSSD 0x40
946
+
#define BF_RCC_BDCR_LSECSSD(v) (((v) & 0x1) << 6)
947
+
#define BFM_RCC_BDCR_LSECSSD(v) BM_RCC_BDCR_LSECSSD
948
+
#define BF_RCC_BDCR_LSECSSD_V(e) BF_RCC_BDCR_LSECSSD(BV_RCC_BDCR_LSECSSD__##e)
949
+
#define BFM_RCC_BDCR_LSECSSD_V(v) BM_RCC_BDCR_LSECSSD
950
+
#define BP_RCC_BDCR_LSECSSON 5
951
+
#define BM_RCC_BDCR_LSECSSON 0x20
952
+
#define BF_RCC_BDCR_LSECSSON(v) (((v) & 0x1) << 5)
953
+
#define BFM_RCC_BDCR_LSECSSON(v) BM_RCC_BDCR_LSECSSON
954
+
#define BF_RCC_BDCR_LSECSSON_V(e) BF_RCC_BDCR_LSECSSON(BV_RCC_BDCR_LSECSSON__##e)
955
+
#define BFM_RCC_BDCR_LSECSSON_V(v) BM_RCC_BDCR_LSECSSON
956
+
#define BP_RCC_BDCR_LSEBYP 2
957
+
#define BM_RCC_BDCR_LSEBYP 0x4
958
+
#define BF_RCC_BDCR_LSEBYP(v) (((v) & 0x1) << 2)
959
+
#define BFM_RCC_BDCR_LSEBYP(v) BM_RCC_BDCR_LSEBYP
960
+
#define BF_RCC_BDCR_LSEBYP_V(e) BF_RCC_BDCR_LSEBYP(BV_RCC_BDCR_LSEBYP__##e)
961
+
#define BFM_RCC_BDCR_LSEBYP_V(v) BM_RCC_BDCR_LSEBYP
962
+
#define BP_RCC_BDCR_LSERDY 1
963
+
#define BM_RCC_BDCR_LSERDY 0x2
964
+
#define BF_RCC_BDCR_LSERDY(v) (((v) & 0x1) << 1)
965
+
#define BFM_RCC_BDCR_LSERDY(v) BM_RCC_BDCR_LSERDY
966
+
#define BF_RCC_BDCR_LSERDY_V(e) BF_RCC_BDCR_LSERDY(BV_RCC_BDCR_LSERDY__##e)
967
+
#define BFM_RCC_BDCR_LSERDY_V(v) BM_RCC_BDCR_LSERDY
968
+
#define BP_RCC_BDCR_LSEON 0
969
+
#define BM_RCC_BDCR_LSEON 0x1
970
+
#define BF_RCC_BDCR_LSEON(v) (((v) & 0x1) << 0)
971
+
#define BFM_RCC_BDCR_LSEON(v) BM_RCC_BDCR_LSEON
972
+
#define BF_RCC_BDCR_LSEON_V(e) BF_RCC_BDCR_LSEON(BV_RCC_BDCR_LSEON__##e)
973
+
#define BFM_RCC_BDCR_LSEON_V(v) BM_RCC_BDCR_LSEON
974
+
975
+
#define REG_RCC_CSR st_reg(RCC_CSR)
976
+
#define STA_RCC_CSR (0x58024400 + 0x74)
977
+
#define STO_RCC_CSR (0x74)
978
+
#define STT_RCC_CSR STIO_32_RW
979
+
#define STN_RCC_CSR RCC_CSR
980
+
#define BP_RCC_CSR_LSIRDY 1
981
+
#define BM_RCC_CSR_LSIRDY 0x2
982
+
#define BF_RCC_CSR_LSIRDY(v) (((v) & 0x1) << 1)
983
+
#define BFM_RCC_CSR_LSIRDY(v) BM_RCC_CSR_LSIRDY
984
+
#define BF_RCC_CSR_LSIRDY_V(e) BF_RCC_CSR_LSIRDY(BV_RCC_CSR_LSIRDY__##e)
985
+
#define BFM_RCC_CSR_LSIRDY_V(v) BM_RCC_CSR_LSIRDY
986
+
#define BP_RCC_CSR_LSION 0
987
+
#define BM_RCC_CSR_LSION 0x1
988
+
#define BF_RCC_CSR_LSION(v) (((v) & 0x1) << 0)
989
+
#define BFM_RCC_CSR_LSION(v) BM_RCC_CSR_LSION
990
+
#define BF_RCC_CSR_LSION_V(e) BF_RCC_CSR_LSION(BV_RCC_CSR_LSION__##e)
991
+
#define BFM_RCC_CSR_LSION_V(v) BM_RCC_CSR_LSION
992
+
993
+
#define REG_RCC_AHB3ENR st_reg(RCC_AHB3ENR)
994
+
#define STA_RCC_AHB3ENR (0x58024400 + 0xd4)
995
+
#define STO_RCC_AHB3ENR (0xd4)
996
+
#define STT_RCC_AHB3ENR STIO_32_RW
997
+
#define STN_RCC_AHB3ENR RCC_AHB3ENR
998
+
#define BP_RCC_AHB3ENR_AXISRAMEN 31
999
+
#define BM_RCC_AHB3ENR_AXISRAMEN 0x80000000
1000
+
#define BF_RCC_AHB3ENR_AXISRAMEN(v) (((v) & 0x1) << 31)
1001
+
#define BFM_RCC_AHB3ENR_AXISRAMEN(v) BM_RCC_AHB3ENR_AXISRAMEN
1002
+
#define BF_RCC_AHB3ENR_AXISRAMEN_V(e) BF_RCC_AHB3ENR_AXISRAMEN(BV_RCC_AHB3ENR_AXISRAMEN__##e)
1003
+
#define BFM_RCC_AHB3ENR_AXISRAMEN_V(v) BM_RCC_AHB3ENR_AXISRAMEN
1004
+
#define BP_RCC_AHB3ENR_ITCMEN 30
1005
+
#define BM_RCC_AHB3ENR_ITCMEN 0x40000000
1006
+
#define BF_RCC_AHB3ENR_ITCMEN(v) (((v) & 0x1) << 30)
1007
+
#define BFM_RCC_AHB3ENR_ITCMEN(v) BM_RCC_AHB3ENR_ITCMEN
1008
+
#define BF_RCC_AHB3ENR_ITCMEN_V(e) BF_RCC_AHB3ENR_ITCMEN(BV_RCC_AHB3ENR_ITCMEN__##e)
1009
+
#define BFM_RCC_AHB3ENR_ITCMEN_V(v) BM_RCC_AHB3ENR_ITCMEN
1010
+
#define BP_RCC_AHB3ENR_DTCM2EN 29
1011
+
#define BM_RCC_AHB3ENR_DTCM2EN 0x20000000
1012
+
#define BF_RCC_AHB3ENR_DTCM2EN(v) (((v) & 0x1) << 29)
1013
+
#define BFM_RCC_AHB3ENR_DTCM2EN(v) BM_RCC_AHB3ENR_DTCM2EN
1014
+
#define BF_RCC_AHB3ENR_DTCM2EN_V(e) BF_RCC_AHB3ENR_DTCM2EN(BV_RCC_AHB3ENR_DTCM2EN__##e)
1015
+
#define BFM_RCC_AHB3ENR_DTCM2EN_V(v) BM_RCC_AHB3ENR_DTCM2EN
1016
+
#define BP_RCC_AHB3ENR_D1DTCM1EN 28
1017
+
#define BM_RCC_AHB3ENR_D1DTCM1EN 0x10000000
1018
+
#define BF_RCC_AHB3ENR_D1DTCM1EN(v) (((v) & 0x1) << 28)
1019
+
#define BFM_RCC_AHB3ENR_D1DTCM1EN(v) BM_RCC_AHB3ENR_D1DTCM1EN
1020
+
#define BF_RCC_AHB3ENR_D1DTCM1EN_V(e) BF_RCC_AHB3ENR_D1DTCM1EN(BV_RCC_AHB3ENR_D1DTCM1EN__##e)
1021
+
#define BFM_RCC_AHB3ENR_D1DTCM1EN_V(v) BM_RCC_AHB3ENR_D1DTCM1EN
1022
+
#define BP_RCC_AHB3ENR_SDMMC1EN 16
1023
+
#define BM_RCC_AHB3ENR_SDMMC1EN 0x10000
1024
+
#define BF_RCC_AHB3ENR_SDMMC1EN(v) (((v) & 0x1) << 16)
1025
+
#define BFM_RCC_AHB3ENR_SDMMC1EN(v) BM_RCC_AHB3ENR_SDMMC1EN
1026
+
#define BF_RCC_AHB3ENR_SDMMC1EN_V(e) BF_RCC_AHB3ENR_SDMMC1EN(BV_RCC_AHB3ENR_SDMMC1EN__##e)
1027
+
#define BFM_RCC_AHB3ENR_SDMMC1EN_V(v) BM_RCC_AHB3ENR_SDMMC1EN
1028
+
#define BP_RCC_AHB3ENR_QSPIEN 14
1029
+
#define BM_RCC_AHB3ENR_QSPIEN 0x4000
1030
+
#define BF_RCC_AHB3ENR_QSPIEN(v) (((v) & 0x1) << 14)
1031
+
#define BFM_RCC_AHB3ENR_QSPIEN(v) BM_RCC_AHB3ENR_QSPIEN
1032
+
#define BF_RCC_AHB3ENR_QSPIEN_V(e) BF_RCC_AHB3ENR_QSPIEN(BV_RCC_AHB3ENR_QSPIEN__##e)
1033
+
#define BFM_RCC_AHB3ENR_QSPIEN_V(v) BM_RCC_AHB3ENR_QSPIEN
1034
+
#define BP_RCC_AHB3ENR_FMCEN 12
1035
+
#define BM_RCC_AHB3ENR_FMCEN 0x1000
1036
+
#define BF_RCC_AHB3ENR_FMCEN(v) (((v) & 0x1) << 12)
1037
+
#define BFM_RCC_AHB3ENR_FMCEN(v) BM_RCC_AHB3ENR_FMCEN
1038
+
#define BF_RCC_AHB3ENR_FMCEN_V(e) BF_RCC_AHB3ENR_FMCEN(BV_RCC_AHB3ENR_FMCEN__##e)
1039
+
#define BFM_RCC_AHB3ENR_FMCEN_V(v) BM_RCC_AHB3ENR_FMCEN
1040
+
#define BP_RCC_AHB3ENR_FLASHEN 8
1041
+
#define BM_RCC_AHB3ENR_FLASHEN 0x100
1042
+
#define BF_RCC_AHB3ENR_FLASHEN(v) (((v) & 0x1) << 8)
1043
+
#define BFM_RCC_AHB3ENR_FLASHEN(v) BM_RCC_AHB3ENR_FLASHEN
1044
+
#define BF_RCC_AHB3ENR_FLASHEN_V(e) BF_RCC_AHB3ENR_FLASHEN(BV_RCC_AHB3ENR_FLASHEN__##e)
1045
+
#define BFM_RCC_AHB3ENR_FLASHEN_V(v) BM_RCC_AHB3ENR_FLASHEN
1046
+
#define BP_RCC_AHB3ENR_JPEGDECEN 5
1047
+
#define BM_RCC_AHB3ENR_JPEGDECEN 0x20
1048
+
#define BF_RCC_AHB3ENR_JPEGDECEN(v) (((v) & 0x1) << 5)
1049
+
#define BFM_RCC_AHB3ENR_JPEGDECEN(v) BM_RCC_AHB3ENR_JPEGDECEN
1050
+
#define BF_RCC_AHB3ENR_JPEGDECEN_V(e) BF_RCC_AHB3ENR_JPEGDECEN(BV_RCC_AHB3ENR_JPEGDECEN__##e)
1051
+
#define BFM_RCC_AHB3ENR_JPEGDECEN_V(v) BM_RCC_AHB3ENR_JPEGDECEN
1052
+
#define BP_RCC_AHB3ENR_DMA2DEN 4
1053
+
#define BM_RCC_AHB3ENR_DMA2DEN 0x10
1054
+
#define BF_RCC_AHB3ENR_DMA2DEN(v) (((v) & 0x1) << 4)
1055
+
#define BFM_RCC_AHB3ENR_DMA2DEN(v) BM_RCC_AHB3ENR_DMA2DEN
1056
+
#define BF_RCC_AHB3ENR_DMA2DEN_V(e) BF_RCC_AHB3ENR_DMA2DEN(BV_RCC_AHB3ENR_DMA2DEN__##e)
1057
+
#define BFM_RCC_AHB3ENR_DMA2DEN_V(v) BM_RCC_AHB3ENR_DMA2DEN
1058
+
#define BP_RCC_AHB3ENR_MDMAEN 0
1059
+
#define BM_RCC_AHB3ENR_MDMAEN 0x1
1060
+
#define BF_RCC_AHB3ENR_MDMAEN(v) (((v) & 0x1) << 0)
1061
+
#define BFM_RCC_AHB3ENR_MDMAEN(v) BM_RCC_AHB3ENR_MDMAEN
1062
+
#define BF_RCC_AHB3ENR_MDMAEN_V(e) BF_RCC_AHB3ENR_MDMAEN(BV_RCC_AHB3ENR_MDMAEN__##e)
1063
+
#define BFM_RCC_AHB3ENR_MDMAEN_V(v) BM_RCC_AHB3ENR_MDMAEN
1064
+
1065
+
#define REG_RCC_AHB3LPENR st_reg(RCC_AHB3LPENR)
1066
+
#define STA_RCC_AHB3LPENR (0x58024400 + 0xfc)
1067
+
#define STO_RCC_AHB3LPENR (0xfc)
1068
+
#define STT_RCC_AHB3LPENR STIO_32_RW
1069
+
#define STN_RCC_AHB3LPENR RCC_AHB3LPENR
1070
+
#define BP_RCC_AHB3LPENR_AXISRAMEN 31
1071
+
#define BM_RCC_AHB3LPENR_AXISRAMEN 0x80000000
1072
+
#define BF_RCC_AHB3LPENR_AXISRAMEN(v) (((v) & 0x1) << 31)
1073
+
#define BFM_RCC_AHB3LPENR_AXISRAMEN(v) BM_RCC_AHB3LPENR_AXISRAMEN
1074
+
#define BF_RCC_AHB3LPENR_AXISRAMEN_V(e) BF_RCC_AHB3LPENR_AXISRAMEN(BV_RCC_AHB3LPENR_AXISRAMEN__##e)
1075
+
#define BFM_RCC_AHB3LPENR_AXISRAMEN_V(v) BM_RCC_AHB3LPENR_AXISRAMEN
1076
+
#define BP_RCC_AHB3LPENR_ITCMEN 30
1077
+
#define BM_RCC_AHB3LPENR_ITCMEN 0x40000000
1078
+
#define BF_RCC_AHB3LPENR_ITCMEN(v) (((v) & 0x1) << 30)
1079
+
#define BFM_RCC_AHB3LPENR_ITCMEN(v) BM_RCC_AHB3LPENR_ITCMEN
1080
+
#define BF_RCC_AHB3LPENR_ITCMEN_V(e) BF_RCC_AHB3LPENR_ITCMEN(BV_RCC_AHB3LPENR_ITCMEN__##e)
1081
+
#define BFM_RCC_AHB3LPENR_ITCMEN_V(v) BM_RCC_AHB3LPENR_ITCMEN
1082
+
#define BP_RCC_AHB3LPENR_DTCM2EN 29
1083
+
#define BM_RCC_AHB3LPENR_DTCM2EN 0x20000000
1084
+
#define BF_RCC_AHB3LPENR_DTCM2EN(v) (((v) & 0x1) << 29)
1085
+
#define BFM_RCC_AHB3LPENR_DTCM2EN(v) BM_RCC_AHB3LPENR_DTCM2EN
1086
+
#define BF_RCC_AHB3LPENR_DTCM2EN_V(e) BF_RCC_AHB3LPENR_DTCM2EN(BV_RCC_AHB3LPENR_DTCM2EN__##e)
1087
+
#define BFM_RCC_AHB3LPENR_DTCM2EN_V(v) BM_RCC_AHB3LPENR_DTCM2EN
1088
+
#define BP_RCC_AHB3LPENR_D1DTCM1EN 28
1089
+
#define BM_RCC_AHB3LPENR_D1DTCM1EN 0x10000000
1090
+
#define BF_RCC_AHB3LPENR_D1DTCM1EN(v) (((v) & 0x1) << 28)
1091
+
#define BFM_RCC_AHB3LPENR_D1DTCM1EN(v) BM_RCC_AHB3LPENR_D1DTCM1EN
1092
+
#define BF_RCC_AHB3LPENR_D1DTCM1EN_V(e) BF_RCC_AHB3LPENR_D1DTCM1EN(BV_RCC_AHB3LPENR_D1DTCM1EN__##e)
1093
+
#define BFM_RCC_AHB3LPENR_D1DTCM1EN_V(v) BM_RCC_AHB3LPENR_D1DTCM1EN
1094
+
#define BP_RCC_AHB3LPENR_SDMMC1EN 16
1095
+
#define BM_RCC_AHB3LPENR_SDMMC1EN 0x10000
1096
+
#define BF_RCC_AHB3LPENR_SDMMC1EN(v) (((v) & 0x1) << 16)
1097
+
#define BFM_RCC_AHB3LPENR_SDMMC1EN(v) BM_RCC_AHB3LPENR_SDMMC1EN
1098
+
#define BF_RCC_AHB3LPENR_SDMMC1EN_V(e) BF_RCC_AHB3LPENR_SDMMC1EN(BV_RCC_AHB3LPENR_SDMMC1EN__##e)
1099
+
#define BFM_RCC_AHB3LPENR_SDMMC1EN_V(v) BM_RCC_AHB3LPENR_SDMMC1EN
1100
+
#define BP_RCC_AHB3LPENR_QSPIEN 14
1101
+
#define BM_RCC_AHB3LPENR_QSPIEN 0x4000
1102
+
#define BF_RCC_AHB3LPENR_QSPIEN(v) (((v) & 0x1) << 14)
1103
+
#define BFM_RCC_AHB3LPENR_QSPIEN(v) BM_RCC_AHB3LPENR_QSPIEN
1104
+
#define BF_RCC_AHB3LPENR_QSPIEN_V(e) BF_RCC_AHB3LPENR_QSPIEN(BV_RCC_AHB3LPENR_QSPIEN__##e)
1105
+
#define BFM_RCC_AHB3LPENR_QSPIEN_V(v) BM_RCC_AHB3LPENR_QSPIEN
1106
+
#define BP_RCC_AHB3LPENR_FMCEN 12
1107
+
#define BM_RCC_AHB3LPENR_FMCEN 0x1000
1108
+
#define BF_RCC_AHB3LPENR_FMCEN(v) (((v) & 0x1) << 12)
1109
+
#define BFM_RCC_AHB3LPENR_FMCEN(v) BM_RCC_AHB3LPENR_FMCEN
1110
+
#define BF_RCC_AHB3LPENR_FMCEN_V(e) BF_RCC_AHB3LPENR_FMCEN(BV_RCC_AHB3LPENR_FMCEN__##e)
1111
+
#define BFM_RCC_AHB3LPENR_FMCEN_V(v) BM_RCC_AHB3LPENR_FMCEN
1112
+
#define BP_RCC_AHB3LPENR_FLASHEN 8
1113
+
#define BM_RCC_AHB3LPENR_FLASHEN 0x100
1114
+
#define BF_RCC_AHB3LPENR_FLASHEN(v) (((v) & 0x1) << 8)
1115
+
#define BFM_RCC_AHB3LPENR_FLASHEN(v) BM_RCC_AHB3LPENR_FLASHEN
1116
+
#define BF_RCC_AHB3LPENR_FLASHEN_V(e) BF_RCC_AHB3LPENR_FLASHEN(BV_RCC_AHB3LPENR_FLASHEN__##e)
1117
+
#define BFM_RCC_AHB3LPENR_FLASHEN_V(v) BM_RCC_AHB3LPENR_FLASHEN
1118
+
#define BP_RCC_AHB3LPENR_JPEGDECEN 5
1119
+
#define BM_RCC_AHB3LPENR_JPEGDECEN 0x20
1120
+
#define BF_RCC_AHB3LPENR_JPEGDECEN(v) (((v) & 0x1) << 5)
1121
+
#define BFM_RCC_AHB3LPENR_JPEGDECEN(v) BM_RCC_AHB3LPENR_JPEGDECEN
1122
+
#define BF_RCC_AHB3LPENR_JPEGDECEN_V(e) BF_RCC_AHB3LPENR_JPEGDECEN(BV_RCC_AHB3LPENR_JPEGDECEN__##e)
1123
+
#define BFM_RCC_AHB3LPENR_JPEGDECEN_V(v) BM_RCC_AHB3LPENR_JPEGDECEN
1124
+
#define BP_RCC_AHB3LPENR_DMA2DEN 4
1125
+
#define BM_RCC_AHB3LPENR_DMA2DEN 0x10
1126
+
#define BF_RCC_AHB3LPENR_DMA2DEN(v) (((v) & 0x1) << 4)
1127
+
#define BFM_RCC_AHB3LPENR_DMA2DEN(v) BM_RCC_AHB3LPENR_DMA2DEN
1128
+
#define BF_RCC_AHB3LPENR_DMA2DEN_V(e) BF_RCC_AHB3LPENR_DMA2DEN(BV_RCC_AHB3LPENR_DMA2DEN__##e)
1129
+
#define BFM_RCC_AHB3LPENR_DMA2DEN_V(v) BM_RCC_AHB3LPENR_DMA2DEN
1130
+
#define BP_RCC_AHB3LPENR_MDMAEN 0
1131
+
#define BM_RCC_AHB3LPENR_MDMAEN 0x1
1132
+
#define BF_RCC_AHB3LPENR_MDMAEN(v) (((v) & 0x1) << 0)
1133
+
#define BFM_RCC_AHB3LPENR_MDMAEN(v) BM_RCC_AHB3LPENR_MDMAEN
1134
+
#define BF_RCC_AHB3LPENR_MDMAEN_V(e) BF_RCC_AHB3LPENR_MDMAEN(BV_RCC_AHB3LPENR_MDMAEN__##e)
1135
+
#define BFM_RCC_AHB3LPENR_MDMAEN_V(v) BM_RCC_AHB3LPENR_MDMAEN
1136
+
1137
+
#define REG_RCC_AHB4ENR st_reg(RCC_AHB4ENR)
1138
+
#define STA_RCC_AHB4ENR (0x58024400 + 0xe0)
1139
+
#define STO_RCC_AHB4ENR (0xe0)
1140
+
#define STT_RCC_AHB4ENR STIO_32_RW
1141
+
#define STN_RCC_AHB4ENR RCC_AHB4ENR
1142
+
#define BP_RCC_AHB4ENR_SRAM4EN 29
1143
+
#define BM_RCC_AHB4ENR_SRAM4EN 0x20000000
1144
+
#define BF_RCC_AHB4ENR_SRAM4EN(v) (((v) & 0x1) << 29)
1145
+
#define BFM_RCC_AHB4ENR_SRAM4EN(v) BM_RCC_AHB4ENR_SRAM4EN
1146
+
#define BF_RCC_AHB4ENR_SRAM4EN_V(e) BF_RCC_AHB4ENR_SRAM4EN(BV_RCC_AHB4ENR_SRAM4EN__##e)
1147
+
#define BFM_RCC_AHB4ENR_SRAM4EN_V(v) BM_RCC_AHB4ENR_SRAM4EN
1148
+
#define BP_RCC_AHB4ENR_BKPRAMEN 28
1149
+
#define BM_RCC_AHB4ENR_BKPRAMEN 0x10000000
1150
+
#define BF_RCC_AHB4ENR_BKPRAMEN(v) (((v) & 0x1) << 28)
1151
+
#define BFM_RCC_AHB4ENR_BKPRAMEN(v) BM_RCC_AHB4ENR_BKPRAMEN
1152
+
#define BF_RCC_AHB4ENR_BKPRAMEN_V(e) BF_RCC_AHB4ENR_BKPRAMEN(BV_RCC_AHB4ENR_BKPRAMEN__##e)
1153
+
#define BFM_RCC_AHB4ENR_BKPRAMEN_V(v) BM_RCC_AHB4ENR_BKPRAMEN
1154
+
#define BP_RCC_AHB4ENR_HSEMEN 25
1155
+
#define BM_RCC_AHB4ENR_HSEMEN 0x2000000
1156
+
#define BF_RCC_AHB4ENR_HSEMEN(v) (((v) & 0x1) << 25)
1157
+
#define BFM_RCC_AHB4ENR_HSEMEN(v) BM_RCC_AHB4ENR_HSEMEN
1158
+
#define BF_RCC_AHB4ENR_HSEMEN_V(e) BF_RCC_AHB4ENR_HSEMEN(BV_RCC_AHB4ENR_HSEMEN__##e)
1159
+
#define BFM_RCC_AHB4ENR_HSEMEN_V(v) BM_RCC_AHB4ENR_HSEMEN
1160
+
#define BP_RCC_AHB4ENR_ADC3EN 24
1161
+
#define BM_RCC_AHB4ENR_ADC3EN 0x1000000
1162
+
#define BF_RCC_AHB4ENR_ADC3EN(v) (((v) & 0x1) << 24)
1163
+
#define BFM_RCC_AHB4ENR_ADC3EN(v) BM_RCC_AHB4ENR_ADC3EN
1164
+
#define BF_RCC_AHB4ENR_ADC3EN_V(e) BF_RCC_AHB4ENR_ADC3EN(BV_RCC_AHB4ENR_ADC3EN__##e)
1165
+
#define BFM_RCC_AHB4ENR_ADC3EN_V(v) BM_RCC_AHB4ENR_ADC3EN
1166
+
#define BP_RCC_AHB4ENR_BDMAEN 21
1167
+
#define BM_RCC_AHB4ENR_BDMAEN 0x200000
1168
+
#define BF_RCC_AHB4ENR_BDMAEN(v) (((v) & 0x1) << 21)
1169
+
#define BFM_RCC_AHB4ENR_BDMAEN(v) BM_RCC_AHB4ENR_BDMAEN
1170
+
#define BF_RCC_AHB4ENR_BDMAEN_V(e) BF_RCC_AHB4ENR_BDMAEN(BV_RCC_AHB4ENR_BDMAEN__##e)
1171
+
#define BFM_RCC_AHB4ENR_BDMAEN_V(v) BM_RCC_AHB4ENR_BDMAEN
1172
+
#define BP_RCC_AHB4ENR_CRCEN 19
1173
+
#define BM_RCC_AHB4ENR_CRCEN 0x80000
1174
+
#define BF_RCC_AHB4ENR_CRCEN(v) (((v) & 0x1) << 19)
1175
+
#define BFM_RCC_AHB4ENR_CRCEN(v) BM_RCC_AHB4ENR_CRCEN
1176
+
#define BF_RCC_AHB4ENR_CRCEN_V(e) BF_RCC_AHB4ENR_CRCEN(BV_RCC_AHB4ENR_CRCEN__##e)
1177
+
#define BFM_RCC_AHB4ENR_CRCEN_V(v) BM_RCC_AHB4ENR_CRCEN
1178
+
#define BP_RCC_AHB4ENR_GPIOKEN 10
1179
+
#define BM_RCC_AHB4ENR_GPIOKEN 0x400
1180
+
#define BF_RCC_AHB4ENR_GPIOKEN(v) (((v) & 0x1) << 10)
1181
+
#define BFM_RCC_AHB4ENR_GPIOKEN(v) BM_RCC_AHB4ENR_GPIOKEN
1182
+
#define BF_RCC_AHB4ENR_GPIOKEN_V(e) BF_RCC_AHB4ENR_GPIOKEN(BV_RCC_AHB4ENR_GPIOKEN__##e)
1183
+
#define BFM_RCC_AHB4ENR_GPIOKEN_V(v) BM_RCC_AHB4ENR_GPIOKEN
1184
+
#define BP_RCC_AHB4ENR_GPIOJEN 9
1185
+
#define BM_RCC_AHB4ENR_GPIOJEN 0x200
1186
+
#define BF_RCC_AHB4ENR_GPIOJEN(v) (((v) & 0x1) << 9)
1187
+
#define BFM_RCC_AHB4ENR_GPIOJEN(v) BM_RCC_AHB4ENR_GPIOJEN
1188
+
#define BF_RCC_AHB4ENR_GPIOJEN_V(e) BF_RCC_AHB4ENR_GPIOJEN(BV_RCC_AHB4ENR_GPIOJEN__##e)
1189
+
#define BFM_RCC_AHB4ENR_GPIOJEN_V(v) BM_RCC_AHB4ENR_GPIOJEN
1190
+
#define BP_RCC_AHB4ENR_GPIOIEN 8
1191
+
#define BM_RCC_AHB4ENR_GPIOIEN 0x100
1192
+
#define BF_RCC_AHB4ENR_GPIOIEN(v) (((v) & 0x1) << 8)
1193
+
#define BFM_RCC_AHB4ENR_GPIOIEN(v) BM_RCC_AHB4ENR_GPIOIEN
1194
+
#define BF_RCC_AHB4ENR_GPIOIEN_V(e) BF_RCC_AHB4ENR_GPIOIEN(BV_RCC_AHB4ENR_GPIOIEN__##e)
1195
+
#define BFM_RCC_AHB4ENR_GPIOIEN_V(v) BM_RCC_AHB4ENR_GPIOIEN
1196
+
#define BP_RCC_AHB4ENR_GPIOHEN 7
1197
+
#define BM_RCC_AHB4ENR_GPIOHEN 0x80
1198
+
#define BF_RCC_AHB4ENR_GPIOHEN(v) (((v) & 0x1) << 7)
1199
+
#define BFM_RCC_AHB4ENR_GPIOHEN(v) BM_RCC_AHB4ENR_GPIOHEN
1200
+
#define BF_RCC_AHB4ENR_GPIOHEN_V(e) BF_RCC_AHB4ENR_GPIOHEN(BV_RCC_AHB4ENR_GPIOHEN__##e)
1201
+
#define BFM_RCC_AHB4ENR_GPIOHEN_V(v) BM_RCC_AHB4ENR_GPIOHEN
1202
+
#define BP_RCC_AHB4ENR_GPIOGEN 6
1203
+
#define BM_RCC_AHB4ENR_GPIOGEN 0x40
1204
+
#define BF_RCC_AHB4ENR_GPIOGEN(v) (((v) & 0x1) << 6)
1205
+
#define BFM_RCC_AHB4ENR_GPIOGEN(v) BM_RCC_AHB4ENR_GPIOGEN
1206
+
#define BF_RCC_AHB4ENR_GPIOGEN_V(e) BF_RCC_AHB4ENR_GPIOGEN(BV_RCC_AHB4ENR_GPIOGEN__##e)
1207
+
#define BFM_RCC_AHB4ENR_GPIOGEN_V(v) BM_RCC_AHB4ENR_GPIOGEN
1208
+
#define BP_RCC_AHB4ENR_GPIOFEN 5
1209
+
#define BM_RCC_AHB4ENR_GPIOFEN 0x20
1210
+
#define BF_RCC_AHB4ENR_GPIOFEN(v) (((v) & 0x1) << 5)
1211
+
#define BFM_RCC_AHB4ENR_GPIOFEN(v) BM_RCC_AHB4ENR_GPIOFEN
1212
+
#define BF_RCC_AHB4ENR_GPIOFEN_V(e) BF_RCC_AHB4ENR_GPIOFEN(BV_RCC_AHB4ENR_GPIOFEN__##e)
1213
+
#define BFM_RCC_AHB4ENR_GPIOFEN_V(v) BM_RCC_AHB4ENR_GPIOFEN
1214
+
#define BP_RCC_AHB4ENR_GPIOEEN 4
1215
+
#define BM_RCC_AHB4ENR_GPIOEEN 0x10
1216
+
#define BF_RCC_AHB4ENR_GPIOEEN(v) (((v) & 0x1) << 4)
1217
+
#define BFM_RCC_AHB4ENR_GPIOEEN(v) BM_RCC_AHB4ENR_GPIOEEN
1218
+
#define BF_RCC_AHB4ENR_GPIOEEN_V(e) BF_RCC_AHB4ENR_GPIOEEN(BV_RCC_AHB4ENR_GPIOEEN__##e)
1219
+
#define BFM_RCC_AHB4ENR_GPIOEEN_V(v) BM_RCC_AHB4ENR_GPIOEEN
1220
+
#define BP_RCC_AHB4ENR_GPIODEN 3
1221
+
#define BM_RCC_AHB4ENR_GPIODEN 0x8
1222
+
#define BF_RCC_AHB4ENR_GPIODEN(v) (((v) & 0x1) << 3)
1223
+
#define BFM_RCC_AHB4ENR_GPIODEN(v) BM_RCC_AHB4ENR_GPIODEN
1224
+
#define BF_RCC_AHB4ENR_GPIODEN_V(e) BF_RCC_AHB4ENR_GPIODEN(BV_RCC_AHB4ENR_GPIODEN__##e)
1225
+
#define BFM_RCC_AHB4ENR_GPIODEN_V(v) BM_RCC_AHB4ENR_GPIODEN
1226
+
#define BP_RCC_AHB4ENR_GPIOCEN 2
1227
+
#define BM_RCC_AHB4ENR_GPIOCEN 0x4
1228
+
#define BF_RCC_AHB4ENR_GPIOCEN(v) (((v) & 0x1) << 2)
1229
+
#define BFM_RCC_AHB4ENR_GPIOCEN(v) BM_RCC_AHB4ENR_GPIOCEN
1230
+
#define BF_RCC_AHB4ENR_GPIOCEN_V(e) BF_RCC_AHB4ENR_GPIOCEN(BV_RCC_AHB4ENR_GPIOCEN__##e)
1231
+
#define BFM_RCC_AHB4ENR_GPIOCEN_V(v) BM_RCC_AHB4ENR_GPIOCEN
1232
+
#define BP_RCC_AHB4ENR_GPIOBEN 1
1233
+
#define BM_RCC_AHB4ENR_GPIOBEN 0x2
1234
+
#define BF_RCC_AHB4ENR_GPIOBEN(v) (((v) & 0x1) << 1)
1235
+
#define BFM_RCC_AHB4ENR_GPIOBEN(v) BM_RCC_AHB4ENR_GPIOBEN
1236
+
#define BF_RCC_AHB4ENR_GPIOBEN_V(e) BF_RCC_AHB4ENR_GPIOBEN(BV_RCC_AHB4ENR_GPIOBEN__##e)
1237
+
#define BFM_RCC_AHB4ENR_GPIOBEN_V(v) BM_RCC_AHB4ENR_GPIOBEN
1238
+
#define BP_RCC_AHB4ENR_GPIOAEN 0
1239
+
#define BM_RCC_AHB4ENR_GPIOAEN 0x1
1240
+
#define BF_RCC_AHB4ENR_GPIOAEN(v) (((v) & 0x1) << 0)
1241
+
#define BFM_RCC_AHB4ENR_GPIOAEN(v) BM_RCC_AHB4ENR_GPIOAEN
1242
+
#define BF_RCC_AHB4ENR_GPIOAEN_V(e) BF_RCC_AHB4ENR_GPIOAEN(BV_RCC_AHB4ENR_GPIOAEN__##e)
1243
+
#define BFM_RCC_AHB4ENR_GPIOAEN_V(v) BM_RCC_AHB4ENR_GPIOAEN
1244
+
1245
+
#define REG_RCC_AHB4LPENR st_reg(RCC_AHB4LPENR)
1246
+
#define STA_RCC_AHB4LPENR (0x58024400 + 0x108)
1247
+
#define STO_RCC_AHB4LPENR (0x108)
1248
+
#define STT_RCC_AHB4LPENR STIO_32_RW
1249
+
#define STN_RCC_AHB4LPENR RCC_AHB4LPENR
1250
+
#define BP_RCC_AHB4LPENR_SRAM4EN 29
1251
+
#define BM_RCC_AHB4LPENR_SRAM4EN 0x20000000
1252
+
#define BF_RCC_AHB4LPENR_SRAM4EN(v) (((v) & 0x1) << 29)
1253
+
#define BFM_RCC_AHB4LPENR_SRAM4EN(v) BM_RCC_AHB4LPENR_SRAM4EN
1254
+
#define BF_RCC_AHB4LPENR_SRAM4EN_V(e) BF_RCC_AHB4LPENR_SRAM4EN(BV_RCC_AHB4LPENR_SRAM4EN__##e)
1255
+
#define BFM_RCC_AHB4LPENR_SRAM4EN_V(v) BM_RCC_AHB4LPENR_SRAM4EN
1256
+
#define BP_RCC_AHB4LPENR_BKPRAMEN 28
1257
+
#define BM_RCC_AHB4LPENR_BKPRAMEN 0x10000000
1258
+
#define BF_RCC_AHB4LPENR_BKPRAMEN(v) (((v) & 0x1) << 28)
1259
+
#define BFM_RCC_AHB4LPENR_BKPRAMEN(v) BM_RCC_AHB4LPENR_BKPRAMEN
1260
+
#define BF_RCC_AHB4LPENR_BKPRAMEN_V(e) BF_RCC_AHB4LPENR_BKPRAMEN(BV_RCC_AHB4LPENR_BKPRAMEN__##e)
1261
+
#define BFM_RCC_AHB4LPENR_BKPRAMEN_V(v) BM_RCC_AHB4LPENR_BKPRAMEN
1262
+
#define BP_RCC_AHB4LPENR_HSEMEN 25
1263
+
#define BM_RCC_AHB4LPENR_HSEMEN 0x2000000
1264
+
#define BF_RCC_AHB4LPENR_HSEMEN(v) (((v) & 0x1) << 25)
1265
+
#define BFM_RCC_AHB4LPENR_HSEMEN(v) BM_RCC_AHB4LPENR_HSEMEN
1266
+
#define BF_RCC_AHB4LPENR_HSEMEN_V(e) BF_RCC_AHB4LPENR_HSEMEN(BV_RCC_AHB4LPENR_HSEMEN__##e)
1267
+
#define BFM_RCC_AHB4LPENR_HSEMEN_V(v) BM_RCC_AHB4LPENR_HSEMEN
1268
+
#define BP_RCC_AHB4LPENR_ADC3EN 24
1269
+
#define BM_RCC_AHB4LPENR_ADC3EN 0x1000000
1270
+
#define BF_RCC_AHB4LPENR_ADC3EN(v) (((v) & 0x1) << 24)
1271
+
#define BFM_RCC_AHB4LPENR_ADC3EN(v) BM_RCC_AHB4LPENR_ADC3EN
1272
+
#define BF_RCC_AHB4LPENR_ADC3EN_V(e) BF_RCC_AHB4LPENR_ADC3EN(BV_RCC_AHB4LPENR_ADC3EN__##e)
1273
+
#define BFM_RCC_AHB4LPENR_ADC3EN_V(v) BM_RCC_AHB4LPENR_ADC3EN
1274
+
#define BP_RCC_AHB4LPENR_BDMAEN 21
1275
+
#define BM_RCC_AHB4LPENR_BDMAEN 0x200000
1276
+
#define BF_RCC_AHB4LPENR_BDMAEN(v) (((v) & 0x1) << 21)
1277
+
#define BFM_RCC_AHB4LPENR_BDMAEN(v) BM_RCC_AHB4LPENR_BDMAEN
1278
+
#define BF_RCC_AHB4LPENR_BDMAEN_V(e) BF_RCC_AHB4LPENR_BDMAEN(BV_RCC_AHB4LPENR_BDMAEN__##e)
1279
+
#define BFM_RCC_AHB4LPENR_BDMAEN_V(v) BM_RCC_AHB4LPENR_BDMAEN
1280
+
#define BP_RCC_AHB4LPENR_CRCEN 19
1281
+
#define BM_RCC_AHB4LPENR_CRCEN 0x80000
1282
+
#define BF_RCC_AHB4LPENR_CRCEN(v) (((v) & 0x1) << 19)
1283
+
#define BFM_RCC_AHB4LPENR_CRCEN(v) BM_RCC_AHB4LPENR_CRCEN
1284
+
#define BF_RCC_AHB4LPENR_CRCEN_V(e) BF_RCC_AHB4LPENR_CRCEN(BV_RCC_AHB4LPENR_CRCEN__##e)
1285
+
#define BFM_RCC_AHB4LPENR_CRCEN_V(v) BM_RCC_AHB4LPENR_CRCEN
1286
+
#define BP_RCC_AHB4LPENR_GPIOKEN 10
1287
+
#define BM_RCC_AHB4LPENR_GPIOKEN 0x400
1288
+
#define BF_RCC_AHB4LPENR_GPIOKEN(v) (((v) & 0x1) << 10)
1289
+
#define BFM_RCC_AHB4LPENR_GPIOKEN(v) BM_RCC_AHB4LPENR_GPIOKEN
1290
+
#define BF_RCC_AHB4LPENR_GPIOKEN_V(e) BF_RCC_AHB4LPENR_GPIOKEN(BV_RCC_AHB4LPENR_GPIOKEN__##e)
1291
+
#define BFM_RCC_AHB4LPENR_GPIOKEN_V(v) BM_RCC_AHB4LPENR_GPIOKEN
1292
+
#define BP_RCC_AHB4LPENR_GPIOJEN 9
1293
+
#define BM_RCC_AHB4LPENR_GPIOJEN 0x200
1294
+
#define BF_RCC_AHB4LPENR_GPIOJEN(v) (((v) & 0x1) << 9)
1295
+
#define BFM_RCC_AHB4LPENR_GPIOJEN(v) BM_RCC_AHB4LPENR_GPIOJEN
1296
+
#define BF_RCC_AHB4LPENR_GPIOJEN_V(e) BF_RCC_AHB4LPENR_GPIOJEN(BV_RCC_AHB4LPENR_GPIOJEN__##e)
1297
+
#define BFM_RCC_AHB4LPENR_GPIOJEN_V(v) BM_RCC_AHB4LPENR_GPIOJEN
1298
+
#define BP_RCC_AHB4LPENR_GPIOIEN 8
1299
+
#define BM_RCC_AHB4LPENR_GPIOIEN 0x100
1300
+
#define BF_RCC_AHB4LPENR_GPIOIEN(v) (((v) & 0x1) << 8)
1301
+
#define BFM_RCC_AHB4LPENR_GPIOIEN(v) BM_RCC_AHB4LPENR_GPIOIEN
1302
+
#define BF_RCC_AHB4LPENR_GPIOIEN_V(e) BF_RCC_AHB4LPENR_GPIOIEN(BV_RCC_AHB4LPENR_GPIOIEN__##e)
1303
+
#define BFM_RCC_AHB4LPENR_GPIOIEN_V(v) BM_RCC_AHB4LPENR_GPIOIEN
1304
+
#define BP_RCC_AHB4LPENR_GPIOHEN 7
1305
+
#define BM_RCC_AHB4LPENR_GPIOHEN 0x80
1306
+
#define BF_RCC_AHB4LPENR_GPIOHEN(v) (((v) & 0x1) << 7)
1307
+
#define BFM_RCC_AHB4LPENR_GPIOHEN(v) BM_RCC_AHB4LPENR_GPIOHEN
1308
+
#define BF_RCC_AHB4LPENR_GPIOHEN_V(e) BF_RCC_AHB4LPENR_GPIOHEN(BV_RCC_AHB4LPENR_GPIOHEN__##e)
1309
+
#define BFM_RCC_AHB4LPENR_GPIOHEN_V(v) BM_RCC_AHB4LPENR_GPIOHEN
1310
+
#define BP_RCC_AHB4LPENR_GPIOGEN 6
1311
+
#define BM_RCC_AHB4LPENR_GPIOGEN 0x40
1312
+
#define BF_RCC_AHB4LPENR_GPIOGEN(v) (((v) & 0x1) << 6)
1313
+
#define BFM_RCC_AHB4LPENR_GPIOGEN(v) BM_RCC_AHB4LPENR_GPIOGEN
1314
+
#define BF_RCC_AHB4LPENR_GPIOGEN_V(e) BF_RCC_AHB4LPENR_GPIOGEN(BV_RCC_AHB4LPENR_GPIOGEN__##e)
1315
+
#define BFM_RCC_AHB4LPENR_GPIOGEN_V(v) BM_RCC_AHB4LPENR_GPIOGEN
1316
+
#define BP_RCC_AHB4LPENR_GPIOFEN 5
1317
+
#define BM_RCC_AHB4LPENR_GPIOFEN 0x20
1318
+
#define BF_RCC_AHB4LPENR_GPIOFEN(v) (((v) & 0x1) << 5)
1319
+
#define BFM_RCC_AHB4LPENR_GPIOFEN(v) BM_RCC_AHB4LPENR_GPIOFEN
1320
+
#define BF_RCC_AHB4LPENR_GPIOFEN_V(e) BF_RCC_AHB4LPENR_GPIOFEN(BV_RCC_AHB4LPENR_GPIOFEN__##e)
1321
+
#define BFM_RCC_AHB4LPENR_GPIOFEN_V(v) BM_RCC_AHB4LPENR_GPIOFEN
1322
+
#define BP_RCC_AHB4LPENR_GPIOEEN 4
1323
+
#define BM_RCC_AHB4LPENR_GPIOEEN 0x10
1324
+
#define BF_RCC_AHB4LPENR_GPIOEEN(v) (((v) & 0x1) << 4)
1325
+
#define BFM_RCC_AHB4LPENR_GPIOEEN(v) BM_RCC_AHB4LPENR_GPIOEEN
1326
+
#define BF_RCC_AHB4LPENR_GPIOEEN_V(e) BF_RCC_AHB4LPENR_GPIOEEN(BV_RCC_AHB4LPENR_GPIOEEN__##e)
1327
+
#define BFM_RCC_AHB4LPENR_GPIOEEN_V(v) BM_RCC_AHB4LPENR_GPIOEEN
1328
+
#define BP_RCC_AHB4LPENR_GPIODEN 3
1329
+
#define BM_RCC_AHB4LPENR_GPIODEN 0x8
1330
+
#define BF_RCC_AHB4LPENR_GPIODEN(v) (((v) & 0x1) << 3)
1331
+
#define BFM_RCC_AHB4LPENR_GPIODEN(v) BM_RCC_AHB4LPENR_GPIODEN
1332
+
#define BF_RCC_AHB4LPENR_GPIODEN_V(e) BF_RCC_AHB4LPENR_GPIODEN(BV_RCC_AHB4LPENR_GPIODEN__##e)
1333
+
#define BFM_RCC_AHB4LPENR_GPIODEN_V(v) BM_RCC_AHB4LPENR_GPIODEN
1334
+
#define BP_RCC_AHB4LPENR_GPIOCEN 2
1335
+
#define BM_RCC_AHB4LPENR_GPIOCEN 0x4
1336
+
#define BF_RCC_AHB4LPENR_GPIOCEN(v) (((v) & 0x1) << 2)
1337
+
#define BFM_RCC_AHB4LPENR_GPIOCEN(v) BM_RCC_AHB4LPENR_GPIOCEN
1338
+
#define BF_RCC_AHB4LPENR_GPIOCEN_V(e) BF_RCC_AHB4LPENR_GPIOCEN(BV_RCC_AHB4LPENR_GPIOCEN__##e)
1339
+
#define BFM_RCC_AHB4LPENR_GPIOCEN_V(v) BM_RCC_AHB4LPENR_GPIOCEN
1340
+
#define BP_RCC_AHB4LPENR_GPIOBEN 1
1341
+
#define BM_RCC_AHB4LPENR_GPIOBEN 0x2
1342
+
#define BF_RCC_AHB4LPENR_GPIOBEN(v) (((v) & 0x1) << 1)
1343
+
#define BFM_RCC_AHB4LPENR_GPIOBEN(v) BM_RCC_AHB4LPENR_GPIOBEN
1344
+
#define BF_RCC_AHB4LPENR_GPIOBEN_V(e) BF_RCC_AHB4LPENR_GPIOBEN(BV_RCC_AHB4LPENR_GPIOBEN__##e)
1345
+
#define BFM_RCC_AHB4LPENR_GPIOBEN_V(v) BM_RCC_AHB4LPENR_GPIOBEN
1346
+
#define BP_RCC_AHB4LPENR_GPIOAEN 0
1347
+
#define BM_RCC_AHB4LPENR_GPIOAEN 0x1
1348
+
#define BF_RCC_AHB4LPENR_GPIOAEN(v) (((v) & 0x1) << 0)
1349
+
#define BFM_RCC_AHB4LPENR_GPIOAEN(v) BM_RCC_AHB4LPENR_GPIOAEN
1350
+
#define BF_RCC_AHB4LPENR_GPIOAEN_V(e) BF_RCC_AHB4LPENR_GPIOAEN(BV_RCC_AHB4LPENR_GPIOAEN__##e)
1351
+
#define BFM_RCC_AHB4LPENR_GPIOAEN_V(v) BM_RCC_AHB4LPENR_GPIOAEN
1352
+
1353
+
#define REG_RCC_APB3ENR st_reg(RCC_APB3ENR)
1354
+
#define STA_RCC_APB3ENR (0x58024400 + 0xe4)
1355
+
#define STO_RCC_APB3ENR (0xe4)
1356
+
#define STT_RCC_APB3ENR STIO_32_RW
1357
+
#define STN_RCC_APB3ENR RCC_APB3ENR
1358
+
#define BP_RCC_APB3ENR_WWDG1EN 6
1359
+
#define BM_RCC_APB3ENR_WWDG1EN 0x40
1360
+
#define BF_RCC_APB3ENR_WWDG1EN(v) (((v) & 0x1) << 6)
1361
+
#define BFM_RCC_APB3ENR_WWDG1EN(v) BM_RCC_APB3ENR_WWDG1EN
1362
+
#define BF_RCC_APB3ENR_WWDG1EN_V(e) BF_RCC_APB3ENR_WWDG1EN(BV_RCC_APB3ENR_WWDG1EN__##e)
1363
+
#define BFM_RCC_APB3ENR_WWDG1EN_V(v) BM_RCC_APB3ENR_WWDG1EN
1364
+
#define BP_RCC_APB3ENR_LTDCEN 3
1365
+
#define BM_RCC_APB3ENR_LTDCEN 0x8
1366
+
#define BF_RCC_APB3ENR_LTDCEN(v) (((v) & 0x1) << 3)
1367
+
#define BFM_RCC_APB3ENR_LTDCEN(v) BM_RCC_APB3ENR_LTDCEN
1368
+
#define BF_RCC_APB3ENR_LTDCEN_V(e) BF_RCC_APB3ENR_LTDCEN(BV_RCC_APB3ENR_LTDCEN__##e)
1369
+
#define BFM_RCC_APB3ENR_LTDCEN_V(v) BM_RCC_APB3ENR_LTDCEN
1370
+
1371
+
#define REG_RCC_APB3LPENR st_reg(RCC_APB3LPENR)
1372
+
#define STA_RCC_APB3LPENR (0x58024400 + 0x10c)
1373
+
#define STO_RCC_APB3LPENR (0x10c)
1374
+
#define STT_RCC_APB3LPENR STIO_32_RW
1375
+
#define STN_RCC_APB3LPENR RCC_APB3LPENR
1376
+
#define BP_RCC_APB3LPENR_WWDG1EN 6
1377
+
#define BM_RCC_APB3LPENR_WWDG1EN 0x40
1378
+
#define BF_RCC_APB3LPENR_WWDG1EN(v) (((v) & 0x1) << 6)
1379
+
#define BFM_RCC_APB3LPENR_WWDG1EN(v) BM_RCC_APB3LPENR_WWDG1EN
1380
+
#define BF_RCC_APB3LPENR_WWDG1EN_V(e) BF_RCC_APB3LPENR_WWDG1EN(BV_RCC_APB3LPENR_WWDG1EN__##e)
1381
+
#define BFM_RCC_APB3LPENR_WWDG1EN_V(v) BM_RCC_APB3LPENR_WWDG1EN
1382
+
#define BP_RCC_APB3LPENR_LTDCEN 3
1383
+
#define BM_RCC_APB3LPENR_LTDCEN 0x8
1384
+
#define BF_RCC_APB3LPENR_LTDCEN(v) (((v) & 0x1) << 3)
1385
+
#define BFM_RCC_APB3LPENR_LTDCEN(v) BM_RCC_APB3LPENR_LTDCEN
1386
+
#define BF_RCC_APB3LPENR_LTDCEN_V(e) BF_RCC_APB3LPENR_LTDCEN(BV_RCC_APB3LPENR_LTDCEN__##e)
1387
+
#define BFM_RCC_APB3LPENR_LTDCEN_V(v) BM_RCC_APB3LPENR_LTDCEN
1388
+
1389
+
#define REG_RCC_APB1LENR st_reg(RCC_APB1LENR)
1390
+
#define STA_RCC_APB1LENR (0x58024400 + 0xe8)
1391
+
#define STO_RCC_APB1LENR (0xe8)
1392
+
#define STT_RCC_APB1LENR STIO_32_RW
1393
+
#define STN_RCC_APB1LENR RCC_APB1LENR
1394
+
#define BP_RCC_APB1LENR_UART8EN 31
1395
+
#define BM_RCC_APB1LENR_UART8EN 0x80000000
1396
+
#define BF_RCC_APB1LENR_UART8EN(v) (((v) & 0x1) << 31)
1397
+
#define BFM_RCC_APB1LENR_UART8EN(v) BM_RCC_APB1LENR_UART8EN
1398
+
#define BF_RCC_APB1LENR_UART8EN_V(e) BF_RCC_APB1LENR_UART8EN(BV_RCC_APB1LENR_UART8EN__##e)
1399
+
#define BFM_RCC_APB1LENR_UART8EN_V(v) BM_RCC_APB1LENR_UART8EN
1400
+
#define BP_RCC_APB1LENR_UART7EN 30
1401
+
#define BM_RCC_APB1LENR_UART7EN 0x40000000
1402
+
#define BF_RCC_APB1LENR_UART7EN(v) (((v) & 0x1) << 30)
1403
+
#define BFM_RCC_APB1LENR_UART7EN(v) BM_RCC_APB1LENR_UART7EN
1404
+
#define BF_RCC_APB1LENR_UART7EN_V(e) BF_RCC_APB1LENR_UART7EN(BV_RCC_APB1LENR_UART7EN__##e)
1405
+
#define BFM_RCC_APB1LENR_UART7EN_V(v) BM_RCC_APB1LENR_UART7EN
1406
+
#define BP_RCC_APB1LENR_DAC12EN 29
1407
+
#define BM_RCC_APB1LENR_DAC12EN 0x20000000
1408
+
#define BF_RCC_APB1LENR_DAC12EN(v) (((v) & 0x1) << 29)
1409
+
#define BFM_RCC_APB1LENR_DAC12EN(v) BM_RCC_APB1LENR_DAC12EN
1410
+
#define BF_RCC_APB1LENR_DAC12EN_V(e) BF_RCC_APB1LENR_DAC12EN(BV_RCC_APB1LENR_DAC12EN__##e)
1411
+
#define BFM_RCC_APB1LENR_DAC12EN_V(v) BM_RCC_APB1LENR_DAC12EN
1412
+
#define BP_RCC_APB1LENR_CECEN 27
1413
+
#define BM_RCC_APB1LENR_CECEN 0x8000000
1414
+
#define BF_RCC_APB1LENR_CECEN(v) (((v) & 0x1) << 27)
1415
+
#define BFM_RCC_APB1LENR_CECEN(v) BM_RCC_APB1LENR_CECEN
1416
+
#define BF_RCC_APB1LENR_CECEN_V(e) BF_RCC_APB1LENR_CECEN(BV_RCC_APB1LENR_CECEN__##e)
1417
+
#define BFM_RCC_APB1LENR_CECEN_V(v) BM_RCC_APB1LENR_CECEN
1418
+
#define BP_RCC_APB1LENR_I2C3EN 23
1419
+
#define BM_RCC_APB1LENR_I2C3EN 0x800000
1420
+
#define BF_RCC_APB1LENR_I2C3EN(v) (((v) & 0x1) << 23)
1421
+
#define BFM_RCC_APB1LENR_I2C3EN(v) BM_RCC_APB1LENR_I2C3EN
1422
+
#define BF_RCC_APB1LENR_I2C3EN_V(e) BF_RCC_APB1LENR_I2C3EN(BV_RCC_APB1LENR_I2C3EN__##e)
1423
+
#define BFM_RCC_APB1LENR_I2C3EN_V(v) BM_RCC_APB1LENR_I2C3EN
1424
+
#define BP_RCC_APB1LENR_I2C2EN 22
1425
+
#define BM_RCC_APB1LENR_I2C2EN 0x400000
1426
+
#define BF_RCC_APB1LENR_I2C2EN(v) (((v) & 0x1) << 22)
1427
+
#define BFM_RCC_APB1LENR_I2C2EN(v) BM_RCC_APB1LENR_I2C2EN
1428
+
#define BF_RCC_APB1LENR_I2C2EN_V(e) BF_RCC_APB1LENR_I2C2EN(BV_RCC_APB1LENR_I2C2EN__##e)
1429
+
#define BFM_RCC_APB1LENR_I2C2EN_V(v) BM_RCC_APB1LENR_I2C2EN
1430
+
#define BP_RCC_APB1LENR_I2C1EN 21
1431
+
#define BM_RCC_APB1LENR_I2C1EN 0x200000
1432
+
#define BF_RCC_APB1LENR_I2C1EN(v) (((v) & 0x1) << 21)
1433
+
#define BFM_RCC_APB1LENR_I2C1EN(v) BM_RCC_APB1LENR_I2C1EN
1434
+
#define BF_RCC_APB1LENR_I2C1EN_V(e) BF_RCC_APB1LENR_I2C1EN(BV_RCC_APB1LENR_I2C1EN__##e)
1435
+
#define BFM_RCC_APB1LENR_I2C1EN_V(v) BM_RCC_APB1LENR_I2C1EN
1436
+
#define BP_RCC_APB1LENR_UART5EN 20
1437
+
#define BM_RCC_APB1LENR_UART5EN 0x100000
1438
+
#define BF_RCC_APB1LENR_UART5EN(v) (((v) & 0x1) << 20)
1439
+
#define BFM_RCC_APB1LENR_UART5EN(v) BM_RCC_APB1LENR_UART5EN
1440
+
#define BF_RCC_APB1LENR_UART5EN_V(e) BF_RCC_APB1LENR_UART5EN(BV_RCC_APB1LENR_UART5EN__##e)
1441
+
#define BFM_RCC_APB1LENR_UART5EN_V(v) BM_RCC_APB1LENR_UART5EN
1442
+
#define BP_RCC_APB1LENR_UART4EN 19
1443
+
#define BM_RCC_APB1LENR_UART4EN 0x80000
1444
+
#define BF_RCC_APB1LENR_UART4EN(v) (((v) & 0x1) << 19)
1445
+
#define BFM_RCC_APB1LENR_UART4EN(v) BM_RCC_APB1LENR_UART4EN
1446
+
#define BF_RCC_APB1LENR_UART4EN_V(e) BF_RCC_APB1LENR_UART4EN(BV_RCC_APB1LENR_UART4EN__##e)
1447
+
#define BFM_RCC_APB1LENR_UART4EN_V(v) BM_RCC_APB1LENR_UART4EN
1448
+
#define BP_RCC_APB1LENR_USART3EN 18
1449
+
#define BM_RCC_APB1LENR_USART3EN 0x40000
1450
+
#define BF_RCC_APB1LENR_USART3EN(v) (((v) & 0x1) << 18)
1451
+
#define BFM_RCC_APB1LENR_USART3EN(v) BM_RCC_APB1LENR_USART3EN
1452
+
#define BF_RCC_APB1LENR_USART3EN_V(e) BF_RCC_APB1LENR_USART3EN(BV_RCC_APB1LENR_USART3EN__##e)
1453
+
#define BFM_RCC_APB1LENR_USART3EN_V(v) BM_RCC_APB1LENR_USART3EN
1454
+
#define BP_RCC_APB1LENR_USART2EN 17
1455
+
#define BM_RCC_APB1LENR_USART2EN 0x20000
1456
+
#define BF_RCC_APB1LENR_USART2EN(v) (((v) & 0x1) << 17)
1457
+
#define BFM_RCC_APB1LENR_USART2EN(v) BM_RCC_APB1LENR_USART2EN
1458
+
#define BF_RCC_APB1LENR_USART2EN_V(e) BF_RCC_APB1LENR_USART2EN(BV_RCC_APB1LENR_USART2EN__##e)
1459
+
#define BFM_RCC_APB1LENR_USART2EN_V(v) BM_RCC_APB1LENR_USART2EN
1460
+
#define BP_RCC_APB1LENR_SPDIFRXEN 16
1461
+
#define BM_RCC_APB1LENR_SPDIFRXEN 0x10000
1462
+
#define BF_RCC_APB1LENR_SPDIFRXEN(v) (((v) & 0x1) << 16)
1463
+
#define BFM_RCC_APB1LENR_SPDIFRXEN(v) BM_RCC_APB1LENR_SPDIFRXEN
1464
+
#define BF_RCC_APB1LENR_SPDIFRXEN_V(e) BF_RCC_APB1LENR_SPDIFRXEN(BV_RCC_APB1LENR_SPDIFRXEN__##e)
1465
+
#define BFM_RCC_APB1LENR_SPDIFRXEN_V(v) BM_RCC_APB1LENR_SPDIFRXEN
1466
+
#define BP_RCC_APB1LENR_SPI3EN 15
1467
+
#define BM_RCC_APB1LENR_SPI3EN 0x8000
1468
+
#define BF_RCC_APB1LENR_SPI3EN(v) (((v) & 0x1) << 15)
1469
+
#define BFM_RCC_APB1LENR_SPI3EN(v) BM_RCC_APB1LENR_SPI3EN
1470
+
#define BF_RCC_APB1LENR_SPI3EN_V(e) BF_RCC_APB1LENR_SPI3EN(BV_RCC_APB1LENR_SPI3EN__##e)
1471
+
#define BFM_RCC_APB1LENR_SPI3EN_V(v) BM_RCC_APB1LENR_SPI3EN
1472
+
#define BP_RCC_APB1LENR_SPI2EN 14
1473
+
#define BM_RCC_APB1LENR_SPI2EN 0x4000
1474
+
#define BF_RCC_APB1LENR_SPI2EN(v) (((v) & 0x1) << 14)
1475
+
#define BFM_RCC_APB1LENR_SPI2EN(v) BM_RCC_APB1LENR_SPI2EN
1476
+
#define BF_RCC_APB1LENR_SPI2EN_V(e) BF_RCC_APB1LENR_SPI2EN(BV_RCC_APB1LENR_SPI2EN__##e)
1477
+
#define BFM_RCC_APB1LENR_SPI2EN_V(v) BM_RCC_APB1LENR_SPI2EN
1478
+
#define BP_RCC_APB1LENR_LPTIM1EN 9
1479
+
#define BM_RCC_APB1LENR_LPTIM1EN 0x200
1480
+
#define BF_RCC_APB1LENR_LPTIM1EN(v) (((v) & 0x1) << 9)
1481
+
#define BFM_RCC_APB1LENR_LPTIM1EN(v) BM_RCC_APB1LENR_LPTIM1EN
1482
+
#define BF_RCC_APB1LENR_LPTIM1EN_V(e) BF_RCC_APB1LENR_LPTIM1EN(BV_RCC_APB1LENR_LPTIM1EN__##e)
1483
+
#define BFM_RCC_APB1LENR_LPTIM1EN_V(v) BM_RCC_APB1LENR_LPTIM1EN
1484
+
#define BP_RCC_APB1LENR_TIM14EN 8
1485
+
#define BM_RCC_APB1LENR_TIM14EN 0x100
1486
+
#define BF_RCC_APB1LENR_TIM14EN(v) (((v) & 0x1) << 8)
1487
+
#define BFM_RCC_APB1LENR_TIM14EN(v) BM_RCC_APB1LENR_TIM14EN
1488
+
#define BF_RCC_APB1LENR_TIM14EN_V(e) BF_RCC_APB1LENR_TIM14EN(BV_RCC_APB1LENR_TIM14EN__##e)
1489
+
#define BFM_RCC_APB1LENR_TIM14EN_V(v) BM_RCC_APB1LENR_TIM14EN
1490
+
#define BP_RCC_APB1LENR_TIM13EN 7
1491
+
#define BM_RCC_APB1LENR_TIM13EN 0x80
1492
+
#define BF_RCC_APB1LENR_TIM13EN(v) (((v) & 0x1) << 7)
1493
+
#define BFM_RCC_APB1LENR_TIM13EN(v) BM_RCC_APB1LENR_TIM13EN
1494
+
#define BF_RCC_APB1LENR_TIM13EN_V(e) BF_RCC_APB1LENR_TIM13EN(BV_RCC_APB1LENR_TIM13EN__##e)
1495
+
#define BFM_RCC_APB1LENR_TIM13EN_V(v) BM_RCC_APB1LENR_TIM13EN
1496
+
#define BP_RCC_APB1LENR_TIM12EN 6
1497
+
#define BM_RCC_APB1LENR_TIM12EN 0x40
1498
+
#define BF_RCC_APB1LENR_TIM12EN(v) (((v) & 0x1) << 6)
1499
+
#define BFM_RCC_APB1LENR_TIM12EN(v) BM_RCC_APB1LENR_TIM12EN
1500
+
#define BF_RCC_APB1LENR_TIM12EN_V(e) BF_RCC_APB1LENR_TIM12EN(BV_RCC_APB1LENR_TIM12EN__##e)
1501
+
#define BFM_RCC_APB1LENR_TIM12EN_V(v) BM_RCC_APB1LENR_TIM12EN
1502
+
#define BP_RCC_APB1LENR_TIM7EN 5
1503
+
#define BM_RCC_APB1LENR_TIM7EN 0x20
1504
+
#define BF_RCC_APB1LENR_TIM7EN(v) (((v) & 0x1) << 5)
1505
+
#define BFM_RCC_APB1LENR_TIM7EN(v) BM_RCC_APB1LENR_TIM7EN
1506
+
#define BF_RCC_APB1LENR_TIM7EN_V(e) BF_RCC_APB1LENR_TIM7EN(BV_RCC_APB1LENR_TIM7EN__##e)
1507
+
#define BFM_RCC_APB1LENR_TIM7EN_V(v) BM_RCC_APB1LENR_TIM7EN
1508
+
#define BP_RCC_APB1LENR_TIM6EN 4
1509
+
#define BM_RCC_APB1LENR_TIM6EN 0x10
1510
+
#define BF_RCC_APB1LENR_TIM6EN(v) (((v) & 0x1) << 4)
1511
+
#define BFM_RCC_APB1LENR_TIM6EN(v) BM_RCC_APB1LENR_TIM6EN
1512
+
#define BF_RCC_APB1LENR_TIM6EN_V(e) BF_RCC_APB1LENR_TIM6EN(BV_RCC_APB1LENR_TIM6EN__##e)
1513
+
#define BFM_RCC_APB1LENR_TIM6EN_V(v) BM_RCC_APB1LENR_TIM6EN
1514
+
#define BP_RCC_APB1LENR_TIM5EN 3
1515
+
#define BM_RCC_APB1LENR_TIM5EN 0x8
1516
+
#define BF_RCC_APB1LENR_TIM5EN(v) (((v) & 0x1) << 3)
1517
+
#define BFM_RCC_APB1LENR_TIM5EN(v) BM_RCC_APB1LENR_TIM5EN
1518
+
#define BF_RCC_APB1LENR_TIM5EN_V(e) BF_RCC_APB1LENR_TIM5EN(BV_RCC_APB1LENR_TIM5EN__##e)
1519
+
#define BFM_RCC_APB1LENR_TIM5EN_V(v) BM_RCC_APB1LENR_TIM5EN
1520
+
#define BP_RCC_APB1LENR_TIM4EN 2
1521
+
#define BM_RCC_APB1LENR_TIM4EN 0x4
1522
+
#define BF_RCC_APB1LENR_TIM4EN(v) (((v) & 0x1) << 2)
1523
+
#define BFM_RCC_APB1LENR_TIM4EN(v) BM_RCC_APB1LENR_TIM4EN
1524
+
#define BF_RCC_APB1LENR_TIM4EN_V(e) BF_RCC_APB1LENR_TIM4EN(BV_RCC_APB1LENR_TIM4EN__##e)
1525
+
#define BFM_RCC_APB1LENR_TIM4EN_V(v) BM_RCC_APB1LENR_TIM4EN
1526
+
#define BP_RCC_APB1LENR_TIM3EN 1
1527
+
#define BM_RCC_APB1LENR_TIM3EN 0x2
1528
+
#define BF_RCC_APB1LENR_TIM3EN(v) (((v) & 0x1) << 1)
1529
+
#define BFM_RCC_APB1LENR_TIM3EN(v) BM_RCC_APB1LENR_TIM3EN
1530
+
#define BF_RCC_APB1LENR_TIM3EN_V(e) BF_RCC_APB1LENR_TIM3EN(BV_RCC_APB1LENR_TIM3EN__##e)
1531
+
#define BFM_RCC_APB1LENR_TIM3EN_V(v) BM_RCC_APB1LENR_TIM3EN
1532
+
#define BP_RCC_APB1LENR_TIM2EN 0
1533
+
#define BM_RCC_APB1LENR_TIM2EN 0x1
1534
+
#define BF_RCC_APB1LENR_TIM2EN(v) (((v) & 0x1) << 0)
1535
+
#define BFM_RCC_APB1LENR_TIM2EN(v) BM_RCC_APB1LENR_TIM2EN
1536
+
#define BF_RCC_APB1LENR_TIM2EN_V(e) BF_RCC_APB1LENR_TIM2EN(BV_RCC_APB1LENR_TIM2EN__##e)
1537
+
#define BFM_RCC_APB1LENR_TIM2EN_V(v) BM_RCC_APB1LENR_TIM2EN
1538
+
1539
+
#define REG_RCC_APB1LLPENR st_reg(RCC_APB1LLPENR)
1540
+
#define STA_RCC_APB1LLPENR (0x58024400 + 0x110)
1541
+
#define STO_RCC_APB1LLPENR (0x110)
1542
+
#define STT_RCC_APB1LLPENR STIO_32_RW
1543
+
#define STN_RCC_APB1LLPENR RCC_APB1LLPENR
1544
+
#define BP_RCC_APB1LLPENR_UART8EN 31
1545
+
#define BM_RCC_APB1LLPENR_UART8EN 0x80000000
1546
+
#define BF_RCC_APB1LLPENR_UART8EN(v) (((v) & 0x1) << 31)
1547
+
#define BFM_RCC_APB1LLPENR_UART8EN(v) BM_RCC_APB1LLPENR_UART8EN
1548
+
#define BF_RCC_APB1LLPENR_UART8EN_V(e) BF_RCC_APB1LLPENR_UART8EN(BV_RCC_APB1LLPENR_UART8EN__##e)
1549
+
#define BFM_RCC_APB1LLPENR_UART8EN_V(v) BM_RCC_APB1LLPENR_UART8EN
1550
+
#define BP_RCC_APB1LLPENR_UART7EN 30
1551
+
#define BM_RCC_APB1LLPENR_UART7EN 0x40000000
1552
+
#define BF_RCC_APB1LLPENR_UART7EN(v) (((v) & 0x1) << 30)
1553
+
#define BFM_RCC_APB1LLPENR_UART7EN(v) BM_RCC_APB1LLPENR_UART7EN
1554
+
#define BF_RCC_APB1LLPENR_UART7EN_V(e) BF_RCC_APB1LLPENR_UART7EN(BV_RCC_APB1LLPENR_UART7EN__##e)
1555
+
#define BFM_RCC_APB1LLPENR_UART7EN_V(v) BM_RCC_APB1LLPENR_UART7EN
1556
+
#define BP_RCC_APB1LLPENR_DAC12EN 29
1557
+
#define BM_RCC_APB1LLPENR_DAC12EN 0x20000000
1558
+
#define BF_RCC_APB1LLPENR_DAC12EN(v) (((v) & 0x1) << 29)
1559
+
#define BFM_RCC_APB1LLPENR_DAC12EN(v) BM_RCC_APB1LLPENR_DAC12EN
1560
+
#define BF_RCC_APB1LLPENR_DAC12EN_V(e) BF_RCC_APB1LLPENR_DAC12EN(BV_RCC_APB1LLPENR_DAC12EN__##e)
1561
+
#define BFM_RCC_APB1LLPENR_DAC12EN_V(v) BM_RCC_APB1LLPENR_DAC12EN
1562
+
#define BP_RCC_APB1LLPENR_CECEN 27
1563
+
#define BM_RCC_APB1LLPENR_CECEN 0x8000000
1564
+
#define BF_RCC_APB1LLPENR_CECEN(v) (((v) & 0x1) << 27)
1565
+
#define BFM_RCC_APB1LLPENR_CECEN(v) BM_RCC_APB1LLPENR_CECEN
1566
+
#define BF_RCC_APB1LLPENR_CECEN_V(e) BF_RCC_APB1LLPENR_CECEN(BV_RCC_APB1LLPENR_CECEN__##e)
1567
+
#define BFM_RCC_APB1LLPENR_CECEN_V(v) BM_RCC_APB1LLPENR_CECEN
1568
+
#define BP_RCC_APB1LLPENR_I2C3EN 23
1569
+
#define BM_RCC_APB1LLPENR_I2C3EN 0x800000
1570
+
#define BF_RCC_APB1LLPENR_I2C3EN(v) (((v) & 0x1) << 23)
1571
+
#define BFM_RCC_APB1LLPENR_I2C3EN(v) BM_RCC_APB1LLPENR_I2C3EN
1572
+
#define BF_RCC_APB1LLPENR_I2C3EN_V(e) BF_RCC_APB1LLPENR_I2C3EN(BV_RCC_APB1LLPENR_I2C3EN__##e)
1573
+
#define BFM_RCC_APB1LLPENR_I2C3EN_V(v) BM_RCC_APB1LLPENR_I2C3EN
1574
+
#define BP_RCC_APB1LLPENR_I2C2EN 22
1575
+
#define BM_RCC_APB1LLPENR_I2C2EN 0x400000
1576
+
#define BF_RCC_APB1LLPENR_I2C2EN(v) (((v) & 0x1) << 22)
1577
+
#define BFM_RCC_APB1LLPENR_I2C2EN(v) BM_RCC_APB1LLPENR_I2C2EN
1578
+
#define BF_RCC_APB1LLPENR_I2C2EN_V(e) BF_RCC_APB1LLPENR_I2C2EN(BV_RCC_APB1LLPENR_I2C2EN__##e)
1579
+
#define BFM_RCC_APB1LLPENR_I2C2EN_V(v) BM_RCC_APB1LLPENR_I2C2EN
1580
+
#define BP_RCC_APB1LLPENR_I2C1EN 21
1581
+
#define BM_RCC_APB1LLPENR_I2C1EN 0x200000
1582
+
#define BF_RCC_APB1LLPENR_I2C1EN(v) (((v) & 0x1) << 21)
1583
+
#define BFM_RCC_APB1LLPENR_I2C1EN(v) BM_RCC_APB1LLPENR_I2C1EN
1584
+
#define BF_RCC_APB1LLPENR_I2C1EN_V(e) BF_RCC_APB1LLPENR_I2C1EN(BV_RCC_APB1LLPENR_I2C1EN__##e)
1585
+
#define BFM_RCC_APB1LLPENR_I2C1EN_V(v) BM_RCC_APB1LLPENR_I2C1EN
1586
+
#define BP_RCC_APB1LLPENR_UART5EN 20
1587
+
#define BM_RCC_APB1LLPENR_UART5EN 0x100000
1588
+
#define BF_RCC_APB1LLPENR_UART5EN(v) (((v) & 0x1) << 20)
1589
+
#define BFM_RCC_APB1LLPENR_UART5EN(v) BM_RCC_APB1LLPENR_UART5EN
1590
+
#define BF_RCC_APB1LLPENR_UART5EN_V(e) BF_RCC_APB1LLPENR_UART5EN(BV_RCC_APB1LLPENR_UART5EN__##e)
1591
+
#define BFM_RCC_APB1LLPENR_UART5EN_V(v) BM_RCC_APB1LLPENR_UART5EN
1592
+
#define BP_RCC_APB1LLPENR_UART4EN 19
1593
+
#define BM_RCC_APB1LLPENR_UART4EN 0x80000
1594
+
#define BF_RCC_APB1LLPENR_UART4EN(v) (((v) & 0x1) << 19)
1595
+
#define BFM_RCC_APB1LLPENR_UART4EN(v) BM_RCC_APB1LLPENR_UART4EN
1596
+
#define BF_RCC_APB1LLPENR_UART4EN_V(e) BF_RCC_APB1LLPENR_UART4EN(BV_RCC_APB1LLPENR_UART4EN__##e)
1597
+
#define BFM_RCC_APB1LLPENR_UART4EN_V(v) BM_RCC_APB1LLPENR_UART4EN
1598
+
#define BP_RCC_APB1LLPENR_USART3EN 18
1599
+
#define BM_RCC_APB1LLPENR_USART3EN 0x40000
1600
+
#define BF_RCC_APB1LLPENR_USART3EN(v) (((v) & 0x1) << 18)
1601
+
#define BFM_RCC_APB1LLPENR_USART3EN(v) BM_RCC_APB1LLPENR_USART3EN
1602
+
#define BF_RCC_APB1LLPENR_USART3EN_V(e) BF_RCC_APB1LLPENR_USART3EN(BV_RCC_APB1LLPENR_USART3EN__##e)
1603
+
#define BFM_RCC_APB1LLPENR_USART3EN_V(v) BM_RCC_APB1LLPENR_USART3EN
1604
+
#define BP_RCC_APB1LLPENR_USART2EN 17
1605
+
#define BM_RCC_APB1LLPENR_USART2EN 0x20000
1606
+
#define BF_RCC_APB1LLPENR_USART2EN(v) (((v) & 0x1) << 17)
1607
+
#define BFM_RCC_APB1LLPENR_USART2EN(v) BM_RCC_APB1LLPENR_USART2EN
1608
+
#define BF_RCC_APB1LLPENR_USART2EN_V(e) BF_RCC_APB1LLPENR_USART2EN(BV_RCC_APB1LLPENR_USART2EN__##e)
1609
+
#define BFM_RCC_APB1LLPENR_USART2EN_V(v) BM_RCC_APB1LLPENR_USART2EN
1610
+
#define BP_RCC_APB1LLPENR_SPDIFRXEN 16
1611
+
#define BM_RCC_APB1LLPENR_SPDIFRXEN 0x10000
1612
+
#define BF_RCC_APB1LLPENR_SPDIFRXEN(v) (((v) & 0x1) << 16)
1613
+
#define BFM_RCC_APB1LLPENR_SPDIFRXEN(v) BM_RCC_APB1LLPENR_SPDIFRXEN
1614
+
#define BF_RCC_APB1LLPENR_SPDIFRXEN_V(e) BF_RCC_APB1LLPENR_SPDIFRXEN(BV_RCC_APB1LLPENR_SPDIFRXEN__##e)
1615
+
#define BFM_RCC_APB1LLPENR_SPDIFRXEN_V(v) BM_RCC_APB1LLPENR_SPDIFRXEN
1616
+
#define BP_RCC_APB1LLPENR_SPI3EN 15
1617
+
#define BM_RCC_APB1LLPENR_SPI3EN 0x8000
1618
+
#define BF_RCC_APB1LLPENR_SPI3EN(v) (((v) & 0x1) << 15)
1619
+
#define BFM_RCC_APB1LLPENR_SPI3EN(v) BM_RCC_APB1LLPENR_SPI3EN
1620
+
#define BF_RCC_APB1LLPENR_SPI3EN_V(e) BF_RCC_APB1LLPENR_SPI3EN(BV_RCC_APB1LLPENR_SPI3EN__##e)
1621
+
#define BFM_RCC_APB1LLPENR_SPI3EN_V(v) BM_RCC_APB1LLPENR_SPI3EN
1622
+
#define BP_RCC_APB1LLPENR_SPI2EN 14
1623
+
#define BM_RCC_APB1LLPENR_SPI2EN 0x4000
1624
+
#define BF_RCC_APB1LLPENR_SPI2EN(v) (((v) & 0x1) << 14)
1625
+
#define BFM_RCC_APB1LLPENR_SPI2EN(v) BM_RCC_APB1LLPENR_SPI2EN
1626
+
#define BF_RCC_APB1LLPENR_SPI2EN_V(e) BF_RCC_APB1LLPENR_SPI2EN(BV_RCC_APB1LLPENR_SPI2EN__##e)
1627
+
#define BFM_RCC_APB1LLPENR_SPI2EN_V(v) BM_RCC_APB1LLPENR_SPI2EN
1628
+
#define BP_RCC_APB1LLPENR_LPTIM1EN 9
1629
+
#define BM_RCC_APB1LLPENR_LPTIM1EN 0x200
1630
+
#define BF_RCC_APB1LLPENR_LPTIM1EN(v) (((v) & 0x1) << 9)
1631
+
#define BFM_RCC_APB1LLPENR_LPTIM1EN(v) BM_RCC_APB1LLPENR_LPTIM1EN
1632
+
#define BF_RCC_APB1LLPENR_LPTIM1EN_V(e) BF_RCC_APB1LLPENR_LPTIM1EN(BV_RCC_APB1LLPENR_LPTIM1EN__##e)
1633
+
#define BFM_RCC_APB1LLPENR_LPTIM1EN_V(v) BM_RCC_APB1LLPENR_LPTIM1EN
1634
+
#define BP_RCC_APB1LLPENR_TIM14EN 8
1635
+
#define BM_RCC_APB1LLPENR_TIM14EN 0x100
1636
+
#define BF_RCC_APB1LLPENR_TIM14EN(v) (((v) & 0x1) << 8)
1637
+
#define BFM_RCC_APB1LLPENR_TIM14EN(v) BM_RCC_APB1LLPENR_TIM14EN
1638
+
#define BF_RCC_APB1LLPENR_TIM14EN_V(e) BF_RCC_APB1LLPENR_TIM14EN(BV_RCC_APB1LLPENR_TIM14EN__##e)
1639
+
#define BFM_RCC_APB1LLPENR_TIM14EN_V(v) BM_RCC_APB1LLPENR_TIM14EN
1640
+
#define BP_RCC_APB1LLPENR_TIM13EN 7
1641
+
#define BM_RCC_APB1LLPENR_TIM13EN 0x80
1642
+
#define BF_RCC_APB1LLPENR_TIM13EN(v) (((v) & 0x1) << 7)
1643
+
#define BFM_RCC_APB1LLPENR_TIM13EN(v) BM_RCC_APB1LLPENR_TIM13EN
1644
+
#define BF_RCC_APB1LLPENR_TIM13EN_V(e) BF_RCC_APB1LLPENR_TIM13EN(BV_RCC_APB1LLPENR_TIM13EN__##e)
1645
+
#define BFM_RCC_APB1LLPENR_TIM13EN_V(v) BM_RCC_APB1LLPENR_TIM13EN
1646
+
#define BP_RCC_APB1LLPENR_TIM12EN 6
1647
+
#define BM_RCC_APB1LLPENR_TIM12EN 0x40
1648
+
#define BF_RCC_APB1LLPENR_TIM12EN(v) (((v) & 0x1) << 6)
1649
+
#define BFM_RCC_APB1LLPENR_TIM12EN(v) BM_RCC_APB1LLPENR_TIM12EN
1650
+
#define BF_RCC_APB1LLPENR_TIM12EN_V(e) BF_RCC_APB1LLPENR_TIM12EN(BV_RCC_APB1LLPENR_TIM12EN__##e)
1651
+
#define BFM_RCC_APB1LLPENR_TIM12EN_V(v) BM_RCC_APB1LLPENR_TIM12EN
1652
+
#define BP_RCC_APB1LLPENR_TIM7EN 5
1653
+
#define BM_RCC_APB1LLPENR_TIM7EN 0x20
1654
+
#define BF_RCC_APB1LLPENR_TIM7EN(v) (((v) & 0x1) << 5)
1655
+
#define BFM_RCC_APB1LLPENR_TIM7EN(v) BM_RCC_APB1LLPENR_TIM7EN
1656
+
#define BF_RCC_APB1LLPENR_TIM7EN_V(e) BF_RCC_APB1LLPENR_TIM7EN(BV_RCC_APB1LLPENR_TIM7EN__##e)
1657
+
#define BFM_RCC_APB1LLPENR_TIM7EN_V(v) BM_RCC_APB1LLPENR_TIM7EN
1658
+
#define BP_RCC_APB1LLPENR_TIM6EN 4
1659
+
#define BM_RCC_APB1LLPENR_TIM6EN 0x10
1660
+
#define BF_RCC_APB1LLPENR_TIM6EN(v) (((v) & 0x1) << 4)
1661
+
#define BFM_RCC_APB1LLPENR_TIM6EN(v) BM_RCC_APB1LLPENR_TIM6EN
1662
+
#define BF_RCC_APB1LLPENR_TIM6EN_V(e) BF_RCC_APB1LLPENR_TIM6EN(BV_RCC_APB1LLPENR_TIM6EN__##e)
1663
+
#define BFM_RCC_APB1LLPENR_TIM6EN_V(v) BM_RCC_APB1LLPENR_TIM6EN
1664
+
#define BP_RCC_APB1LLPENR_TIM5EN 3
1665
+
#define BM_RCC_APB1LLPENR_TIM5EN 0x8
1666
+
#define BF_RCC_APB1LLPENR_TIM5EN(v) (((v) & 0x1) << 3)
1667
+
#define BFM_RCC_APB1LLPENR_TIM5EN(v) BM_RCC_APB1LLPENR_TIM5EN
1668
+
#define BF_RCC_APB1LLPENR_TIM5EN_V(e) BF_RCC_APB1LLPENR_TIM5EN(BV_RCC_APB1LLPENR_TIM5EN__##e)
1669
+
#define BFM_RCC_APB1LLPENR_TIM5EN_V(v) BM_RCC_APB1LLPENR_TIM5EN
1670
+
#define BP_RCC_APB1LLPENR_TIM4EN 2
1671
+
#define BM_RCC_APB1LLPENR_TIM4EN 0x4
1672
+
#define BF_RCC_APB1LLPENR_TIM4EN(v) (((v) & 0x1) << 2)
1673
+
#define BFM_RCC_APB1LLPENR_TIM4EN(v) BM_RCC_APB1LLPENR_TIM4EN
1674
+
#define BF_RCC_APB1LLPENR_TIM4EN_V(e) BF_RCC_APB1LLPENR_TIM4EN(BV_RCC_APB1LLPENR_TIM4EN__##e)
1675
+
#define BFM_RCC_APB1LLPENR_TIM4EN_V(v) BM_RCC_APB1LLPENR_TIM4EN
1676
+
#define BP_RCC_APB1LLPENR_TIM3EN 1
1677
+
#define BM_RCC_APB1LLPENR_TIM3EN 0x2
1678
+
#define BF_RCC_APB1LLPENR_TIM3EN(v) (((v) & 0x1) << 1)
1679
+
#define BFM_RCC_APB1LLPENR_TIM3EN(v) BM_RCC_APB1LLPENR_TIM3EN
1680
+
#define BF_RCC_APB1LLPENR_TIM3EN_V(e) BF_RCC_APB1LLPENR_TIM3EN(BV_RCC_APB1LLPENR_TIM3EN__##e)
1681
+
#define BFM_RCC_APB1LLPENR_TIM3EN_V(v) BM_RCC_APB1LLPENR_TIM3EN
1682
+
#define BP_RCC_APB1LLPENR_TIM2EN 0
1683
+
#define BM_RCC_APB1LLPENR_TIM2EN 0x1
1684
+
#define BF_RCC_APB1LLPENR_TIM2EN(v) (((v) & 0x1) << 0)
1685
+
#define BFM_RCC_APB1LLPENR_TIM2EN(v) BM_RCC_APB1LLPENR_TIM2EN
1686
+
#define BF_RCC_APB1LLPENR_TIM2EN_V(e) BF_RCC_APB1LLPENR_TIM2EN(BV_RCC_APB1LLPENR_TIM2EN__##e)
1687
+
#define BFM_RCC_APB1LLPENR_TIM2EN_V(v) BM_RCC_APB1LLPENR_TIM2EN
1688
+
1689
+
#define REG_RCC_APB1HENR st_reg(RCC_APB1HENR)
1690
+
#define STA_RCC_APB1HENR (0x58024400 + 0xec)
1691
+
#define STO_RCC_APB1HENR (0xec)
1692
+
#define STT_RCC_APB1HENR STIO_32_RW
1693
+
#define STN_RCC_APB1HENR RCC_APB1HENR
1694
+
#define BP_RCC_APB1HENR_FDCANEN 8
1695
+
#define BM_RCC_APB1HENR_FDCANEN 0x100
1696
+
#define BF_RCC_APB1HENR_FDCANEN(v) (((v) & 0x1) << 8)
1697
+
#define BFM_RCC_APB1HENR_FDCANEN(v) BM_RCC_APB1HENR_FDCANEN
1698
+
#define BF_RCC_APB1HENR_FDCANEN_V(e) BF_RCC_APB1HENR_FDCANEN(BV_RCC_APB1HENR_FDCANEN__##e)
1699
+
#define BFM_RCC_APB1HENR_FDCANEN_V(v) BM_RCC_APB1HENR_FDCANEN
1700
+
#define BP_RCC_APB1HENR_MDIOSEN 5
1701
+
#define BM_RCC_APB1HENR_MDIOSEN 0x20
1702
+
#define BF_RCC_APB1HENR_MDIOSEN(v) (((v) & 0x1) << 5)
1703
+
#define BFM_RCC_APB1HENR_MDIOSEN(v) BM_RCC_APB1HENR_MDIOSEN
1704
+
#define BF_RCC_APB1HENR_MDIOSEN_V(e) BF_RCC_APB1HENR_MDIOSEN(BV_RCC_APB1HENR_MDIOSEN__##e)
1705
+
#define BFM_RCC_APB1HENR_MDIOSEN_V(v) BM_RCC_APB1HENR_MDIOSEN
1706
+
#define BP_RCC_APB1HENR_OPAMPEN 4
1707
+
#define BM_RCC_APB1HENR_OPAMPEN 0x10
1708
+
#define BF_RCC_APB1HENR_OPAMPEN(v) (((v) & 0x1) << 4)
1709
+
#define BFM_RCC_APB1HENR_OPAMPEN(v) BM_RCC_APB1HENR_OPAMPEN
1710
+
#define BF_RCC_APB1HENR_OPAMPEN_V(e) BF_RCC_APB1HENR_OPAMPEN(BV_RCC_APB1HENR_OPAMPEN__##e)
1711
+
#define BFM_RCC_APB1HENR_OPAMPEN_V(v) BM_RCC_APB1HENR_OPAMPEN
1712
+
#define BP_RCC_APB1HENR_SWPEN 2
1713
+
#define BM_RCC_APB1HENR_SWPEN 0x4
1714
+
#define BF_RCC_APB1HENR_SWPEN(v) (((v) & 0x1) << 2)
1715
+
#define BFM_RCC_APB1HENR_SWPEN(v) BM_RCC_APB1HENR_SWPEN
1716
+
#define BF_RCC_APB1HENR_SWPEN_V(e) BF_RCC_APB1HENR_SWPEN(BV_RCC_APB1HENR_SWPEN__##e)
1717
+
#define BFM_RCC_APB1HENR_SWPEN_V(v) BM_RCC_APB1HENR_SWPEN
1718
+
#define BP_RCC_APB1HENR_CRSEN 1
1719
+
#define BM_RCC_APB1HENR_CRSEN 0x2
1720
+
#define BF_RCC_APB1HENR_CRSEN(v) (((v) & 0x1) << 1)
1721
+
#define BFM_RCC_APB1HENR_CRSEN(v) BM_RCC_APB1HENR_CRSEN
1722
+
#define BF_RCC_APB1HENR_CRSEN_V(e) BF_RCC_APB1HENR_CRSEN(BV_RCC_APB1HENR_CRSEN__##e)
1723
+
#define BFM_RCC_APB1HENR_CRSEN_V(v) BM_RCC_APB1HENR_CRSEN
1724
+
1725
+
#define REG_RCC_APB1HLPENR st_reg(RCC_APB1HLPENR)
1726
+
#define STA_RCC_APB1HLPENR (0x58024400 + 0x114)
1727
+
#define STO_RCC_APB1HLPENR (0x114)
1728
+
#define STT_RCC_APB1HLPENR STIO_32_RW
1729
+
#define STN_RCC_APB1HLPENR RCC_APB1HLPENR
1730
+
#define BP_RCC_APB1HLPENR_FDCANEN 8
1731
+
#define BM_RCC_APB1HLPENR_FDCANEN 0x100
1732
+
#define BF_RCC_APB1HLPENR_FDCANEN(v) (((v) & 0x1) << 8)
1733
+
#define BFM_RCC_APB1HLPENR_FDCANEN(v) BM_RCC_APB1HLPENR_FDCANEN
1734
+
#define BF_RCC_APB1HLPENR_FDCANEN_V(e) BF_RCC_APB1HLPENR_FDCANEN(BV_RCC_APB1HLPENR_FDCANEN__##e)
1735
+
#define BFM_RCC_APB1HLPENR_FDCANEN_V(v) BM_RCC_APB1HLPENR_FDCANEN
1736
+
#define BP_RCC_APB1HLPENR_MDIOSEN 5
1737
+
#define BM_RCC_APB1HLPENR_MDIOSEN 0x20
1738
+
#define BF_RCC_APB1HLPENR_MDIOSEN(v) (((v) & 0x1) << 5)
1739
+
#define BFM_RCC_APB1HLPENR_MDIOSEN(v) BM_RCC_APB1HLPENR_MDIOSEN
1740
+
#define BF_RCC_APB1HLPENR_MDIOSEN_V(e) BF_RCC_APB1HLPENR_MDIOSEN(BV_RCC_APB1HLPENR_MDIOSEN__##e)
1741
+
#define BFM_RCC_APB1HLPENR_MDIOSEN_V(v) BM_RCC_APB1HLPENR_MDIOSEN
1742
+
#define BP_RCC_APB1HLPENR_OPAMPEN 4
1743
+
#define BM_RCC_APB1HLPENR_OPAMPEN 0x10
1744
+
#define BF_RCC_APB1HLPENR_OPAMPEN(v) (((v) & 0x1) << 4)
1745
+
#define BFM_RCC_APB1HLPENR_OPAMPEN(v) BM_RCC_APB1HLPENR_OPAMPEN
1746
+
#define BF_RCC_APB1HLPENR_OPAMPEN_V(e) BF_RCC_APB1HLPENR_OPAMPEN(BV_RCC_APB1HLPENR_OPAMPEN__##e)
1747
+
#define BFM_RCC_APB1HLPENR_OPAMPEN_V(v) BM_RCC_APB1HLPENR_OPAMPEN
1748
+
#define BP_RCC_APB1HLPENR_SWPEN 2
1749
+
#define BM_RCC_APB1HLPENR_SWPEN 0x4
1750
+
#define BF_RCC_APB1HLPENR_SWPEN(v) (((v) & 0x1) << 2)
1751
+
#define BFM_RCC_APB1HLPENR_SWPEN(v) BM_RCC_APB1HLPENR_SWPEN
1752
+
#define BF_RCC_APB1HLPENR_SWPEN_V(e) BF_RCC_APB1HLPENR_SWPEN(BV_RCC_APB1HLPENR_SWPEN__##e)
1753
+
#define BFM_RCC_APB1HLPENR_SWPEN_V(v) BM_RCC_APB1HLPENR_SWPEN
1754
+
#define BP_RCC_APB1HLPENR_CRSEN 1
1755
+
#define BM_RCC_APB1HLPENR_CRSEN 0x2
1756
+
#define BF_RCC_APB1HLPENR_CRSEN(v) (((v) & 0x1) << 1)
1757
+
#define BFM_RCC_APB1HLPENR_CRSEN(v) BM_RCC_APB1HLPENR_CRSEN
1758
+
#define BF_RCC_APB1HLPENR_CRSEN_V(e) BF_RCC_APB1HLPENR_CRSEN(BV_RCC_APB1HLPENR_CRSEN__##e)
1759
+
#define BFM_RCC_APB1HLPENR_CRSEN_V(v) BM_RCC_APB1HLPENR_CRSEN
1760
+
1761
+
#define REG_RCC_APB2ENR st_reg(RCC_APB2ENR)
1762
+
#define STA_RCC_APB2ENR (0x58024400 + 0xf0)
1763
+
#define STO_RCC_APB2ENR (0xf0)
1764
+
#define STT_RCC_APB2ENR STIO_32_RW
1765
+
#define STN_RCC_APB2ENR RCC_APB2ENR
1766
+
#define BP_RCC_APB2ENR_HRTIMEN 29
1767
+
#define BM_RCC_APB2ENR_HRTIMEN 0x20000000
1768
+
#define BF_RCC_APB2ENR_HRTIMEN(v) (((v) & 0x1) << 29)
1769
+
#define BFM_RCC_APB2ENR_HRTIMEN(v) BM_RCC_APB2ENR_HRTIMEN
1770
+
#define BF_RCC_APB2ENR_HRTIMEN_V(e) BF_RCC_APB2ENR_HRTIMEN(BV_RCC_APB2ENR_HRTIMEN__##e)
1771
+
#define BFM_RCC_APB2ENR_HRTIMEN_V(v) BM_RCC_APB2ENR_HRTIMEN
1772
+
#define BP_RCC_APB2ENR_DFSDM1EN 28
1773
+
#define BM_RCC_APB2ENR_DFSDM1EN 0x10000000
1774
+
#define BF_RCC_APB2ENR_DFSDM1EN(v) (((v) & 0x1) << 28)
1775
+
#define BFM_RCC_APB2ENR_DFSDM1EN(v) BM_RCC_APB2ENR_DFSDM1EN
1776
+
#define BF_RCC_APB2ENR_DFSDM1EN_V(e) BF_RCC_APB2ENR_DFSDM1EN(BV_RCC_APB2ENR_DFSDM1EN__##e)
1777
+
#define BFM_RCC_APB2ENR_DFSDM1EN_V(v) BM_RCC_APB2ENR_DFSDM1EN
1778
+
#define BP_RCC_APB2ENR_SAI3EN 24
1779
+
#define BM_RCC_APB2ENR_SAI3EN 0x1000000
1780
+
#define BF_RCC_APB2ENR_SAI3EN(v) (((v) & 0x1) << 24)
1781
+
#define BFM_RCC_APB2ENR_SAI3EN(v) BM_RCC_APB2ENR_SAI3EN
1782
+
#define BF_RCC_APB2ENR_SAI3EN_V(e) BF_RCC_APB2ENR_SAI3EN(BV_RCC_APB2ENR_SAI3EN__##e)
1783
+
#define BFM_RCC_APB2ENR_SAI3EN_V(v) BM_RCC_APB2ENR_SAI3EN
1784
+
#define BP_RCC_APB2ENR_SAI2EN 23
1785
+
#define BM_RCC_APB2ENR_SAI2EN 0x800000
1786
+
#define BF_RCC_APB2ENR_SAI2EN(v) (((v) & 0x1) << 23)
1787
+
#define BFM_RCC_APB2ENR_SAI2EN(v) BM_RCC_APB2ENR_SAI2EN
1788
+
#define BF_RCC_APB2ENR_SAI2EN_V(e) BF_RCC_APB2ENR_SAI2EN(BV_RCC_APB2ENR_SAI2EN__##e)
1789
+
#define BFM_RCC_APB2ENR_SAI2EN_V(v) BM_RCC_APB2ENR_SAI2EN
1790
+
#define BP_RCC_APB2ENR_SAI1EN 22
1791
+
#define BM_RCC_APB2ENR_SAI1EN 0x400000
1792
+
#define BF_RCC_APB2ENR_SAI1EN(v) (((v) & 0x1) << 22)
1793
+
#define BFM_RCC_APB2ENR_SAI1EN(v) BM_RCC_APB2ENR_SAI1EN
1794
+
#define BF_RCC_APB2ENR_SAI1EN_V(e) BF_RCC_APB2ENR_SAI1EN(BV_RCC_APB2ENR_SAI1EN__##e)
1795
+
#define BFM_RCC_APB2ENR_SAI1EN_V(v) BM_RCC_APB2ENR_SAI1EN
1796
+
#define BP_RCC_APB2ENR_SPI5EN 20
1797
+
#define BM_RCC_APB2ENR_SPI5EN 0x100000
1798
+
#define BF_RCC_APB2ENR_SPI5EN(v) (((v) & 0x1) << 20)
1799
+
#define BFM_RCC_APB2ENR_SPI5EN(v) BM_RCC_APB2ENR_SPI5EN
1800
+
#define BF_RCC_APB2ENR_SPI5EN_V(e) BF_RCC_APB2ENR_SPI5EN(BV_RCC_APB2ENR_SPI5EN__##e)
1801
+
#define BFM_RCC_APB2ENR_SPI5EN_V(v) BM_RCC_APB2ENR_SPI5EN
1802
+
#define BP_RCC_APB2ENR_TIM17EN 18
1803
+
#define BM_RCC_APB2ENR_TIM17EN 0x40000
1804
+
#define BF_RCC_APB2ENR_TIM17EN(v) (((v) & 0x1) << 18)
1805
+
#define BFM_RCC_APB2ENR_TIM17EN(v) BM_RCC_APB2ENR_TIM17EN
1806
+
#define BF_RCC_APB2ENR_TIM17EN_V(e) BF_RCC_APB2ENR_TIM17EN(BV_RCC_APB2ENR_TIM17EN__##e)
1807
+
#define BFM_RCC_APB2ENR_TIM17EN_V(v) BM_RCC_APB2ENR_TIM17EN
1808
+
#define BP_RCC_APB2ENR_TIM16EN 17
1809
+
#define BM_RCC_APB2ENR_TIM16EN 0x20000
1810
+
#define BF_RCC_APB2ENR_TIM16EN(v) (((v) & 0x1) << 17)
1811
+
#define BFM_RCC_APB2ENR_TIM16EN(v) BM_RCC_APB2ENR_TIM16EN
1812
+
#define BF_RCC_APB2ENR_TIM16EN_V(e) BF_RCC_APB2ENR_TIM16EN(BV_RCC_APB2ENR_TIM16EN__##e)
1813
+
#define BFM_RCC_APB2ENR_TIM16EN_V(v) BM_RCC_APB2ENR_TIM16EN
1814
+
#define BP_RCC_APB2ENR_TIM15EN 16
1815
+
#define BM_RCC_APB2ENR_TIM15EN 0x10000
1816
+
#define BF_RCC_APB2ENR_TIM15EN(v) (((v) & 0x1) << 16)
1817
+
#define BFM_RCC_APB2ENR_TIM15EN(v) BM_RCC_APB2ENR_TIM15EN
1818
+
#define BF_RCC_APB2ENR_TIM15EN_V(e) BF_RCC_APB2ENR_TIM15EN(BV_RCC_APB2ENR_TIM15EN__##e)
1819
+
#define BFM_RCC_APB2ENR_TIM15EN_V(v) BM_RCC_APB2ENR_TIM15EN
1820
+
#define BP_RCC_APB2ENR_SPI4EN 13
1821
+
#define BM_RCC_APB2ENR_SPI4EN 0x2000
1822
+
#define BF_RCC_APB2ENR_SPI4EN(v) (((v) & 0x1) << 13)
1823
+
#define BFM_RCC_APB2ENR_SPI4EN(v) BM_RCC_APB2ENR_SPI4EN
1824
+
#define BF_RCC_APB2ENR_SPI4EN_V(e) BF_RCC_APB2ENR_SPI4EN(BV_RCC_APB2ENR_SPI4EN__##e)
1825
+
#define BFM_RCC_APB2ENR_SPI4EN_V(v) BM_RCC_APB2ENR_SPI4EN
1826
+
#define BP_RCC_APB2ENR_SPI1EN 12
1827
+
#define BM_RCC_APB2ENR_SPI1EN 0x1000
1828
+
#define BF_RCC_APB2ENR_SPI1EN(v) (((v) & 0x1) << 12)
1829
+
#define BFM_RCC_APB2ENR_SPI1EN(v) BM_RCC_APB2ENR_SPI1EN
1830
+
#define BF_RCC_APB2ENR_SPI1EN_V(e) BF_RCC_APB2ENR_SPI1EN(BV_RCC_APB2ENR_SPI1EN__##e)
1831
+
#define BFM_RCC_APB2ENR_SPI1EN_V(v) BM_RCC_APB2ENR_SPI1EN
1832
+
#define BP_RCC_APB2ENR_USART6EN 5
1833
+
#define BM_RCC_APB2ENR_USART6EN 0x20
1834
+
#define BF_RCC_APB2ENR_USART6EN(v) (((v) & 0x1) << 5)
1835
+
#define BFM_RCC_APB2ENR_USART6EN(v) BM_RCC_APB2ENR_USART6EN
1836
+
#define BF_RCC_APB2ENR_USART6EN_V(e) BF_RCC_APB2ENR_USART6EN(BV_RCC_APB2ENR_USART6EN__##e)
1837
+
#define BFM_RCC_APB2ENR_USART6EN_V(v) BM_RCC_APB2ENR_USART6EN
1838
+
#define BP_RCC_APB2ENR_USART1EN 4
1839
+
#define BM_RCC_APB2ENR_USART1EN 0x10
1840
+
#define BF_RCC_APB2ENR_USART1EN(v) (((v) & 0x1) << 4)
1841
+
#define BFM_RCC_APB2ENR_USART1EN(v) BM_RCC_APB2ENR_USART1EN
1842
+
#define BF_RCC_APB2ENR_USART1EN_V(e) BF_RCC_APB2ENR_USART1EN(BV_RCC_APB2ENR_USART1EN__##e)
1843
+
#define BFM_RCC_APB2ENR_USART1EN_V(v) BM_RCC_APB2ENR_USART1EN
1844
+
#define BP_RCC_APB2ENR_TIM8EN 1
1845
+
#define BM_RCC_APB2ENR_TIM8EN 0x2
1846
+
#define BF_RCC_APB2ENR_TIM8EN(v) (((v) & 0x1) << 1)
1847
+
#define BFM_RCC_APB2ENR_TIM8EN(v) BM_RCC_APB2ENR_TIM8EN
1848
+
#define BF_RCC_APB2ENR_TIM8EN_V(e) BF_RCC_APB2ENR_TIM8EN(BV_RCC_APB2ENR_TIM8EN__##e)
1849
+
#define BFM_RCC_APB2ENR_TIM8EN_V(v) BM_RCC_APB2ENR_TIM8EN
1850
+
#define BP_RCC_APB2ENR_TIM1EN 0
1851
+
#define BM_RCC_APB2ENR_TIM1EN 0x1
1852
+
#define BF_RCC_APB2ENR_TIM1EN(v) (((v) & 0x1) << 0)
1853
+
#define BFM_RCC_APB2ENR_TIM1EN(v) BM_RCC_APB2ENR_TIM1EN
1854
+
#define BF_RCC_APB2ENR_TIM1EN_V(e) BF_RCC_APB2ENR_TIM1EN(BV_RCC_APB2ENR_TIM1EN__##e)
1855
+
#define BFM_RCC_APB2ENR_TIM1EN_V(v) BM_RCC_APB2ENR_TIM1EN
1856
+
1857
+
#define REG_RCC_APB2LPENR st_reg(RCC_APB2LPENR)
1858
+
#define STA_RCC_APB2LPENR (0x58024400 + 0x118)
1859
+
#define STO_RCC_APB2LPENR (0x118)
1860
+
#define STT_RCC_APB2LPENR STIO_32_RW
1861
+
#define STN_RCC_APB2LPENR RCC_APB2LPENR
1862
+
#define BP_RCC_APB2LPENR_HRTIMEN 29
1863
+
#define BM_RCC_APB2LPENR_HRTIMEN 0x20000000
1864
+
#define BF_RCC_APB2LPENR_HRTIMEN(v) (((v) & 0x1) << 29)
1865
+
#define BFM_RCC_APB2LPENR_HRTIMEN(v) BM_RCC_APB2LPENR_HRTIMEN
1866
+
#define BF_RCC_APB2LPENR_HRTIMEN_V(e) BF_RCC_APB2LPENR_HRTIMEN(BV_RCC_APB2LPENR_HRTIMEN__##e)
1867
+
#define BFM_RCC_APB2LPENR_HRTIMEN_V(v) BM_RCC_APB2LPENR_HRTIMEN
1868
+
#define BP_RCC_APB2LPENR_DFSDM1EN 28
1869
+
#define BM_RCC_APB2LPENR_DFSDM1EN 0x10000000
1870
+
#define BF_RCC_APB2LPENR_DFSDM1EN(v) (((v) & 0x1) << 28)
1871
+
#define BFM_RCC_APB2LPENR_DFSDM1EN(v) BM_RCC_APB2LPENR_DFSDM1EN
1872
+
#define BF_RCC_APB2LPENR_DFSDM1EN_V(e) BF_RCC_APB2LPENR_DFSDM1EN(BV_RCC_APB2LPENR_DFSDM1EN__##e)
1873
+
#define BFM_RCC_APB2LPENR_DFSDM1EN_V(v) BM_RCC_APB2LPENR_DFSDM1EN
1874
+
#define BP_RCC_APB2LPENR_SAI3EN 24
1875
+
#define BM_RCC_APB2LPENR_SAI3EN 0x1000000
1876
+
#define BF_RCC_APB2LPENR_SAI3EN(v) (((v) & 0x1) << 24)
1877
+
#define BFM_RCC_APB2LPENR_SAI3EN(v) BM_RCC_APB2LPENR_SAI3EN
1878
+
#define BF_RCC_APB2LPENR_SAI3EN_V(e) BF_RCC_APB2LPENR_SAI3EN(BV_RCC_APB2LPENR_SAI3EN__##e)
1879
+
#define BFM_RCC_APB2LPENR_SAI3EN_V(v) BM_RCC_APB2LPENR_SAI3EN
1880
+
#define BP_RCC_APB2LPENR_SAI2EN 23
1881
+
#define BM_RCC_APB2LPENR_SAI2EN 0x800000
1882
+
#define BF_RCC_APB2LPENR_SAI2EN(v) (((v) & 0x1) << 23)
1883
+
#define BFM_RCC_APB2LPENR_SAI2EN(v) BM_RCC_APB2LPENR_SAI2EN
1884
+
#define BF_RCC_APB2LPENR_SAI2EN_V(e) BF_RCC_APB2LPENR_SAI2EN(BV_RCC_APB2LPENR_SAI2EN__##e)
1885
+
#define BFM_RCC_APB2LPENR_SAI2EN_V(v) BM_RCC_APB2LPENR_SAI2EN
1886
+
#define BP_RCC_APB2LPENR_SAI1EN 22
1887
+
#define BM_RCC_APB2LPENR_SAI1EN 0x400000
1888
+
#define BF_RCC_APB2LPENR_SAI1EN(v) (((v) & 0x1) << 22)
1889
+
#define BFM_RCC_APB2LPENR_SAI1EN(v) BM_RCC_APB2LPENR_SAI1EN
1890
+
#define BF_RCC_APB2LPENR_SAI1EN_V(e) BF_RCC_APB2LPENR_SAI1EN(BV_RCC_APB2LPENR_SAI1EN__##e)
1891
+
#define BFM_RCC_APB2LPENR_SAI1EN_V(v) BM_RCC_APB2LPENR_SAI1EN
1892
+
#define BP_RCC_APB2LPENR_SPI5EN 20
1893
+
#define BM_RCC_APB2LPENR_SPI5EN 0x100000
1894
+
#define BF_RCC_APB2LPENR_SPI5EN(v) (((v) & 0x1) << 20)
1895
+
#define BFM_RCC_APB2LPENR_SPI5EN(v) BM_RCC_APB2LPENR_SPI5EN
1896
+
#define BF_RCC_APB2LPENR_SPI5EN_V(e) BF_RCC_APB2LPENR_SPI5EN(BV_RCC_APB2LPENR_SPI5EN__##e)
1897
+
#define BFM_RCC_APB2LPENR_SPI5EN_V(v) BM_RCC_APB2LPENR_SPI5EN
1898
+
#define BP_RCC_APB2LPENR_TIM17EN 18
1899
+
#define BM_RCC_APB2LPENR_TIM17EN 0x40000
1900
+
#define BF_RCC_APB2LPENR_TIM17EN(v) (((v) & 0x1) << 18)
1901
+
#define BFM_RCC_APB2LPENR_TIM17EN(v) BM_RCC_APB2LPENR_TIM17EN
1902
+
#define BF_RCC_APB2LPENR_TIM17EN_V(e) BF_RCC_APB2LPENR_TIM17EN(BV_RCC_APB2LPENR_TIM17EN__##e)
1903
+
#define BFM_RCC_APB2LPENR_TIM17EN_V(v) BM_RCC_APB2LPENR_TIM17EN
1904
+
#define BP_RCC_APB2LPENR_TIM16EN 17
1905
+
#define BM_RCC_APB2LPENR_TIM16EN 0x20000
1906
+
#define BF_RCC_APB2LPENR_TIM16EN(v) (((v) & 0x1) << 17)
1907
+
#define BFM_RCC_APB2LPENR_TIM16EN(v) BM_RCC_APB2LPENR_TIM16EN
1908
+
#define BF_RCC_APB2LPENR_TIM16EN_V(e) BF_RCC_APB2LPENR_TIM16EN(BV_RCC_APB2LPENR_TIM16EN__##e)
1909
+
#define BFM_RCC_APB2LPENR_TIM16EN_V(v) BM_RCC_APB2LPENR_TIM16EN
1910
+
#define BP_RCC_APB2LPENR_TIM15EN 16
1911
+
#define BM_RCC_APB2LPENR_TIM15EN 0x10000
1912
+
#define BF_RCC_APB2LPENR_TIM15EN(v) (((v) & 0x1) << 16)
1913
+
#define BFM_RCC_APB2LPENR_TIM15EN(v) BM_RCC_APB2LPENR_TIM15EN
1914
+
#define BF_RCC_APB2LPENR_TIM15EN_V(e) BF_RCC_APB2LPENR_TIM15EN(BV_RCC_APB2LPENR_TIM15EN__##e)
1915
+
#define BFM_RCC_APB2LPENR_TIM15EN_V(v) BM_RCC_APB2LPENR_TIM15EN
1916
+
#define BP_RCC_APB2LPENR_SPI4EN 13
1917
+
#define BM_RCC_APB2LPENR_SPI4EN 0x2000
1918
+
#define BF_RCC_APB2LPENR_SPI4EN(v) (((v) & 0x1) << 13)
1919
+
#define BFM_RCC_APB2LPENR_SPI4EN(v) BM_RCC_APB2LPENR_SPI4EN
1920
+
#define BF_RCC_APB2LPENR_SPI4EN_V(e) BF_RCC_APB2LPENR_SPI4EN(BV_RCC_APB2LPENR_SPI4EN__##e)
1921
+
#define BFM_RCC_APB2LPENR_SPI4EN_V(v) BM_RCC_APB2LPENR_SPI4EN
1922
+
#define BP_RCC_APB2LPENR_SPI1EN 12
1923
+
#define BM_RCC_APB2LPENR_SPI1EN 0x1000
1924
+
#define BF_RCC_APB2LPENR_SPI1EN(v) (((v) & 0x1) << 12)
1925
+
#define BFM_RCC_APB2LPENR_SPI1EN(v) BM_RCC_APB2LPENR_SPI1EN
1926
+
#define BF_RCC_APB2LPENR_SPI1EN_V(e) BF_RCC_APB2LPENR_SPI1EN(BV_RCC_APB2LPENR_SPI1EN__##e)
1927
+
#define BFM_RCC_APB2LPENR_SPI1EN_V(v) BM_RCC_APB2LPENR_SPI1EN
1928
+
#define BP_RCC_APB2LPENR_USART6EN 5
1929
+
#define BM_RCC_APB2LPENR_USART6EN 0x20
1930
+
#define BF_RCC_APB2LPENR_USART6EN(v) (((v) & 0x1) << 5)
1931
+
#define BFM_RCC_APB2LPENR_USART6EN(v) BM_RCC_APB2LPENR_USART6EN
1932
+
#define BF_RCC_APB2LPENR_USART6EN_V(e) BF_RCC_APB2LPENR_USART6EN(BV_RCC_APB2LPENR_USART6EN__##e)
1933
+
#define BFM_RCC_APB2LPENR_USART6EN_V(v) BM_RCC_APB2LPENR_USART6EN
1934
+
#define BP_RCC_APB2LPENR_USART1EN 4
1935
+
#define BM_RCC_APB2LPENR_USART1EN 0x10
1936
+
#define BF_RCC_APB2LPENR_USART1EN(v) (((v) & 0x1) << 4)
1937
+
#define BFM_RCC_APB2LPENR_USART1EN(v) BM_RCC_APB2LPENR_USART1EN
1938
+
#define BF_RCC_APB2LPENR_USART1EN_V(e) BF_RCC_APB2LPENR_USART1EN(BV_RCC_APB2LPENR_USART1EN__##e)
1939
+
#define BFM_RCC_APB2LPENR_USART1EN_V(v) BM_RCC_APB2LPENR_USART1EN
1940
+
#define BP_RCC_APB2LPENR_TIM8EN 1
1941
+
#define BM_RCC_APB2LPENR_TIM8EN 0x2
1942
+
#define BF_RCC_APB2LPENR_TIM8EN(v) (((v) & 0x1) << 1)
1943
+
#define BFM_RCC_APB2LPENR_TIM8EN(v) BM_RCC_APB2LPENR_TIM8EN
1944
+
#define BF_RCC_APB2LPENR_TIM8EN_V(e) BF_RCC_APB2LPENR_TIM8EN(BV_RCC_APB2LPENR_TIM8EN__##e)
1945
+
#define BFM_RCC_APB2LPENR_TIM8EN_V(v) BM_RCC_APB2LPENR_TIM8EN
1946
+
#define BP_RCC_APB2LPENR_TIM1EN 0
1947
+
#define BM_RCC_APB2LPENR_TIM1EN 0x1
1948
+
#define BF_RCC_APB2LPENR_TIM1EN(v) (((v) & 0x1) << 0)
1949
+
#define BFM_RCC_APB2LPENR_TIM1EN(v) BM_RCC_APB2LPENR_TIM1EN
1950
+
#define BF_RCC_APB2LPENR_TIM1EN_V(e) BF_RCC_APB2LPENR_TIM1EN(BV_RCC_APB2LPENR_TIM1EN__##e)
1951
+
#define BFM_RCC_APB2LPENR_TIM1EN_V(v) BM_RCC_APB2LPENR_TIM1EN
1952
+
1953
+
#define REG_RCC_APB4ENR st_reg(RCC_APB4ENR)
1954
+
#define STA_RCC_APB4ENR (0x58024400 + 0xf4)
1955
+
#define STO_RCC_APB4ENR (0xf4)
1956
+
#define STT_RCC_APB4ENR STIO_32_RW
1957
+
#define STN_RCC_APB4ENR RCC_APB4ENR
1958
+
#define BP_RCC_APB4ENR_SAI4EN 21
1959
+
#define BM_RCC_APB4ENR_SAI4EN 0x200000
1960
+
#define BF_RCC_APB4ENR_SAI4EN(v) (((v) & 0x1) << 21)
1961
+
#define BFM_RCC_APB4ENR_SAI4EN(v) BM_RCC_APB4ENR_SAI4EN
1962
+
#define BF_RCC_APB4ENR_SAI4EN_V(e) BF_RCC_APB4ENR_SAI4EN(BV_RCC_APB4ENR_SAI4EN__##e)
1963
+
#define BFM_RCC_APB4ENR_SAI4EN_V(v) BM_RCC_APB4ENR_SAI4EN
1964
+
#define BP_RCC_APB4ENR_RTCAPBEN 16
1965
+
#define BM_RCC_APB4ENR_RTCAPBEN 0x10000
1966
+
#define BF_RCC_APB4ENR_RTCAPBEN(v) (((v) & 0x1) << 16)
1967
+
#define BFM_RCC_APB4ENR_RTCAPBEN(v) BM_RCC_APB4ENR_RTCAPBEN
1968
+
#define BF_RCC_APB4ENR_RTCAPBEN_V(e) BF_RCC_APB4ENR_RTCAPBEN(BV_RCC_APB4ENR_RTCAPBEN__##e)
1969
+
#define BFM_RCC_APB4ENR_RTCAPBEN_V(v) BM_RCC_APB4ENR_RTCAPBEN
1970
+
#define BP_RCC_APB4ENR_VREFEN 15
1971
+
#define BM_RCC_APB4ENR_VREFEN 0x8000
1972
+
#define BF_RCC_APB4ENR_VREFEN(v) (((v) & 0x1) << 15)
1973
+
#define BFM_RCC_APB4ENR_VREFEN(v) BM_RCC_APB4ENR_VREFEN
1974
+
#define BF_RCC_APB4ENR_VREFEN_V(e) BF_RCC_APB4ENR_VREFEN(BV_RCC_APB4ENR_VREFEN__##e)
1975
+
#define BFM_RCC_APB4ENR_VREFEN_V(v) BM_RCC_APB4ENR_VREFEN
1976
+
#define BP_RCC_APB4ENR_COMP12EN 14
1977
+
#define BM_RCC_APB4ENR_COMP12EN 0x4000
1978
+
#define BF_RCC_APB4ENR_COMP12EN(v) (((v) & 0x1) << 14)
1979
+
#define BFM_RCC_APB4ENR_COMP12EN(v) BM_RCC_APB4ENR_COMP12EN
1980
+
#define BF_RCC_APB4ENR_COMP12EN_V(e) BF_RCC_APB4ENR_COMP12EN(BV_RCC_APB4ENR_COMP12EN__##e)
1981
+
#define BFM_RCC_APB4ENR_COMP12EN_V(v) BM_RCC_APB4ENR_COMP12EN
1982
+
#define BP_RCC_APB4ENR_LPTIM5EN 12
1983
+
#define BM_RCC_APB4ENR_LPTIM5EN 0x1000
1984
+
#define BF_RCC_APB4ENR_LPTIM5EN(v) (((v) & 0x1) << 12)
1985
+
#define BFM_RCC_APB4ENR_LPTIM5EN(v) BM_RCC_APB4ENR_LPTIM5EN
1986
+
#define BF_RCC_APB4ENR_LPTIM5EN_V(e) BF_RCC_APB4ENR_LPTIM5EN(BV_RCC_APB4ENR_LPTIM5EN__##e)
1987
+
#define BFM_RCC_APB4ENR_LPTIM5EN_V(v) BM_RCC_APB4ENR_LPTIM5EN
1988
+
#define BP_RCC_APB4ENR_LPTIM4EN 11
1989
+
#define BM_RCC_APB4ENR_LPTIM4EN 0x800
1990
+
#define BF_RCC_APB4ENR_LPTIM4EN(v) (((v) & 0x1) << 11)
1991
+
#define BFM_RCC_APB4ENR_LPTIM4EN(v) BM_RCC_APB4ENR_LPTIM4EN
1992
+
#define BF_RCC_APB4ENR_LPTIM4EN_V(e) BF_RCC_APB4ENR_LPTIM4EN(BV_RCC_APB4ENR_LPTIM4EN__##e)
1993
+
#define BFM_RCC_APB4ENR_LPTIM4EN_V(v) BM_RCC_APB4ENR_LPTIM4EN
1994
+
#define BP_RCC_APB4ENR_LPTIM3EN 10
1995
+
#define BM_RCC_APB4ENR_LPTIM3EN 0x400
1996
+
#define BF_RCC_APB4ENR_LPTIM3EN(v) (((v) & 0x1) << 10)
1997
+
#define BFM_RCC_APB4ENR_LPTIM3EN(v) BM_RCC_APB4ENR_LPTIM3EN
1998
+
#define BF_RCC_APB4ENR_LPTIM3EN_V(e) BF_RCC_APB4ENR_LPTIM3EN(BV_RCC_APB4ENR_LPTIM3EN__##e)
1999
+
#define BFM_RCC_APB4ENR_LPTIM3EN_V(v) BM_RCC_APB4ENR_LPTIM3EN
2000
+
#define BP_RCC_APB4ENR_LPTIM2EN 9
2001
+
#define BM_RCC_APB4ENR_LPTIM2EN 0x200
2002
+
#define BF_RCC_APB4ENR_LPTIM2EN(v) (((v) & 0x1) << 9)
2003
+
#define BFM_RCC_APB4ENR_LPTIM2EN(v) BM_RCC_APB4ENR_LPTIM2EN
2004
+
#define BF_RCC_APB4ENR_LPTIM2EN_V(e) BF_RCC_APB4ENR_LPTIM2EN(BV_RCC_APB4ENR_LPTIM2EN__##e)
2005
+
#define BFM_RCC_APB4ENR_LPTIM2EN_V(v) BM_RCC_APB4ENR_LPTIM2EN
2006
+
#define BP_RCC_APB4ENR_I2C4EN 7
2007
+
#define BM_RCC_APB4ENR_I2C4EN 0x80
2008
+
#define BF_RCC_APB4ENR_I2C4EN(v) (((v) & 0x1) << 7)
2009
+
#define BFM_RCC_APB4ENR_I2C4EN(v) BM_RCC_APB4ENR_I2C4EN
2010
+
#define BF_RCC_APB4ENR_I2C4EN_V(e) BF_RCC_APB4ENR_I2C4EN(BV_RCC_APB4ENR_I2C4EN__##e)
2011
+
#define BFM_RCC_APB4ENR_I2C4EN_V(v) BM_RCC_APB4ENR_I2C4EN
2012
+
#define BP_RCC_APB4ENR_SPI6EN 5
2013
+
#define BM_RCC_APB4ENR_SPI6EN 0x20
2014
+
#define BF_RCC_APB4ENR_SPI6EN(v) (((v) & 0x1) << 5)
2015
+
#define BFM_RCC_APB4ENR_SPI6EN(v) BM_RCC_APB4ENR_SPI6EN
2016
+
#define BF_RCC_APB4ENR_SPI6EN_V(e) BF_RCC_APB4ENR_SPI6EN(BV_RCC_APB4ENR_SPI6EN__##e)
2017
+
#define BFM_RCC_APB4ENR_SPI6EN_V(v) BM_RCC_APB4ENR_SPI6EN
2018
+
#define BP_RCC_APB4ENR_LPUART1EN 3
2019
+
#define BM_RCC_APB4ENR_LPUART1EN 0x8
2020
+
#define BF_RCC_APB4ENR_LPUART1EN(v) (((v) & 0x1) << 3)
2021
+
#define BFM_RCC_APB4ENR_LPUART1EN(v) BM_RCC_APB4ENR_LPUART1EN
2022
+
#define BF_RCC_APB4ENR_LPUART1EN_V(e) BF_RCC_APB4ENR_LPUART1EN(BV_RCC_APB4ENR_LPUART1EN__##e)
2023
+
#define BFM_RCC_APB4ENR_LPUART1EN_V(v) BM_RCC_APB4ENR_LPUART1EN
2024
+
#define BP_RCC_APB4ENR_SYSCFGEN 1
2025
+
#define BM_RCC_APB4ENR_SYSCFGEN 0x2
2026
+
#define BF_RCC_APB4ENR_SYSCFGEN(v) (((v) & 0x1) << 1)
2027
+
#define BFM_RCC_APB4ENR_SYSCFGEN(v) BM_RCC_APB4ENR_SYSCFGEN
2028
+
#define BF_RCC_APB4ENR_SYSCFGEN_V(e) BF_RCC_APB4ENR_SYSCFGEN(BV_RCC_APB4ENR_SYSCFGEN__##e)
2029
+
#define BFM_RCC_APB4ENR_SYSCFGEN_V(v) BM_RCC_APB4ENR_SYSCFGEN
2030
+
2031
+
#define REG_RCC_APB4LPENR st_reg(RCC_APB4LPENR)
2032
+
#define STA_RCC_APB4LPENR (0x58024400 + 0x11c)
2033
+
#define STO_RCC_APB4LPENR (0x11c)
2034
+
#define STT_RCC_APB4LPENR STIO_32_RW
2035
+
#define STN_RCC_APB4LPENR RCC_APB4LPENR
2036
+
#define BP_RCC_APB4LPENR_SAI4EN 21
2037
+
#define BM_RCC_APB4LPENR_SAI4EN 0x200000
2038
+
#define BF_RCC_APB4LPENR_SAI4EN(v) (((v) & 0x1) << 21)
2039
+
#define BFM_RCC_APB4LPENR_SAI4EN(v) BM_RCC_APB4LPENR_SAI4EN
2040
+
#define BF_RCC_APB4LPENR_SAI4EN_V(e) BF_RCC_APB4LPENR_SAI4EN(BV_RCC_APB4LPENR_SAI4EN__##e)
2041
+
#define BFM_RCC_APB4LPENR_SAI4EN_V(v) BM_RCC_APB4LPENR_SAI4EN
2042
+
#define BP_RCC_APB4LPENR_RTCAPBEN 16
2043
+
#define BM_RCC_APB4LPENR_RTCAPBEN 0x10000
2044
+
#define BF_RCC_APB4LPENR_RTCAPBEN(v) (((v) & 0x1) << 16)
2045
+
#define BFM_RCC_APB4LPENR_RTCAPBEN(v) BM_RCC_APB4LPENR_RTCAPBEN
2046
+
#define BF_RCC_APB4LPENR_RTCAPBEN_V(e) BF_RCC_APB4LPENR_RTCAPBEN(BV_RCC_APB4LPENR_RTCAPBEN__##e)
2047
+
#define BFM_RCC_APB4LPENR_RTCAPBEN_V(v) BM_RCC_APB4LPENR_RTCAPBEN
2048
+
#define BP_RCC_APB4LPENR_VREFEN 15
2049
+
#define BM_RCC_APB4LPENR_VREFEN 0x8000
2050
+
#define BF_RCC_APB4LPENR_VREFEN(v) (((v) & 0x1) << 15)
2051
+
#define BFM_RCC_APB4LPENR_VREFEN(v) BM_RCC_APB4LPENR_VREFEN
2052
+
#define BF_RCC_APB4LPENR_VREFEN_V(e) BF_RCC_APB4LPENR_VREFEN(BV_RCC_APB4LPENR_VREFEN__##e)
2053
+
#define BFM_RCC_APB4LPENR_VREFEN_V(v) BM_RCC_APB4LPENR_VREFEN
2054
+
#define BP_RCC_APB4LPENR_COMP12EN 14
2055
+
#define BM_RCC_APB4LPENR_COMP12EN 0x4000
2056
+
#define BF_RCC_APB4LPENR_COMP12EN(v) (((v) & 0x1) << 14)
2057
+
#define BFM_RCC_APB4LPENR_COMP12EN(v) BM_RCC_APB4LPENR_COMP12EN
2058
+
#define BF_RCC_APB4LPENR_COMP12EN_V(e) BF_RCC_APB4LPENR_COMP12EN(BV_RCC_APB4LPENR_COMP12EN__##e)
2059
+
#define BFM_RCC_APB4LPENR_COMP12EN_V(v) BM_RCC_APB4LPENR_COMP12EN
2060
+
#define BP_RCC_APB4LPENR_LPTIM5EN 12
2061
+
#define BM_RCC_APB4LPENR_LPTIM5EN 0x1000
2062
+
#define BF_RCC_APB4LPENR_LPTIM5EN(v) (((v) & 0x1) << 12)
2063
+
#define BFM_RCC_APB4LPENR_LPTIM5EN(v) BM_RCC_APB4LPENR_LPTIM5EN
2064
+
#define BF_RCC_APB4LPENR_LPTIM5EN_V(e) BF_RCC_APB4LPENR_LPTIM5EN(BV_RCC_APB4LPENR_LPTIM5EN__##e)
2065
+
#define BFM_RCC_APB4LPENR_LPTIM5EN_V(v) BM_RCC_APB4LPENR_LPTIM5EN
2066
+
#define BP_RCC_APB4LPENR_LPTIM4EN 11
2067
+
#define BM_RCC_APB4LPENR_LPTIM4EN 0x800
2068
+
#define BF_RCC_APB4LPENR_LPTIM4EN(v) (((v) & 0x1) << 11)
2069
+
#define BFM_RCC_APB4LPENR_LPTIM4EN(v) BM_RCC_APB4LPENR_LPTIM4EN
2070
+
#define BF_RCC_APB4LPENR_LPTIM4EN_V(e) BF_RCC_APB4LPENR_LPTIM4EN(BV_RCC_APB4LPENR_LPTIM4EN__##e)
2071
+
#define BFM_RCC_APB4LPENR_LPTIM4EN_V(v) BM_RCC_APB4LPENR_LPTIM4EN
2072
+
#define BP_RCC_APB4LPENR_LPTIM3EN 10
2073
+
#define BM_RCC_APB4LPENR_LPTIM3EN 0x400
2074
+
#define BF_RCC_APB4LPENR_LPTIM3EN(v) (((v) & 0x1) << 10)
2075
+
#define BFM_RCC_APB4LPENR_LPTIM3EN(v) BM_RCC_APB4LPENR_LPTIM3EN
2076
+
#define BF_RCC_APB4LPENR_LPTIM3EN_V(e) BF_RCC_APB4LPENR_LPTIM3EN(BV_RCC_APB4LPENR_LPTIM3EN__##e)
2077
+
#define BFM_RCC_APB4LPENR_LPTIM3EN_V(v) BM_RCC_APB4LPENR_LPTIM3EN
2078
+
#define BP_RCC_APB4LPENR_LPTIM2EN 9
2079
+
#define BM_RCC_APB4LPENR_LPTIM2EN 0x200
2080
+
#define BF_RCC_APB4LPENR_LPTIM2EN(v) (((v) & 0x1) << 9)
2081
+
#define BFM_RCC_APB4LPENR_LPTIM2EN(v) BM_RCC_APB4LPENR_LPTIM2EN
2082
+
#define BF_RCC_APB4LPENR_LPTIM2EN_V(e) BF_RCC_APB4LPENR_LPTIM2EN(BV_RCC_APB4LPENR_LPTIM2EN__##e)
2083
+
#define BFM_RCC_APB4LPENR_LPTIM2EN_V(v) BM_RCC_APB4LPENR_LPTIM2EN
2084
+
#define BP_RCC_APB4LPENR_I2C4EN 7
2085
+
#define BM_RCC_APB4LPENR_I2C4EN 0x80
2086
+
#define BF_RCC_APB4LPENR_I2C4EN(v) (((v) & 0x1) << 7)
2087
+
#define BFM_RCC_APB4LPENR_I2C4EN(v) BM_RCC_APB4LPENR_I2C4EN
2088
+
#define BF_RCC_APB4LPENR_I2C4EN_V(e) BF_RCC_APB4LPENR_I2C4EN(BV_RCC_APB4LPENR_I2C4EN__##e)
2089
+
#define BFM_RCC_APB4LPENR_I2C4EN_V(v) BM_RCC_APB4LPENR_I2C4EN
2090
+
#define BP_RCC_APB4LPENR_SPI6EN 5
2091
+
#define BM_RCC_APB4LPENR_SPI6EN 0x20
2092
+
#define BF_RCC_APB4LPENR_SPI6EN(v) (((v) & 0x1) << 5)
2093
+
#define BFM_RCC_APB4LPENR_SPI6EN(v) BM_RCC_APB4LPENR_SPI6EN
2094
+
#define BF_RCC_APB4LPENR_SPI6EN_V(e) BF_RCC_APB4LPENR_SPI6EN(BV_RCC_APB4LPENR_SPI6EN__##e)
2095
+
#define BFM_RCC_APB4LPENR_SPI6EN_V(v) BM_RCC_APB4LPENR_SPI6EN
2096
+
#define BP_RCC_APB4LPENR_LPUART1EN 3
2097
+
#define BM_RCC_APB4LPENR_LPUART1EN 0x8
2098
+
#define BF_RCC_APB4LPENR_LPUART1EN(v) (((v) & 0x1) << 3)
2099
+
#define BFM_RCC_APB4LPENR_LPUART1EN(v) BM_RCC_APB4LPENR_LPUART1EN
2100
+
#define BF_RCC_APB4LPENR_LPUART1EN_V(e) BF_RCC_APB4LPENR_LPUART1EN(BV_RCC_APB4LPENR_LPUART1EN__##e)
2101
+
#define BFM_RCC_APB4LPENR_LPUART1EN_V(v) BM_RCC_APB4LPENR_LPUART1EN
2102
+
#define BP_RCC_APB4LPENR_SYSCFGEN 1
2103
+
#define BM_RCC_APB4LPENR_SYSCFGEN 0x2
2104
+
#define BF_RCC_APB4LPENR_SYSCFGEN(v) (((v) & 0x1) << 1)
2105
+
#define BFM_RCC_APB4LPENR_SYSCFGEN(v) BM_RCC_APB4LPENR_SYSCFGEN
2106
+
#define BF_RCC_APB4LPENR_SYSCFGEN_V(e) BF_RCC_APB4LPENR_SYSCFGEN(BV_RCC_APB4LPENR_SYSCFGEN__##e)
2107
+
#define BFM_RCC_APB4LPENR_SYSCFGEN_V(v) BM_RCC_APB4LPENR_SYSCFGEN
2108
+
2109
+
#endif /* __HEADERGEN_RCC_H__*/
+561
firmware/target/arm/stm32/stm32h7/rtc.h
+561
firmware/target/arm/stm32/stm32h7/rtc.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
* stm32h743 version: 1.0
11
+
* stm32h743 authors: Aidan MacDonald
12
+
*
13
+
* Copyright (C) 2015 by the authors
14
+
*
15
+
* This program is free software; you can redistribute it and/or
16
+
* modify it under the terms of the GNU General Public License
17
+
* as published by the Free Software Foundation; either version 2
18
+
* of the License, or (at your option) any later version.
19
+
*
20
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21
+
* KIND, either express or implied.
22
+
*
23
+
****************************************************************************/
24
+
#ifndef __HEADERGEN_RTC_H__
25
+
#define __HEADERGEN_RTC_H__
26
+
27
+
#include "macro.h"
28
+
29
+
#define STA_RTC (0x58004000)
30
+
31
+
#define REG_RTC_TR st_reg(RTC_TR)
32
+
#define STA_RTC_TR (0x58004000 + 0x0)
33
+
#define STO_RTC_TR (0x0)
34
+
#define STT_RTC_TR STIO_32_RW
35
+
#define STN_RTC_TR RTC_TR
36
+
#define BP_RTC_TR_HT 20
37
+
#define BM_RTC_TR_HT 0x300000
38
+
#define BF_RTC_TR_HT(v) (((v) & 0x3) << 20)
39
+
#define BFM_RTC_TR_HT(v) BM_RTC_TR_HT
40
+
#define BF_RTC_TR_HT_V(e) BF_RTC_TR_HT(BV_RTC_TR_HT__##e)
41
+
#define BFM_RTC_TR_HT_V(v) BM_RTC_TR_HT
42
+
#define BP_RTC_TR_HU 16
43
+
#define BM_RTC_TR_HU 0xf0000
44
+
#define BF_RTC_TR_HU(v) (((v) & 0xf) << 16)
45
+
#define BFM_RTC_TR_HU(v) BM_RTC_TR_HU
46
+
#define BF_RTC_TR_HU_V(e) BF_RTC_TR_HU(BV_RTC_TR_HU__##e)
47
+
#define BFM_RTC_TR_HU_V(v) BM_RTC_TR_HU
48
+
#define BP_RTC_TR_MNT 12
49
+
#define BM_RTC_TR_MNT 0x7000
50
+
#define BF_RTC_TR_MNT(v) (((v) & 0x7) << 12)
51
+
#define BFM_RTC_TR_MNT(v) BM_RTC_TR_MNT
52
+
#define BF_RTC_TR_MNT_V(e) BF_RTC_TR_MNT(BV_RTC_TR_MNT__##e)
53
+
#define BFM_RTC_TR_MNT_V(v) BM_RTC_TR_MNT
54
+
#define BP_RTC_TR_MNU 8
55
+
#define BM_RTC_TR_MNU 0xf00
56
+
#define BF_RTC_TR_MNU(v) (((v) & 0xf) << 8)
57
+
#define BFM_RTC_TR_MNU(v) BM_RTC_TR_MNU
58
+
#define BF_RTC_TR_MNU_V(e) BF_RTC_TR_MNU(BV_RTC_TR_MNU__##e)
59
+
#define BFM_RTC_TR_MNU_V(v) BM_RTC_TR_MNU
60
+
#define BP_RTC_TR_ST 4
61
+
#define BM_RTC_TR_ST 0x70
62
+
#define BF_RTC_TR_ST(v) (((v) & 0x7) << 4)
63
+
#define BFM_RTC_TR_ST(v) BM_RTC_TR_ST
64
+
#define BF_RTC_TR_ST_V(e) BF_RTC_TR_ST(BV_RTC_TR_ST__##e)
65
+
#define BFM_RTC_TR_ST_V(v) BM_RTC_TR_ST
66
+
#define BP_RTC_TR_SU 0
67
+
#define BM_RTC_TR_SU 0xf
68
+
#define BF_RTC_TR_SU(v) (((v) & 0xf) << 0)
69
+
#define BFM_RTC_TR_SU(v) BM_RTC_TR_SU
70
+
#define BF_RTC_TR_SU_V(e) BF_RTC_TR_SU(BV_RTC_TR_SU__##e)
71
+
#define BFM_RTC_TR_SU_V(v) BM_RTC_TR_SU
72
+
#define BP_RTC_TR_PM 22
73
+
#define BM_RTC_TR_PM 0x400000
74
+
#define BF_RTC_TR_PM(v) (((v) & 0x1) << 22)
75
+
#define BFM_RTC_TR_PM(v) BM_RTC_TR_PM
76
+
#define BF_RTC_TR_PM_V(e) BF_RTC_TR_PM(BV_RTC_TR_PM__##e)
77
+
#define BFM_RTC_TR_PM_V(v) BM_RTC_TR_PM
78
+
79
+
#define REG_RTC_TSTR st_reg(RTC_TSTR)
80
+
#define STA_RTC_TSTR (0x58004000 + 0x30)
81
+
#define STO_RTC_TSTR (0x30)
82
+
#define STT_RTC_TSTR STIO_32_RW
83
+
#define STN_RTC_TSTR RTC_TSTR
84
+
#define BP_RTC_TSTR_HT 20
85
+
#define BM_RTC_TSTR_HT 0x300000
86
+
#define BF_RTC_TSTR_HT(v) (((v) & 0x3) << 20)
87
+
#define BFM_RTC_TSTR_HT(v) BM_RTC_TSTR_HT
88
+
#define BF_RTC_TSTR_HT_V(e) BF_RTC_TSTR_HT(BV_RTC_TSTR_HT__##e)
89
+
#define BFM_RTC_TSTR_HT_V(v) BM_RTC_TSTR_HT
90
+
#define BP_RTC_TSTR_HU 16
91
+
#define BM_RTC_TSTR_HU 0xf0000
92
+
#define BF_RTC_TSTR_HU(v) (((v) & 0xf) << 16)
93
+
#define BFM_RTC_TSTR_HU(v) BM_RTC_TSTR_HU
94
+
#define BF_RTC_TSTR_HU_V(e) BF_RTC_TSTR_HU(BV_RTC_TSTR_HU__##e)
95
+
#define BFM_RTC_TSTR_HU_V(v) BM_RTC_TSTR_HU
96
+
#define BP_RTC_TSTR_MNT 12
97
+
#define BM_RTC_TSTR_MNT 0x7000
98
+
#define BF_RTC_TSTR_MNT(v) (((v) & 0x7) << 12)
99
+
#define BFM_RTC_TSTR_MNT(v) BM_RTC_TSTR_MNT
100
+
#define BF_RTC_TSTR_MNT_V(e) BF_RTC_TSTR_MNT(BV_RTC_TSTR_MNT__##e)
101
+
#define BFM_RTC_TSTR_MNT_V(v) BM_RTC_TSTR_MNT
102
+
#define BP_RTC_TSTR_MNU 8
103
+
#define BM_RTC_TSTR_MNU 0xf00
104
+
#define BF_RTC_TSTR_MNU(v) (((v) & 0xf) << 8)
105
+
#define BFM_RTC_TSTR_MNU(v) BM_RTC_TSTR_MNU
106
+
#define BF_RTC_TSTR_MNU_V(e) BF_RTC_TSTR_MNU(BV_RTC_TSTR_MNU__##e)
107
+
#define BFM_RTC_TSTR_MNU_V(v) BM_RTC_TSTR_MNU
108
+
#define BP_RTC_TSTR_ST 4
109
+
#define BM_RTC_TSTR_ST 0x70
110
+
#define BF_RTC_TSTR_ST(v) (((v) & 0x7) << 4)
111
+
#define BFM_RTC_TSTR_ST(v) BM_RTC_TSTR_ST
112
+
#define BF_RTC_TSTR_ST_V(e) BF_RTC_TSTR_ST(BV_RTC_TSTR_ST__##e)
113
+
#define BFM_RTC_TSTR_ST_V(v) BM_RTC_TSTR_ST
114
+
#define BP_RTC_TSTR_SU 0
115
+
#define BM_RTC_TSTR_SU 0xf
116
+
#define BF_RTC_TSTR_SU(v) (((v) & 0xf) << 0)
117
+
#define BFM_RTC_TSTR_SU(v) BM_RTC_TSTR_SU
118
+
#define BF_RTC_TSTR_SU_V(e) BF_RTC_TSTR_SU(BV_RTC_TSTR_SU__##e)
119
+
#define BFM_RTC_TSTR_SU_V(v) BM_RTC_TSTR_SU
120
+
#define BP_RTC_TSTR_PM 22
121
+
#define BM_RTC_TSTR_PM 0x400000
122
+
#define BF_RTC_TSTR_PM(v) (((v) & 0x1) << 22)
123
+
#define BFM_RTC_TSTR_PM(v) BM_RTC_TSTR_PM
124
+
#define BF_RTC_TSTR_PM_V(e) BF_RTC_TSTR_PM(BV_RTC_TSTR_PM__##e)
125
+
#define BFM_RTC_TSTR_PM_V(v) BM_RTC_TSTR_PM
126
+
127
+
#define REG_RTC_DR st_reg(RTC_DR)
128
+
#define STA_RTC_DR (0x58004000 + 0x4)
129
+
#define STO_RTC_DR (0x4)
130
+
#define STT_RTC_DR STIO_32_RW
131
+
#define STN_RTC_DR RTC_DR
132
+
#define BP_RTC_DR_YT 20
133
+
#define BM_RTC_DR_YT 0xf00000
134
+
#define BF_RTC_DR_YT(v) (((v) & 0xf) << 20)
135
+
#define BFM_RTC_DR_YT(v) BM_RTC_DR_YT
136
+
#define BF_RTC_DR_YT_V(e) BF_RTC_DR_YT(BV_RTC_DR_YT__##e)
137
+
#define BFM_RTC_DR_YT_V(v) BM_RTC_DR_YT
138
+
#define BP_RTC_DR_YU 16
139
+
#define BM_RTC_DR_YU 0xf0000
140
+
#define BF_RTC_DR_YU(v) (((v) & 0xf) << 16)
141
+
#define BFM_RTC_DR_YU(v) BM_RTC_DR_YU
142
+
#define BF_RTC_DR_YU_V(e) BF_RTC_DR_YU(BV_RTC_DR_YU__##e)
143
+
#define BFM_RTC_DR_YU_V(v) BM_RTC_DR_YU
144
+
#define BP_RTC_DR_WDU 13
145
+
#define BM_RTC_DR_WDU 0xe000
146
+
#define BF_RTC_DR_WDU(v) (((v) & 0x7) << 13)
147
+
#define BFM_RTC_DR_WDU(v) BM_RTC_DR_WDU
148
+
#define BF_RTC_DR_WDU_V(e) BF_RTC_DR_WDU(BV_RTC_DR_WDU__##e)
149
+
#define BFM_RTC_DR_WDU_V(v) BM_RTC_DR_WDU
150
+
#define BP_RTC_DR_MU 8
151
+
#define BM_RTC_DR_MU 0xf00
152
+
#define BF_RTC_DR_MU(v) (((v) & 0xf) << 8)
153
+
#define BFM_RTC_DR_MU(v) BM_RTC_DR_MU
154
+
#define BF_RTC_DR_MU_V(e) BF_RTC_DR_MU(BV_RTC_DR_MU__##e)
155
+
#define BFM_RTC_DR_MU_V(v) BM_RTC_DR_MU
156
+
#define BP_RTC_DR_DT 4
157
+
#define BM_RTC_DR_DT 0x30
158
+
#define BF_RTC_DR_DT(v) (((v) & 0x3) << 4)
159
+
#define BFM_RTC_DR_DT(v) BM_RTC_DR_DT
160
+
#define BF_RTC_DR_DT_V(e) BF_RTC_DR_DT(BV_RTC_DR_DT__##e)
161
+
#define BFM_RTC_DR_DT_V(v) BM_RTC_DR_DT
162
+
#define BP_RTC_DR_DU 0
163
+
#define BM_RTC_DR_DU 0xf
164
+
#define BF_RTC_DR_DU(v) (((v) & 0xf) << 0)
165
+
#define BFM_RTC_DR_DU(v) BM_RTC_DR_DU
166
+
#define BF_RTC_DR_DU_V(e) BF_RTC_DR_DU(BV_RTC_DR_DU__##e)
167
+
#define BFM_RTC_DR_DU_V(v) BM_RTC_DR_DU
168
+
#define BP_RTC_DR_MT 12
169
+
#define BM_RTC_DR_MT 0x1000
170
+
#define BF_RTC_DR_MT(v) (((v) & 0x1) << 12)
171
+
#define BFM_RTC_DR_MT(v) BM_RTC_DR_MT
172
+
#define BF_RTC_DR_MT_V(e) BF_RTC_DR_MT(BV_RTC_DR_MT__##e)
173
+
#define BFM_RTC_DR_MT_V(v) BM_RTC_DR_MT
174
+
175
+
#define REG_RTC_DRTR st_reg(RTC_DRTR)
176
+
#define STA_RTC_DRTR (0x58004000 + 0x34)
177
+
#define STO_RTC_DRTR (0x34)
178
+
#define STT_RTC_DRTR STIO_32_RW
179
+
#define STN_RTC_DRTR RTC_DRTR
180
+
#define BP_RTC_DRTR_YT 20
181
+
#define BM_RTC_DRTR_YT 0xf00000
182
+
#define BF_RTC_DRTR_YT(v) (((v) & 0xf) << 20)
183
+
#define BFM_RTC_DRTR_YT(v) BM_RTC_DRTR_YT
184
+
#define BF_RTC_DRTR_YT_V(e) BF_RTC_DRTR_YT(BV_RTC_DRTR_YT__##e)
185
+
#define BFM_RTC_DRTR_YT_V(v) BM_RTC_DRTR_YT
186
+
#define BP_RTC_DRTR_YU 16
187
+
#define BM_RTC_DRTR_YU 0xf0000
188
+
#define BF_RTC_DRTR_YU(v) (((v) & 0xf) << 16)
189
+
#define BFM_RTC_DRTR_YU(v) BM_RTC_DRTR_YU
190
+
#define BF_RTC_DRTR_YU_V(e) BF_RTC_DRTR_YU(BV_RTC_DRTR_YU__##e)
191
+
#define BFM_RTC_DRTR_YU_V(v) BM_RTC_DRTR_YU
192
+
#define BP_RTC_DRTR_WDU 13
193
+
#define BM_RTC_DRTR_WDU 0xe000
194
+
#define BF_RTC_DRTR_WDU(v) (((v) & 0x7) << 13)
195
+
#define BFM_RTC_DRTR_WDU(v) BM_RTC_DRTR_WDU
196
+
#define BF_RTC_DRTR_WDU_V(e) BF_RTC_DRTR_WDU(BV_RTC_DRTR_WDU__##e)
197
+
#define BFM_RTC_DRTR_WDU_V(v) BM_RTC_DRTR_WDU
198
+
#define BP_RTC_DRTR_MU 8
199
+
#define BM_RTC_DRTR_MU 0xf00
200
+
#define BF_RTC_DRTR_MU(v) (((v) & 0xf) << 8)
201
+
#define BFM_RTC_DRTR_MU(v) BM_RTC_DRTR_MU
202
+
#define BF_RTC_DRTR_MU_V(e) BF_RTC_DRTR_MU(BV_RTC_DRTR_MU__##e)
203
+
#define BFM_RTC_DRTR_MU_V(v) BM_RTC_DRTR_MU
204
+
#define BP_RTC_DRTR_DT 4
205
+
#define BM_RTC_DRTR_DT 0x30
206
+
#define BF_RTC_DRTR_DT(v) (((v) & 0x3) << 4)
207
+
#define BFM_RTC_DRTR_DT(v) BM_RTC_DRTR_DT
208
+
#define BF_RTC_DRTR_DT_V(e) BF_RTC_DRTR_DT(BV_RTC_DRTR_DT__##e)
209
+
#define BFM_RTC_DRTR_DT_V(v) BM_RTC_DRTR_DT
210
+
#define BP_RTC_DRTR_DU 0
211
+
#define BM_RTC_DRTR_DU 0xf
212
+
#define BF_RTC_DRTR_DU(v) (((v) & 0xf) << 0)
213
+
#define BFM_RTC_DRTR_DU(v) BM_RTC_DRTR_DU
214
+
#define BF_RTC_DRTR_DU_V(e) BF_RTC_DRTR_DU(BV_RTC_DRTR_DU__##e)
215
+
#define BFM_RTC_DRTR_DU_V(v) BM_RTC_DRTR_DU
216
+
#define BP_RTC_DRTR_MT 12
217
+
#define BM_RTC_DRTR_MT 0x1000
218
+
#define BF_RTC_DRTR_MT(v) (((v) & 0x1) << 12)
219
+
#define BFM_RTC_DRTR_MT(v) BM_RTC_DRTR_MT
220
+
#define BF_RTC_DRTR_MT_V(e) BF_RTC_DRTR_MT(BV_RTC_DRTR_MT__##e)
221
+
#define BFM_RTC_DRTR_MT_V(v) BM_RTC_DRTR_MT
222
+
223
+
#define REG_RTC_CR st_reg(RTC_CR)
224
+
#define STA_RTC_CR (0x58004000 + 0x8)
225
+
#define STO_RTC_CR (0x8)
226
+
#define STT_RTC_CR STIO_32_RW
227
+
#define STN_RTC_CR RTC_CR
228
+
#define BP_RTC_CR_OSEL 21
229
+
#define BM_RTC_CR_OSEL 0x600000
230
+
#define BV_RTC_CR_OSEL__DISABLED 0x0
231
+
#define BV_RTC_CR_OSEL__ALARM_A 0x1
232
+
#define BV_RTC_CR_OSEL__ALARM_B 0x2
233
+
#define BV_RTC_CR_OSEL__WAKEUP 0x3
234
+
#define BF_RTC_CR_OSEL(v) (((v) & 0x3) << 21)
235
+
#define BFM_RTC_CR_OSEL(v) BM_RTC_CR_OSEL
236
+
#define BF_RTC_CR_OSEL_V(e) BF_RTC_CR_OSEL(BV_RTC_CR_OSEL__##e)
237
+
#define BFM_RTC_CR_OSEL_V(v) BM_RTC_CR_OSEL
238
+
#define BP_RTC_CR_ITSE 24
239
+
#define BM_RTC_CR_ITSE 0x1000000
240
+
#define BF_RTC_CR_ITSE(v) (((v) & 0x1) << 24)
241
+
#define BFM_RTC_CR_ITSE(v) BM_RTC_CR_ITSE
242
+
#define BF_RTC_CR_ITSE_V(e) BF_RTC_CR_ITSE(BV_RTC_CR_ITSE__##e)
243
+
#define BFM_RTC_CR_ITSE_V(v) BM_RTC_CR_ITSE
244
+
#define BP_RTC_CR_COE 23
245
+
#define BM_RTC_CR_COE 0x800000
246
+
#define BF_RTC_CR_COE(v) (((v) & 0x1) << 23)
247
+
#define BFM_RTC_CR_COE(v) BM_RTC_CR_COE
248
+
#define BF_RTC_CR_COE_V(e) BF_RTC_CR_COE(BV_RTC_CR_COE__##e)
249
+
#define BFM_RTC_CR_COE_V(v) BM_RTC_CR_COE
250
+
#define BP_RTC_CR_POL 20
251
+
#define BM_RTC_CR_POL 0x100000
252
+
#define BF_RTC_CR_POL(v) (((v) & 0x1) << 20)
253
+
#define BFM_RTC_CR_POL(v) BM_RTC_CR_POL
254
+
#define BF_RTC_CR_POL_V(e) BF_RTC_CR_POL(BV_RTC_CR_POL__##e)
255
+
#define BFM_RTC_CR_POL_V(v) BM_RTC_CR_POL
256
+
#define BP_RTC_CR_COSEL 19
257
+
#define BM_RTC_CR_COSEL 0x80000
258
+
#define BF_RTC_CR_COSEL(v) (((v) & 0x1) << 19)
259
+
#define BFM_RTC_CR_COSEL(v) BM_RTC_CR_COSEL
260
+
#define BF_RTC_CR_COSEL_V(e) BF_RTC_CR_COSEL(BV_RTC_CR_COSEL__##e)
261
+
#define BFM_RTC_CR_COSEL_V(v) BM_RTC_CR_COSEL
262
+
#define BP_RTC_CR_BKP 18
263
+
#define BM_RTC_CR_BKP 0x40000
264
+
#define BF_RTC_CR_BKP(v) (((v) & 0x1) << 18)
265
+
#define BFM_RTC_CR_BKP(v) BM_RTC_CR_BKP
266
+
#define BF_RTC_CR_BKP_V(e) BF_RTC_CR_BKP(BV_RTC_CR_BKP__##e)
267
+
#define BFM_RTC_CR_BKP_V(v) BM_RTC_CR_BKP
268
+
#define BP_RTC_CR_SUB1H 17
269
+
#define BM_RTC_CR_SUB1H 0x20000
270
+
#define BF_RTC_CR_SUB1H(v) (((v) & 0x1) << 17)
271
+
#define BFM_RTC_CR_SUB1H(v) BM_RTC_CR_SUB1H
272
+
#define BF_RTC_CR_SUB1H_V(e) BF_RTC_CR_SUB1H(BV_RTC_CR_SUB1H__##e)
273
+
#define BFM_RTC_CR_SUB1H_V(v) BM_RTC_CR_SUB1H
274
+
#define BP_RTC_CR_ADD1H 16
275
+
#define BM_RTC_CR_ADD1H 0x10000
276
+
#define BF_RTC_CR_ADD1H(v) (((v) & 0x1) << 16)
277
+
#define BFM_RTC_CR_ADD1H(v) BM_RTC_CR_ADD1H
278
+
#define BF_RTC_CR_ADD1H_V(e) BF_RTC_CR_ADD1H(BV_RTC_CR_ADD1H__##e)
279
+
#define BFM_RTC_CR_ADD1H_V(v) BM_RTC_CR_ADD1H
280
+
#define BP_RTC_CR_TSIE 15
281
+
#define BM_RTC_CR_TSIE 0x8000
282
+
#define BF_RTC_CR_TSIE(v) (((v) & 0x1) << 15)
283
+
#define BFM_RTC_CR_TSIE(v) BM_RTC_CR_TSIE
284
+
#define BF_RTC_CR_TSIE_V(e) BF_RTC_CR_TSIE(BV_RTC_CR_TSIE__##e)
285
+
#define BFM_RTC_CR_TSIE_V(v) BM_RTC_CR_TSIE
286
+
#define BP_RTC_CR_WUTIE 14
287
+
#define BM_RTC_CR_WUTIE 0x4000
288
+
#define BF_RTC_CR_WUTIE(v) (((v) & 0x1) << 14)
289
+
#define BFM_RTC_CR_WUTIE(v) BM_RTC_CR_WUTIE
290
+
#define BF_RTC_CR_WUTIE_V(e) BF_RTC_CR_WUTIE(BV_RTC_CR_WUTIE__##e)
291
+
#define BFM_RTC_CR_WUTIE_V(v) BM_RTC_CR_WUTIE
292
+
#define BP_RTC_CR_ALRBIE 13
293
+
#define BM_RTC_CR_ALRBIE 0x2000
294
+
#define BF_RTC_CR_ALRBIE(v) (((v) & 0x1) << 13)
295
+
#define BFM_RTC_CR_ALRBIE(v) BM_RTC_CR_ALRBIE
296
+
#define BF_RTC_CR_ALRBIE_V(e) BF_RTC_CR_ALRBIE(BV_RTC_CR_ALRBIE__##e)
297
+
#define BFM_RTC_CR_ALRBIE_V(v) BM_RTC_CR_ALRBIE
298
+
#define BP_RTC_CR_ALRAIE 12
299
+
#define BM_RTC_CR_ALRAIE 0x1000
300
+
#define BF_RTC_CR_ALRAIE(v) (((v) & 0x1) << 12)
301
+
#define BFM_RTC_CR_ALRAIE(v) BM_RTC_CR_ALRAIE
302
+
#define BF_RTC_CR_ALRAIE_V(e) BF_RTC_CR_ALRAIE(BV_RTC_CR_ALRAIE__##e)
303
+
#define BFM_RTC_CR_ALRAIE_V(v) BM_RTC_CR_ALRAIE
304
+
#define BP_RTC_CR_TSE 11
305
+
#define BM_RTC_CR_TSE 0x800
306
+
#define BF_RTC_CR_TSE(v) (((v) & 0x1) << 11)
307
+
#define BFM_RTC_CR_TSE(v) BM_RTC_CR_TSE
308
+
#define BF_RTC_CR_TSE_V(e) BF_RTC_CR_TSE(BV_RTC_CR_TSE__##e)
309
+
#define BFM_RTC_CR_TSE_V(v) BM_RTC_CR_TSE
310
+
#define BP_RTC_CR_WUTE 10
311
+
#define BM_RTC_CR_WUTE 0x400
312
+
#define BF_RTC_CR_WUTE(v) (((v) & 0x1) << 10)
313
+
#define BFM_RTC_CR_WUTE(v) BM_RTC_CR_WUTE
314
+
#define BF_RTC_CR_WUTE_V(e) BF_RTC_CR_WUTE(BV_RTC_CR_WUTE__##e)
315
+
#define BFM_RTC_CR_WUTE_V(v) BM_RTC_CR_WUTE
316
+
#define BP_RTC_CR_ALRBE 9
317
+
#define BM_RTC_CR_ALRBE 0x200
318
+
#define BF_RTC_CR_ALRBE(v) (((v) & 0x1) << 9)
319
+
#define BFM_RTC_CR_ALRBE(v) BM_RTC_CR_ALRBE
320
+
#define BF_RTC_CR_ALRBE_V(e) BF_RTC_CR_ALRBE(BV_RTC_CR_ALRBE__##e)
321
+
#define BFM_RTC_CR_ALRBE_V(v) BM_RTC_CR_ALRBE
322
+
#define BP_RTC_CR_ALRAE 8
323
+
#define BM_RTC_CR_ALRAE 0x100
324
+
#define BF_RTC_CR_ALRAE(v) (((v) & 0x1) << 8)
325
+
#define BFM_RTC_CR_ALRAE(v) BM_RTC_CR_ALRAE
326
+
#define BF_RTC_CR_ALRAE_V(e) BF_RTC_CR_ALRAE(BV_RTC_CR_ALRAE__##e)
327
+
#define BFM_RTC_CR_ALRAE_V(v) BM_RTC_CR_ALRAE
328
+
#define BP_RTC_CR_FMT 6
329
+
#define BM_RTC_CR_FMT 0x40
330
+
#define BF_RTC_CR_FMT(v) (((v) & 0x1) << 6)
331
+
#define BFM_RTC_CR_FMT(v) BM_RTC_CR_FMT
332
+
#define BF_RTC_CR_FMT_V(e) BF_RTC_CR_FMT(BV_RTC_CR_FMT__##e)
333
+
#define BFM_RTC_CR_FMT_V(v) BM_RTC_CR_FMT
334
+
#define BP_RTC_CR_BYPSHAD 5
335
+
#define BM_RTC_CR_BYPSHAD 0x20
336
+
#define BF_RTC_CR_BYPSHAD(v) (((v) & 0x1) << 5)
337
+
#define BFM_RTC_CR_BYPSHAD(v) BM_RTC_CR_BYPSHAD
338
+
#define BF_RTC_CR_BYPSHAD_V(e) BF_RTC_CR_BYPSHAD(BV_RTC_CR_BYPSHAD__##e)
339
+
#define BFM_RTC_CR_BYPSHAD_V(v) BM_RTC_CR_BYPSHAD
340
+
#define BP_RTC_CR_REFCKON 4
341
+
#define BM_RTC_CR_REFCKON 0x10
342
+
#define BF_RTC_CR_REFCKON(v) (((v) & 0x1) << 4)
343
+
#define BFM_RTC_CR_REFCKON(v) BM_RTC_CR_REFCKON
344
+
#define BF_RTC_CR_REFCKON_V(e) BF_RTC_CR_REFCKON(BV_RTC_CR_REFCKON__##e)
345
+
#define BFM_RTC_CR_REFCKON_V(v) BM_RTC_CR_REFCKON
346
+
#define BP_RTC_CR_TSEDGE 3
347
+
#define BM_RTC_CR_TSEDGE 0x8
348
+
#define BF_RTC_CR_TSEDGE(v) (((v) & 0x1) << 3)
349
+
#define BFM_RTC_CR_TSEDGE(v) BM_RTC_CR_TSEDGE
350
+
#define BF_RTC_CR_TSEDGE_V(e) BF_RTC_CR_TSEDGE(BV_RTC_CR_TSEDGE__##e)
351
+
#define BFM_RTC_CR_TSEDGE_V(v) BM_RTC_CR_TSEDGE
352
+
#define BP_RTC_CR_WUCKSEL 0
353
+
#define BM_RTC_CR_WUCKSEL 0x7
354
+
#define BV_RTC_CR_WUCKSEL__RTC_16 0x0
355
+
#define BV_RTC_CR_WUCKSEL__RTC_8 0x1
356
+
#define BV_RTC_CR_WUCKSEL__RTC_4 0x2
357
+
#define BV_RTC_CR_WUCKSEL__RTC_2 0x3
358
+
#define BV_RTC_CR_WUCKSEL__CK_SPRE 0x4
359
+
#define BV_RTC_CR_WUCKSEL__CK_SPRE_ADDWUT 0x6
360
+
#define BF_RTC_CR_WUCKSEL(v) (((v) & 0x7) << 0)
361
+
#define BFM_RTC_CR_WUCKSEL(v) BM_RTC_CR_WUCKSEL
362
+
#define BF_RTC_CR_WUCKSEL_V(e) BF_RTC_CR_WUCKSEL(BV_RTC_CR_WUCKSEL__##e)
363
+
#define BFM_RTC_CR_WUCKSEL_V(v) BM_RTC_CR_WUCKSEL
364
+
365
+
#define REG_RTC_ISR st_reg(RTC_ISR)
366
+
#define STA_RTC_ISR (0x58004000 + 0xc)
367
+
#define STO_RTC_ISR (0xc)
368
+
#define STT_RTC_ISR STIO_32_RW
369
+
#define STN_RTC_ISR RTC_ISR
370
+
#define BP_RTC_ISR_ITSF 17
371
+
#define BM_RTC_ISR_ITSF 0x20000
372
+
#define BF_RTC_ISR_ITSF(v) (((v) & 0x1) << 17)
373
+
#define BFM_RTC_ISR_ITSF(v) BM_RTC_ISR_ITSF
374
+
#define BF_RTC_ISR_ITSF_V(e) BF_RTC_ISR_ITSF(BV_RTC_ISR_ITSF__##e)
375
+
#define BFM_RTC_ISR_ITSF_V(v) BM_RTC_ISR_ITSF
376
+
#define BP_RTC_ISR_RECALPF 16
377
+
#define BM_RTC_ISR_RECALPF 0x10000
378
+
#define BF_RTC_ISR_RECALPF(v) (((v) & 0x1) << 16)
379
+
#define BFM_RTC_ISR_RECALPF(v) BM_RTC_ISR_RECALPF
380
+
#define BF_RTC_ISR_RECALPF_V(e) BF_RTC_ISR_RECALPF(BV_RTC_ISR_RECALPF__##e)
381
+
#define BFM_RTC_ISR_RECALPF_V(v) BM_RTC_ISR_RECALPF
382
+
#define BP_RTC_ISR_TAMP3F 15
383
+
#define BM_RTC_ISR_TAMP3F 0x8000
384
+
#define BF_RTC_ISR_TAMP3F(v) (((v) & 0x1) << 15)
385
+
#define BFM_RTC_ISR_TAMP3F(v) BM_RTC_ISR_TAMP3F
386
+
#define BF_RTC_ISR_TAMP3F_V(e) BF_RTC_ISR_TAMP3F(BV_RTC_ISR_TAMP3F__##e)
387
+
#define BFM_RTC_ISR_TAMP3F_V(v) BM_RTC_ISR_TAMP3F
388
+
#define BP_RTC_ISR_TAMP2F 14
389
+
#define BM_RTC_ISR_TAMP2F 0x4000
390
+
#define BF_RTC_ISR_TAMP2F(v) (((v) & 0x1) << 14)
391
+
#define BFM_RTC_ISR_TAMP2F(v) BM_RTC_ISR_TAMP2F
392
+
#define BF_RTC_ISR_TAMP2F_V(e) BF_RTC_ISR_TAMP2F(BV_RTC_ISR_TAMP2F__##e)
393
+
#define BFM_RTC_ISR_TAMP2F_V(v) BM_RTC_ISR_TAMP2F
394
+
#define BP_RTC_ISR_TAMP1F 13
395
+
#define BM_RTC_ISR_TAMP1F 0x2000
396
+
#define BF_RTC_ISR_TAMP1F(v) (((v) & 0x1) << 13)
397
+
#define BFM_RTC_ISR_TAMP1F(v) BM_RTC_ISR_TAMP1F
398
+
#define BF_RTC_ISR_TAMP1F_V(e) BF_RTC_ISR_TAMP1F(BV_RTC_ISR_TAMP1F__##e)
399
+
#define BFM_RTC_ISR_TAMP1F_V(v) BM_RTC_ISR_TAMP1F
400
+
#define BP_RTC_ISR_TSOVF 12
401
+
#define BM_RTC_ISR_TSOVF 0x1000
402
+
#define BF_RTC_ISR_TSOVF(v) (((v) & 0x1) << 12)
403
+
#define BFM_RTC_ISR_TSOVF(v) BM_RTC_ISR_TSOVF
404
+
#define BF_RTC_ISR_TSOVF_V(e) BF_RTC_ISR_TSOVF(BV_RTC_ISR_TSOVF__##e)
405
+
#define BFM_RTC_ISR_TSOVF_V(v) BM_RTC_ISR_TSOVF
406
+
#define BP_RTC_ISR_TSF 11
407
+
#define BM_RTC_ISR_TSF 0x800
408
+
#define BF_RTC_ISR_TSF(v) (((v) & 0x1) << 11)
409
+
#define BFM_RTC_ISR_TSF(v) BM_RTC_ISR_TSF
410
+
#define BF_RTC_ISR_TSF_V(e) BF_RTC_ISR_TSF(BV_RTC_ISR_TSF__##e)
411
+
#define BFM_RTC_ISR_TSF_V(v) BM_RTC_ISR_TSF
412
+
#define BP_RTC_ISR_WUTF 10
413
+
#define BM_RTC_ISR_WUTF 0x400
414
+
#define BF_RTC_ISR_WUTF(v) (((v) & 0x1) << 10)
415
+
#define BFM_RTC_ISR_WUTF(v) BM_RTC_ISR_WUTF
416
+
#define BF_RTC_ISR_WUTF_V(e) BF_RTC_ISR_WUTF(BV_RTC_ISR_WUTF__##e)
417
+
#define BFM_RTC_ISR_WUTF_V(v) BM_RTC_ISR_WUTF
418
+
#define BP_RTC_ISR_ALRBF 9
419
+
#define BM_RTC_ISR_ALRBF 0x200
420
+
#define BF_RTC_ISR_ALRBF(v) (((v) & 0x1) << 9)
421
+
#define BFM_RTC_ISR_ALRBF(v) BM_RTC_ISR_ALRBF
422
+
#define BF_RTC_ISR_ALRBF_V(e) BF_RTC_ISR_ALRBF(BV_RTC_ISR_ALRBF__##e)
423
+
#define BFM_RTC_ISR_ALRBF_V(v) BM_RTC_ISR_ALRBF
424
+
#define BP_RTC_ISR_ALRAF 8
425
+
#define BM_RTC_ISR_ALRAF 0x100
426
+
#define BF_RTC_ISR_ALRAF(v) (((v) & 0x1) << 8)
427
+
#define BFM_RTC_ISR_ALRAF(v) BM_RTC_ISR_ALRAF
428
+
#define BF_RTC_ISR_ALRAF_V(e) BF_RTC_ISR_ALRAF(BV_RTC_ISR_ALRAF__##e)
429
+
#define BFM_RTC_ISR_ALRAF_V(v) BM_RTC_ISR_ALRAF
430
+
#define BP_RTC_ISR_INIT 7
431
+
#define BM_RTC_ISR_INIT 0x80
432
+
#define BF_RTC_ISR_INIT(v) (((v) & 0x1) << 7)
433
+
#define BFM_RTC_ISR_INIT(v) BM_RTC_ISR_INIT
434
+
#define BF_RTC_ISR_INIT_V(e) BF_RTC_ISR_INIT(BV_RTC_ISR_INIT__##e)
435
+
#define BFM_RTC_ISR_INIT_V(v) BM_RTC_ISR_INIT
436
+
#define BP_RTC_ISR_INITF 6
437
+
#define BM_RTC_ISR_INITF 0x40
438
+
#define BF_RTC_ISR_INITF(v) (((v) & 0x1) << 6)
439
+
#define BFM_RTC_ISR_INITF(v) BM_RTC_ISR_INITF
440
+
#define BF_RTC_ISR_INITF_V(e) BF_RTC_ISR_INITF(BV_RTC_ISR_INITF__##e)
441
+
#define BFM_RTC_ISR_INITF_V(v) BM_RTC_ISR_INITF
442
+
#define BP_RTC_ISR_RSF 5
443
+
#define BM_RTC_ISR_RSF 0x20
444
+
#define BF_RTC_ISR_RSF(v) (((v) & 0x1) << 5)
445
+
#define BFM_RTC_ISR_RSF(v) BM_RTC_ISR_RSF
446
+
#define BF_RTC_ISR_RSF_V(e) BF_RTC_ISR_RSF(BV_RTC_ISR_RSF__##e)
447
+
#define BFM_RTC_ISR_RSF_V(v) BM_RTC_ISR_RSF
448
+
#define BP_RTC_ISR_INITS 4
449
+
#define BM_RTC_ISR_INITS 0x10
450
+
#define BF_RTC_ISR_INITS(v) (((v) & 0x1) << 4)
451
+
#define BFM_RTC_ISR_INITS(v) BM_RTC_ISR_INITS
452
+
#define BF_RTC_ISR_INITS_V(e) BF_RTC_ISR_INITS(BV_RTC_ISR_INITS__##e)
453
+
#define BFM_RTC_ISR_INITS_V(v) BM_RTC_ISR_INITS
454
+
#define BP_RTC_ISR_SHPF 3
455
+
#define BM_RTC_ISR_SHPF 0x8
456
+
#define BF_RTC_ISR_SHPF(v) (((v) & 0x1) << 3)
457
+
#define BFM_RTC_ISR_SHPF(v) BM_RTC_ISR_SHPF
458
+
#define BF_RTC_ISR_SHPF_V(e) BF_RTC_ISR_SHPF(BV_RTC_ISR_SHPF__##e)
459
+
#define BFM_RTC_ISR_SHPF_V(v) BM_RTC_ISR_SHPF
460
+
#define BP_RTC_ISR_WUTWF 2
461
+
#define BM_RTC_ISR_WUTWF 0x4
462
+
#define BF_RTC_ISR_WUTWF(v) (((v) & 0x1) << 2)
463
+
#define BFM_RTC_ISR_WUTWF(v) BM_RTC_ISR_WUTWF
464
+
#define BF_RTC_ISR_WUTWF_V(e) BF_RTC_ISR_WUTWF(BV_RTC_ISR_WUTWF__##e)
465
+
#define BFM_RTC_ISR_WUTWF_V(v) BM_RTC_ISR_WUTWF
466
+
#define BP_RTC_ISR_ALRBWF 1
467
+
#define BM_RTC_ISR_ALRBWF 0x2
468
+
#define BF_RTC_ISR_ALRBWF(v) (((v) & 0x1) << 1)
469
+
#define BFM_RTC_ISR_ALRBWF(v) BM_RTC_ISR_ALRBWF
470
+
#define BF_RTC_ISR_ALRBWF_V(e) BF_RTC_ISR_ALRBWF(BV_RTC_ISR_ALRBWF__##e)
471
+
#define BFM_RTC_ISR_ALRBWF_V(v) BM_RTC_ISR_ALRBWF
472
+
#define BP_RTC_ISR_ALRAWF 0
473
+
#define BM_RTC_ISR_ALRAWF 0x1
474
+
#define BF_RTC_ISR_ALRAWF(v) (((v) & 0x1) << 0)
475
+
#define BFM_RTC_ISR_ALRAWF(v) BM_RTC_ISR_ALRAWF
476
+
#define BF_RTC_ISR_ALRAWF_V(e) BF_RTC_ISR_ALRAWF(BV_RTC_ISR_ALRAWF__##e)
477
+
#define BFM_RTC_ISR_ALRAWF_V(v) BM_RTC_ISR_ALRAWF
478
+
479
+
#define REG_RTC_PRER st_reg(RTC_PRER)
480
+
#define STA_RTC_PRER (0x58004000 + 0x10)
481
+
#define STO_RTC_PRER (0x10)
482
+
#define STT_RTC_PRER STIO_32_RW
483
+
#define STN_RTC_PRER RTC_PRER
484
+
#define BP_RTC_PRER_PREDIV_A 16
485
+
#define BM_RTC_PRER_PREDIV_A 0x7f0000
486
+
#define BF_RTC_PRER_PREDIV_A(v) (((v) & 0x7f) << 16)
487
+
#define BFM_RTC_PRER_PREDIV_A(v) BM_RTC_PRER_PREDIV_A
488
+
#define BF_RTC_PRER_PREDIV_A_V(e) BF_RTC_PRER_PREDIV_A(BV_RTC_PRER_PREDIV_A__##e)
489
+
#define BFM_RTC_PRER_PREDIV_A_V(v) BM_RTC_PRER_PREDIV_A
490
+
#define BP_RTC_PRER_PREDIV_S 0
491
+
#define BM_RTC_PRER_PREDIV_S 0x7fff
492
+
#define BF_RTC_PRER_PREDIV_S(v) (((v) & 0x7fff) << 0)
493
+
#define BFM_RTC_PRER_PREDIV_S(v) BM_RTC_PRER_PREDIV_S
494
+
#define BF_RTC_PRER_PREDIV_S_V(e) BF_RTC_PRER_PREDIV_S(BV_RTC_PRER_PREDIV_S__##e)
495
+
#define BFM_RTC_PRER_PREDIV_S_V(v) BM_RTC_PRER_PREDIV_S
496
+
497
+
#define REG_RTC_WPR st_reg(RTC_WPR)
498
+
#define STA_RTC_WPR (0x58004000 + 0x24)
499
+
#define STO_RTC_WPR (0x24)
500
+
#define STT_RTC_WPR STIO_32_RW
501
+
#define STN_RTC_WPR RTC_WPR
502
+
#define BP_RTC_WPR_KEY 0
503
+
#define BM_RTC_WPR_KEY 0xff
504
+
#define BV_RTC_WPR_KEY__KEY1 0xca
505
+
#define BV_RTC_WPR_KEY__KEY2 0x53
506
+
#define BF_RTC_WPR_KEY(v) (((v) & 0xff) << 0)
507
+
#define BFM_RTC_WPR_KEY(v) BM_RTC_WPR_KEY
508
+
#define BF_RTC_WPR_KEY_V(e) BF_RTC_WPR_KEY(BV_RTC_WPR_KEY__##e)
509
+
#define BFM_RTC_WPR_KEY_V(v) BM_RTC_WPR_KEY
510
+
511
+
#define REG_RTC_SSR st_reg(RTC_SSR)
512
+
#define STA_RTC_SSR (0x58004000 + 0x28)
513
+
#define STO_RTC_SSR (0x28)
514
+
#define STT_RTC_SSR STIO_32_RW
515
+
#define STN_RTC_SSR RTC_SSR
516
+
#define BP_RTC_SSR_SS 0
517
+
#define BM_RTC_SSR_SS 0xffff
518
+
#define BF_RTC_SSR_SS(v) (((v) & 0xffff) << 0)
519
+
#define BFM_RTC_SSR_SS(v) BM_RTC_SSR_SS
520
+
#define BF_RTC_SSR_SS_V(e) BF_RTC_SSR_SS(BV_RTC_SSR_SS__##e)
521
+
#define BFM_RTC_SSR_SS_V(v) BM_RTC_SSR_SS
522
+
523
+
#define REG_RTC_TSSSR st_reg(RTC_TSSSR)
524
+
#define STA_RTC_TSSSR (0x58004000 + 0x38)
525
+
#define STO_RTC_TSSSR (0x38)
526
+
#define STT_RTC_TSSSR STIO_32_RW
527
+
#define STN_RTC_TSSSR RTC_TSSSR
528
+
#define BP_RTC_TSSSR_SS 0
529
+
#define BM_RTC_TSSSR_SS 0xffff
530
+
#define BF_RTC_TSSSR_SS(v) (((v) & 0xffff) << 0)
531
+
#define BFM_RTC_TSSSR_SS(v) BM_RTC_TSSSR_SS
532
+
#define BF_RTC_TSSSR_SS_V(e) BF_RTC_TSSSR_SS(BV_RTC_TSSSR_SS__##e)
533
+
#define BFM_RTC_TSSSR_SS_V(v) BM_RTC_TSSSR_SS
534
+
535
+
#define REG_RTC_OR st_reg(RTC_OR)
536
+
#define STA_RTC_OR (0x58004000 + 0x4c)
537
+
#define STO_RTC_OR (0x4c)
538
+
#define STT_RTC_OR STIO_32_RW
539
+
#define STN_RTC_OR RTC_OR
540
+
#define BP_RTC_OR_RTC_OUT_RMP 1
541
+
#define BM_RTC_OR_RTC_OUT_RMP 0x2
542
+
#define BF_RTC_OR_RTC_OUT_RMP(v) (((v) & 0x1) << 1)
543
+
#define BFM_RTC_OR_RTC_OUT_RMP(v) BM_RTC_OR_RTC_OUT_RMP
544
+
#define BF_RTC_OR_RTC_OUT_RMP_V(e) BF_RTC_OR_RTC_OUT_RMP(BV_RTC_OR_RTC_OUT_RMP__##e)
545
+
#define BFM_RTC_OR_RTC_OUT_RMP_V(v) BM_RTC_OR_RTC_OUT_RMP
546
+
#define BP_RTC_OR_RTC_ALARM_TYPE 0
547
+
#define BM_RTC_OR_RTC_ALARM_TYPE 0x1
548
+
#define BV_RTC_OR_RTC_ALARM_TYPE__OPEN_DRAIN 0x0
549
+
#define BV_RTC_OR_RTC_ALARM_TYPE__PUSH_PULL 0x1
550
+
#define BF_RTC_OR_RTC_ALARM_TYPE(v) (((v) & 0x1) << 0)
551
+
#define BFM_RTC_OR_RTC_ALARM_TYPE(v) BM_RTC_OR_RTC_ALARM_TYPE
552
+
#define BF_RTC_OR_RTC_ALARM_TYPE_V(e) BF_RTC_OR_RTC_ALARM_TYPE(BV_RTC_OR_RTC_ALARM_TYPE__##e)
553
+
#define BFM_RTC_OR_RTC_ALARM_TYPE_V(v) BM_RTC_OR_RTC_ALARM_TYPE
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+
555
+
#define REG_RTC_BKPR(_n1) st_reg(RTC_BKPR(_n1))
556
+
#define STA_RTC_BKPR(_n1) (0x58004000 + 0x50 + (_n1) * 0x4)
557
+
#define STO_RTC_BKPR(_n1) (0x50 + (_n1) * 0x4)
558
+
#define STT_RTC_BKPR(_n1) STIO_32_RW
559
+
#define STN_RTC_BKPR(_n1) RTC_BKPR
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+
561
+
#endif /* __HEADERGEN_RTC_H__*/
+662
firmware/target/arm/stm32/stm32h7/spi.h
+662
firmware/target/arm/stm32/stm32h7/spi.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
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+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
* stm32h743 version: 1.0
11
+
* stm32h743 authors: Aidan MacDonald
12
+
*
13
+
* Copyright (C) 2015 by the authors
14
+
*
15
+
* This program is free software; you can redistribute it and/or
16
+
* modify it under the terms of the GNU General Public License
17
+
* as published by the Free Software Foundation; either version 2
18
+
* of the License, or (at your option) any later version.
19
+
*
20
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21
+
* KIND, either express or implied.
22
+
*
23
+
****************************************************************************/
24
+
#ifndef __HEADERGEN_SPI_H__
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+
#define __HEADERGEN_SPI_H__
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+
27
+
#include "macro.h"
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+
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+
#define STA_SPI1 (0x40013000)
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+
31
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#define STA_SPI2 (0x40003800)
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+
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+
#define STA_SPI3 (0x40003c00)
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+
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#define STA_SPI4 (0x40013400)
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+
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#define STA_SPI5 (0x40015000)
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+
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#define STA_SPI6 (0x58001400)
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+
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+
#define REG_SPI_CR1 st_reg(SPI_CR1)
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+
#define STO_SPI_CR1 (0x0)
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#define STT_SPI_CR1 STIO_32_RW
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#define STN_SPI_CR1 SPI_CR1
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+
#define BP_SPI_CR1_IO_LOCK 16
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+
#define BM_SPI_CR1_IO_LOCK 0x10000
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+
#define BF_SPI_CR1_IO_LOCK(v) (((v) & 0x1) << 16)
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+
#define BFM_SPI_CR1_IO_LOCK(v) BM_SPI_CR1_IO_LOCK
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#define BF_SPI_CR1_IO_LOCK_V(e) BF_SPI_CR1_IO_LOCK(BV_SPI_CR1_IO_LOCK__##e)
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+
#define BFM_SPI_CR1_IO_LOCK_V(v) BM_SPI_CR1_IO_LOCK
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#define BP_SPI_CR1_TCRCINI 15
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#define BM_SPI_CR1_TCRCINI 0x8000
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#define BF_SPI_CR1_TCRCINI(v) (((v) & 0x1) << 15)
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+
#define BFM_SPI_CR1_TCRCINI(v) BM_SPI_CR1_TCRCINI
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+
#define BF_SPI_CR1_TCRCINI_V(e) BF_SPI_CR1_TCRCINI(BV_SPI_CR1_TCRCINI__##e)
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+
#define BFM_SPI_CR1_TCRCINI_V(v) BM_SPI_CR1_TCRCINI
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+
#define BP_SPI_CR1_RCRCINI 14
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+
#define BM_SPI_CR1_RCRCINI 0x4000
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+
#define BF_SPI_CR1_RCRCINI(v) (((v) & 0x1) << 14)
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+
#define BFM_SPI_CR1_RCRCINI(v) BM_SPI_CR1_RCRCINI
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+
#define BF_SPI_CR1_RCRCINI_V(e) BF_SPI_CR1_RCRCINI(BV_SPI_CR1_RCRCINI__##e)
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+
#define BFM_SPI_CR1_RCRCINI_V(v) BM_SPI_CR1_RCRCINI
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+
#define BP_SPI_CR1_CRC33_17 13
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+
#define BM_SPI_CR1_CRC33_17 0x2000
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+
#define BF_SPI_CR1_CRC33_17(v) (((v) & 0x1) << 13)
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+
#define BFM_SPI_CR1_CRC33_17(v) BM_SPI_CR1_CRC33_17
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+
#define BF_SPI_CR1_CRC33_17_V(e) BF_SPI_CR1_CRC33_17(BV_SPI_CR1_CRC33_17__##e)
68
+
#define BFM_SPI_CR1_CRC33_17_V(v) BM_SPI_CR1_CRC33_17
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#define BP_SPI_CR1_SSI 12
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#define BM_SPI_CR1_SSI 0x1000
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+
#define BF_SPI_CR1_SSI(v) (((v) & 0x1) << 12)
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+
#define BFM_SPI_CR1_SSI(v) BM_SPI_CR1_SSI
73
+
#define BF_SPI_CR1_SSI_V(e) BF_SPI_CR1_SSI(BV_SPI_CR1_SSI__##e)
74
+
#define BFM_SPI_CR1_SSI_V(v) BM_SPI_CR1_SSI
75
+
#define BP_SPI_CR1_HDDIR 11
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#define BM_SPI_CR1_HDDIR 0x800
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#define BF_SPI_CR1_HDDIR(v) (((v) & 0x1) << 11)
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+
#define BFM_SPI_CR1_HDDIR(v) BM_SPI_CR1_HDDIR
79
+
#define BF_SPI_CR1_HDDIR_V(e) BF_SPI_CR1_HDDIR(BV_SPI_CR1_HDDIR__##e)
80
+
#define BFM_SPI_CR1_HDDIR_V(v) BM_SPI_CR1_HDDIR
81
+
#define BP_SPI_CR1_CSUSP 10
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#define BM_SPI_CR1_CSUSP 0x400
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#define BF_SPI_CR1_CSUSP(v) (((v) & 0x1) << 10)
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+
#define BFM_SPI_CR1_CSUSP(v) BM_SPI_CR1_CSUSP
85
+
#define BF_SPI_CR1_CSUSP_V(e) BF_SPI_CR1_CSUSP(BV_SPI_CR1_CSUSP__##e)
86
+
#define BFM_SPI_CR1_CSUSP_V(v) BM_SPI_CR1_CSUSP
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+
#define BP_SPI_CR1_CSTART 9
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#define BM_SPI_CR1_CSTART 0x200
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+
#define BF_SPI_CR1_CSTART(v) (((v) & 0x1) << 9)
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+
#define BFM_SPI_CR1_CSTART(v) BM_SPI_CR1_CSTART
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+
#define BF_SPI_CR1_CSTART_V(e) BF_SPI_CR1_CSTART(BV_SPI_CR1_CSTART__##e)
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+
#define BFM_SPI_CR1_CSTART_V(v) BM_SPI_CR1_CSTART
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+
#define BP_SPI_CR1_MASRX 8
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#define BM_SPI_CR1_MASRX 0x100
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#define BF_SPI_CR1_MASRX(v) (((v) & 0x1) << 8)
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#define BFM_SPI_CR1_MASRX(v) BM_SPI_CR1_MASRX
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+
#define BF_SPI_CR1_MASRX_V(e) BF_SPI_CR1_MASRX(BV_SPI_CR1_MASRX__##e)
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+
#define BFM_SPI_CR1_MASRX_V(v) BM_SPI_CR1_MASRX
99
+
#define BP_SPI_CR1_SPE 0
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#define BM_SPI_CR1_SPE 0x1
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+
#define BF_SPI_CR1_SPE(v) (((v) & 0x1) << 0)
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+
#define BFM_SPI_CR1_SPE(v) BM_SPI_CR1_SPE
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+
#define BF_SPI_CR1_SPE_V(e) BF_SPI_CR1_SPE(BV_SPI_CR1_SPE__##e)
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+
#define BFM_SPI_CR1_SPE_V(v) BM_SPI_CR1_SPE
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+
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#define REG_SPI_CR2 st_reg(SPI_CR2)
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+
#define STO_SPI_CR2 (0x4)
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#define STT_SPI_CR2 STIO_32_RW
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+
#define STN_SPI_CR2 SPI_CR2
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#define BP_SPI_CR2_TSER 16
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+
#define BM_SPI_CR2_TSER 0xffff0000
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#define BF_SPI_CR2_TSER(v) (((v) & 0xffff) << 16)
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+
#define BFM_SPI_CR2_TSER(v) BM_SPI_CR2_TSER
114
+
#define BF_SPI_CR2_TSER_V(e) BF_SPI_CR2_TSER(BV_SPI_CR2_TSER__##e)
115
+
#define BFM_SPI_CR2_TSER_V(v) BM_SPI_CR2_TSER
116
+
#define BP_SPI_CR2_TSIZE 0
117
+
#define BM_SPI_CR2_TSIZE 0xffff
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+
#define BF_SPI_CR2_TSIZE(v) (((v) & 0xffff) << 0)
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+
#define BFM_SPI_CR2_TSIZE(v) BM_SPI_CR2_TSIZE
120
+
#define BF_SPI_CR2_TSIZE_V(e) BF_SPI_CR2_TSIZE(BV_SPI_CR2_TSIZE__##e)
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+
#define BFM_SPI_CR2_TSIZE_V(v) BM_SPI_CR2_TSIZE
122
+
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+
#define REG_SPI_CFG1 st_reg(SPI_CFG1)
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#define STO_SPI_CFG1 (0x8)
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#define STT_SPI_CFG1 STIO_32_RW
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#define STN_SPI_CFG1 SPI_CFG1
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+
#define BP_SPI_CFG1_MBR 28
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#define BM_SPI_CFG1_MBR 0x70000000
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+
#define BF_SPI_CFG1_MBR(v) (((v) & 0x7) << 28)
130
+
#define BFM_SPI_CFG1_MBR(v) BM_SPI_CFG1_MBR
131
+
#define BF_SPI_CFG1_MBR_V(e) BF_SPI_CFG1_MBR(BV_SPI_CFG1_MBR__##e)
132
+
#define BFM_SPI_CFG1_MBR_V(v) BM_SPI_CFG1_MBR
133
+
#define BP_SPI_CFG1_CRCSIZE 16
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#define BM_SPI_CFG1_CRCSIZE 0x1f0000
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+
#define BF_SPI_CFG1_CRCSIZE(v) (((v) & 0x1f) << 16)
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+
#define BFM_SPI_CFG1_CRCSIZE(v) BM_SPI_CFG1_CRCSIZE
137
+
#define BF_SPI_CFG1_CRCSIZE_V(e) BF_SPI_CFG1_CRCSIZE(BV_SPI_CFG1_CRCSIZE__##e)
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+
#define BFM_SPI_CFG1_CRCSIZE_V(v) BM_SPI_CFG1_CRCSIZE
139
+
#define BP_SPI_CFG1_UDRDET 11
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+
#define BM_SPI_CFG1_UDRDET 0x1800
141
+
#define BF_SPI_CFG1_UDRDET(v) (((v) & 0x3) << 11)
142
+
#define BFM_SPI_CFG1_UDRDET(v) BM_SPI_CFG1_UDRDET
143
+
#define BF_SPI_CFG1_UDRDET_V(e) BF_SPI_CFG1_UDRDET(BV_SPI_CFG1_UDRDET__##e)
144
+
#define BFM_SPI_CFG1_UDRDET_V(v) BM_SPI_CFG1_UDRDET
145
+
#define BP_SPI_CFG1_UDRCFG 9
146
+
#define BM_SPI_CFG1_UDRCFG 0x600
147
+
#define BF_SPI_CFG1_UDRCFG(v) (((v) & 0x3) << 9)
148
+
#define BFM_SPI_CFG1_UDRCFG(v) BM_SPI_CFG1_UDRCFG
149
+
#define BF_SPI_CFG1_UDRCFG_V(e) BF_SPI_CFG1_UDRCFG(BV_SPI_CFG1_UDRCFG__##e)
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+
#define BFM_SPI_CFG1_UDRCFG_V(v) BM_SPI_CFG1_UDRCFG
151
+
#define BP_SPI_CFG1_FTHLV 5
152
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#define BM_SPI_CFG1_FTHLV 0x1e0
153
+
#define BF_SPI_CFG1_FTHLV(v) (((v) & 0xf) << 5)
154
+
#define BFM_SPI_CFG1_FTHLV(v) BM_SPI_CFG1_FTHLV
155
+
#define BF_SPI_CFG1_FTHLV_V(e) BF_SPI_CFG1_FTHLV(BV_SPI_CFG1_FTHLV__##e)
156
+
#define BFM_SPI_CFG1_FTHLV_V(v) BM_SPI_CFG1_FTHLV
157
+
#define BP_SPI_CFG1_DSIZE 0
158
+
#define BM_SPI_CFG1_DSIZE 0x1f
159
+
#define BF_SPI_CFG1_DSIZE(v) (((v) & 0x1f) << 0)
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+
#define BFM_SPI_CFG1_DSIZE(v) BM_SPI_CFG1_DSIZE
161
+
#define BF_SPI_CFG1_DSIZE_V(e) BF_SPI_CFG1_DSIZE(BV_SPI_CFG1_DSIZE__##e)
162
+
#define BFM_SPI_CFG1_DSIZE_V(v) BM_SPI_CFG1_DSIZE
163
+
#define BP_SPI_CFG1_CRCEN 22
164
+
#define BM_SPI_CFG1_CRCEN 0x400000
165
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#define BF_SPI_CFG1_CRCEN(v) (((v) & 0x1) << 22)
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+
#define BFM_SPI_CFG1_CRCEN(v) BM_SPI_CFG1_CRCEN
167
+
#define BF_SPI_CFG1_CRCEN_V(e) BF_SPI_CFG1_CRCEN(BV_SPI_CFG1_CRCEN__##e)
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+
#define BFM_SPI_CFG1_CRCEN_V(v) BM_SPI_CFG1_CRCEN
169
+
#define BP_SPI_CFG1_TXDMAEN 15
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#define BM_SPI_CFG1_TXDMAEN 0x8000
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#define BF_SPI_CFG1_TXDMAEN(v) (((v) & 0x1) << 15)
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+
#define BFM_SPI_CFG1_TXDMAEN(v) BM_SPI_CFG1_TXDMAEN
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#define BF_SPI_CFG1_TXDMAEN_V(e) BF_SPI_CFG1_TXDMAEN(BV_SPI_CFG1_TXDMAEN__##e)
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+
#define BFM_SPI_CFG1_TXDMAEN_V(v) BM_SPI_CFG1_TXDMAEN
175
+
#define BP_SPI_CFG1_RXDMAEN 14
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#define BM_SPI_CFG1_RXDMAEN 0x4000
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+
#define BF_SPI_CFG1_RXDMAEN(v) (((v) & 0x1) << 14)
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+
#define BFM_SPI_CFG1_RXDMAEN(v) BM_SPI_CFG1_RXDMAEN
179
+
#define BF_SPI_CFG1_RXDMAEN_V(e) BF_SPI_CFG1_RXDMAEN(BV_SPI_CFG1_RXDMAEN__##e)
180
+
#define BFM_SPI_CFG1_RXDMAEN_V(v) BM_SPI_CFG1_RXDMAEN
181
+
182
+
#define REG_SPI_CFG2 st_reg(SPI_CFG2)
183
+
#define STO_SPI_CFG2 (0xc)
184
+
#define STT_SPI_CFG2 STIO_32_RW
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+
#define STN_SPI_CFG2 SPI_CFG2
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#define BP_SPI_CFG2_SP 19
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#define BM_SPI_CFG2_SP 0x380000
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+
#define BV_SPI_CFG2_SP__MOTOROLA 0x0
189
+
#define BV_SPI_CFG2_SP__TI 0x1
190
+
#define BF_SPI_CFG2_SP(v) (((v) & 0x7) << 19)
191
+
#define BFM_SPI_CFG2_SP(v) BM_SPI_CFG2_SP
192
+
#define BF_SPI_CFG2_SP_V(e) BF_SPI_CFG2_SP(BV_SPI_CFG2_SP__##e)
193
+
#define BFM_SPI_CFG2_SP_V(v) BM_SPI_CFG2_SP
194
+
#define BP_SPI_CFG2_COMM 17
195
+
#define BM_SPI_CFG2_COMM 0x60000
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+
#define BV_SPI_CFG2_COMM__DUPLEX 0x0
197
+
#define BV_SPI_CFG2_COMM__TXONLY 0x1
198
+
#define BV_SPI_CFG2_COMM__RXONLY 0x2
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+
#define BV_SPI_CFG2_COMM__HALF_DUPLEX 0x3
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+
#define BF_SPI_CFG2_COMM(v) (((v) & 0x3) << 17)
201
+
#define BFM_SPI_CFG2_COMM(v) BM_SPI_CFG2_COMM
202
+
#define BF_SPI_CFG2_COMM_V(e) BF_SPI_CFG2_COMM(BV_SPI_CFG2_COMM__##e)
203
+
#define BFM_SPI_CFG2_COMM_V(v) BM_SPI_CFG2_COMM
204
+
#define BP_SPI_CFG2_MIDI 4
205
+
#define BM_SPI_CFG2_MIDI 0xf0
206
+
#define BF_SPI_CFG2_MIDI(v) (((v) & 0xf) << 4)
207
+
#define BFM_SPI_CFG2_MIDI(v) BM_SPI_CFG2_MIDI
208
+
#define BF_SPI_CFG2_MIDI_V(e) BF_SPI_CFG2_MIDI(BV_SPI_CFG2_MIDI__##e)
209
+
#define BFM_SPI_CFG2_MIDI_V(v) BM_SPI_CFG2_MIDI
210
+
#define BP_SPI_CFG2_MSSI 0
211
+
#define BM_SPI_CFG2_MSSI 0xf
212
+
#define BF_SPI_CFG2_MSSI(v) (((v) & 0xf) << 0)
213
+
#define BFM_SPI_CFG2_MSSI(v) BM_SPI_CFG2_MSSI
214
+
#define BF_SPI_CFG2_MSSI_V(e) BF_SPI_CFG2_MSSI(BV_SPI_CFG2_MSSI__##e)
215
+
#define BFM_SPI_CFG2_MSSI_V(v) BM_SPI_CFG2_MSSI
216
+
#define BP_SPI_CFG2_AFCNTR 31
217
+
#define BM_SPI_CFG2_AFCNTR 0x80000000
218
+
#define BF_SPI_CFG2_AFCNTR(v) (((v) & 0x1) << 31)
219
+
#define BFM_SPI_CFG2_AFCNTR(v) BM_SPI_CFG2_AFCNTR
220
+
#define BF_SPI_CFG2_AFCNTR_V(e) BF_SPI_CFG2_AFCNTR(BV_SPI_CFG2_AFCNTR__##e)
221
+
#define BFM_SPI_CFG2_AFCNTR_V(v) BM_SPI_CFG2_AFCNTR
222
+
#define BP_SPI_CFG2_SSOM 30
223
+
#define BM_SPI_CFG2_SSOM 0x40000000
224
+
#define BF_SPI_CFG2_SSOM(v) (((v) & 0x1) << 30)
225
+
#define BFM_SPI_CFG2_SSOM(v) BM_SPI_CFG2_SSOM
226
+
#define BF_SPI_CFG2_SSOM_V(e) BF_SPI_CFG2_SSOM(BV_SPI_CFG2_SSOM__##e)
227
+
#define BFM_SPI_CFG2_SSOM_V(v) BM_SPI_CFG2_SSOM
228
+
#define BP_SPI_CFG2_SSOE 29
229
+
#define BM_SPI_CFG2_SSOE 0x20000000
230
+
#define BF_SPI_CFG2_SSOE(v) (((v) & 0x1) << 29)
231
+
#define BFM_SPI_CFG2_SSOE(v) BM_SPI_CFG2_SSOE
232
+
#define BF_SPI_CFG2_SSOE_V(e) BF_SPI_CFG2_SSOE(BV_SPI_CFG2_SSOE__##e)
233
+
#define BFM_SPI_CFG2_SSOE_V(v) BM_SPI_CFG2_SSOE
234
+
#define BP_SPI_CFG2_SSIOP 28
235
+
#define BM_SPI_CFG2_SSIOP 0x10000000
236
+
#define BF_SPI_CFG2_SSIOP(v) (((v) & 0x1) << 28)
237
+
#define BFM_SPI_CFG2_SSIOP(v) BM_SPI_CFG2_SSIOP
238
+
#define BF_SPI_CFG2_SSIOP_V(e) BF_SPI_CFG2_SSIOP(BV_SPI_CFG2_SSIOP__##e)
239
+
#define BFM_SPI_CFG2_SSIOP_V(v) BM_SPI_CFG2_SSIOP
240
+
#define BP_SPI_CFG2_SSM 26
241
+
#define BM_SPI_CFG2_SSM 0x4000000
242
+
#define BV_SPI_CFG2_SSM__SS_PAD 0x0
243
+
#define BV_SPI_CFG2_SSM__SSI_BIT 0x1
244
+
#define BF_SPI_CFG2_SSM(v) (((v) & 0x1) << 26)
245
+
#define BFM_SPI_CFG2_SSM(v) BM_SPI_CFG2_SSM
246
+
#define BF_SPI_CFG2_SSM_V(e) BF_SPI_CFG2_SSM(BV_SPI_CFG2_SSM__##e)
247
+
#define BFM_SPI_CFG2_SSM_V(v) BM_SPI_CFG2_SSM
248
+
#define BP_SPI_CFG2_CPOL 25
249
+
#define BM_SPI_CFG2_CPOL 0x2000000
250
+
#define BF_SPI_CFG2_CPOL(v) (((v) & 0x1) << 25)
251
+
#define BFM_SPI_CFG2_CPOL(v) BM_SPI_CFG2_CPOL
252
+
#define BF_SPI_CFG2_CPOL_V(e) BF_SPI_CFG2_CPOL(BV_SPI_CFG2_CPOL__##e)
253
+
#define BFM_SPI_CFG2_CPOL_V(v) BM_SPI_CFG2_CPOL
254
+
#define BP_SPI_CFG2_CPHA 24
255
+
#define BM_SPI_CFG2_CPHA 0x1000000
256
+
#define BF_SPI_CFG2_CPHA(v) (((v) & 0x1) << 24)
257
+
#define BFM_SPI_CFG2_CPHA(v) BM_SPI_CFG2_CPHA
258
+
#define BF_SPI_CFG2_CPHA_V(e) BF_SPI_CFG2_CPHA(BV_SPI_CFG2_CPHA__##e)
259
+
#define BFM_SPI_CFG2_CPHA_V(v) BM_SPI_CFG2_CPHA
260
+
#define BP_SPI_CFG2_LSBFIRST 23
261
+
#define BM_SPI_CFG2_LSBFIRST 0x800000
262
+
#define BF_SPI_CFG2_LSBFIRST(v) (((v) & 0x1) << 23)
263
+
#define BFM_SPI_CFG2_LSBFIRST(v) BM_SPI_CFG2_LSBFIRST
264
+
#define BF_SPI_CFG2_LSBFIRST_V(e) BF_SPI_CFG2_LSBFIRST(BV_SPI_CFG2_LSBFIRST__##e)
265
+
#define BFM_SPI_CFG2_LSBFIRST_V(v) BM_SPI_CFG2_LSBFIRST
266
+
#define BP_SPI_CFG2_MASTER 22
267
+
#define BM_SPI_CFG2_MASTER 0x400000
268
+
#define BF_SPI_CFG2_MASTER(v) (((v) & 0x1) << 22)
269
+
#define BFM_SPI_CFG2_MASTER(v) BM_SPI_CFG2_MASTER
270
+
#define BF_SPI_CFG2_MASTER_V(e) BF_SPI_CFG2_MASTER(BV_SPI_CFG2_MASTER__##e)
271
+
#define BFM_SPI_CFG2_MASTER_V(v) BM_SPI_CFG2_MASTER
272
+
#define BP_SPI_CFG2_IOSWP 15
273
+
#define BM_SPI_CFG2_IOSWP 0x8000
274
+
#define BF_SPI_CFG2_IOSWP(v) (((v) & 0x1) << 15)
275
+
#define BFM_SPI_CFG2_IOSWP(v) BM_SPI_CFG2_IOSWP
276
+
#define BF_SPI_CFG2_IOSWP_V(e) BF_SPI_CFG2_IOSWP(BV_SPI_CFG2_IOSWP__##e)
277
+
#define BFM_SPI_CFG2_IOSWP_V(v) BM_SPI_CFG2_IOSWP
278
+
279
+
#define REG_SPI_IER st_reg(SPI_IER)
280
+
#define STO_SPI_IER (0x10)
281
+
#define STT_SPI_IER STIO_32_RW
282
+
#define STN_SPI_IER SPI_IER
283
+
#define BP_SPI_IER_TSERFIE 10
284
+
#define BM_SPI_IER_TSERFIE 0x400
285
+
#define BF_SPI_IER_TSERFIE(v) (((v) & 0x1) << 10)
286
+
#define BFM_SPI_IER_TSERFIE(v) BM_SPI_IER_TSERFIE
287
+
#define BF_SPI_IER_TSERFIE_V(e) BF_SPI_IER_TSERFIE(BV_SPI_IER_TSERFIE__##e)
288
+
#define BFM_SPI_IER_TSERFIE_V(v) BM_SPI_IER_TSERFIE
289
+
#define BP_SPI_IER_MODFIE 9
290
+
#define BM_SPI_IER_MODFIE 0x200
291
+
#define BF_SPI_IER_MODFIE(v) (((v) & 0x1) << 9)
292
+
#define BFM_SPI_IER_MODFIE(v) BM_SPI_IER_MODFIE
293
+
#define BF_SPI_IER_MODFIE_V(e) BF_SPI_IER_MODFIE(BV_SPI_IER_MODFIE__##e)
294
+
#define BFM_SPI_IER_MODFIE_V(v) BM_SPI_IER_MODFIE
295
+
#define BP_SPI_IER_TIFREIE 8
296
+
#define BM_SPI_IER_TIFREIE 0x100
297
+
#define BF_SPI_IER_TIFREIE(v) (((v) & 0x1) << 8)
298
+
#define BFM_SPI_IER_TIFREIE(v) BM_SPI_IER_TIFREIE
299
+
#define BF_SPI_IER_TIFREIE_V(e) BF_SPI_IER_TIFREIE(BV_SPI_IER_TIFREIE__##e)
300
+
#define BFM_SPI_IER_TIFREIE_V(v) BM_SPI_IER_TIFREIE
301
+
#define BP_SPI_IER_CRCEIE 7
302
+
#define BM_SPI_IER_CRCEIE 0x80
303
+
#define BF_SPI_IER_CRCEIE(v) (((v) & 0x1) << 7)
304
+
#define BFM_SPI_IER_CRCEIE(v) BM_SPI_IER_CRCEIE
305
+
#define BF_SPI_IER_CRCEIE_V(e) BF_SPI_IER_CRCEIE(BV_SPI_IER_CRCEIE__##e)
306
+
#define BFM_SPI_IER_CRCEIE_V(v) BM_SPI_IER_CRCEIE
307
+
#define BP_SPI_IER_OVRIE 6
308
+
#define BM_SPI_IER_OVRIE 0x40
309
+
#define BF_SPI_IER_OVRIE(v) (((v) & 0x1) << 6)
310
+
#define BFM_SPI_IER_OVRIE(v) BM_SPI_IER_OVRIE
311
+
#define BF_SPI_IER_OVRIE_V(e) BF_SPI_IER_OVRIE(BV_SPI_IER_OVRIE__##e)
312
+
#define BFM_SPI_IER_OVRIE_V(v) BM_SPI_IER_OVRIE
313
+
#define BP_SPI_IER_UDRIE 5
314
+
#define BM_SPI_IER_UDRIE 0x20
315
+
#define BF_SPI_IER_UDRIE(v) (((v) & 0x1) << 5)
316
+
#define BFM_SPI_IER_UDRIE(v) BM_SPI_IER_UDRIE
317
+
#define BF_SPI_IER_UDRIE_V(e) BF_SPI_IER_UDRIE(BV_SPI_IER_UDRIE__##e)
318
+
#define BFM_SPI_IER_UDRIE_V(v) BM_SPI_IER_UDRIE
319
+
#define BP_SPI_IER_TXTFIE 4
320
+
#define BM_SPI_IER_TXTFIE 0x10
321
+
#define BF_SPI_IER_TXTFIE(v) (((v) & 0x1) << 4)
322
+
#define BFM_SPI_IER_TXTFIE(v) BM_SPI_IER_TXTFIE
323
+
#define BF_SPI_IER_TXTFIE_V(e) BF_SPI_IER_TXTFIE(BV_SPI_IER_TXTFIE__##e)
324
+
#define BFM_SPI_IER_TXTFIE_V(v) BM_SPI_IER_TXTFIE
325
+
#define BP_SPI_IER_EOTIE 3
326
+
#define BM_SPI_IER_EOTIE 0x8
327
+
#define BF_SPI_IER_EOTIE(v) (((v) & 0x1) << 3)
328
+
#define BFM_SPI_IER_EOTIE(v) BM_SPI_IER_EOTIE
329
+
#define BF_SPI_IER_EOTIE_V(e) BF_SPI_IER_EOTIE(BV_SPI_IER_EOTIE__##e)
330
+
#define BFM_SPI_IER_EOTIE_V(v) BM_SPI_IER_EOTIE
331
+
#define BP_SPI_IER_DXPIE 2
332
+
#define BM_SPI_IER_DXPIE 0x4
333
+
#define BF_SPI_IER_DXPIE(v) (((v) & 0x1) << 2)
334
+
#define BFM_SPI_IER_DXPIE(v) BM_SPI_IER_DXPIE
335
+
#define BF_SPI_IER_DXPIE_V(e) BF_SPI_IER_DXPIE(BV_SPI_IER_DXPIE__##e)
336
+
#define BFM_SPI_IER_DXPIE_V(v) BM_SPI_IER_DXPIE
337
+
#define BP_SPI_IER_TXPIE 1
338
+
#define BM_SPI_IER_TXPIE 0x2
339
+
#define BF_SPI_IER_TXPIE(v) (((v) & 0x1) << 1)
340
+
#define BFM_SPI_IER_TXPIE(v) BM_SPI_IER_TXPIE
341
+
#define BF_SPI_IER_TXPIE_V(e) BF_SPI_IER_TXPIE(BV_SPI_IER_TXPIE__##e)
342
+
#define BFM_SPI_IER_TXPIE_V(v) BM_SPI_IER_TXPIE
343
+
#define BP_SPI_IER_RXPIE 0
344
+
#define BM_SPI_IER_RXPIE 0x1
345
+
#define BF_SPI_IER_RXPIE(v) (((v) & 0x1) << 0)
346
+
#define BFM_SPI_IER_RXPIE(v) BM_SPI_IER_RXPIE
347
+
#define BF_SPI_IER_RXPIE_V(e) BF_SPI_IER_RXPIE(BV_SPI_IER_RXPIE__##e)
348
+
#define BFM_SPI_IER_RXPIE_V(v) BM_SPI_IER_RXPIE
349
+
350
+
#define REG_SPI_SR st_reg(SPI_SR)
351
+
#define STO_SPI_SR (0x14)
352
+
#define STT_SPI_SR STIO_32_RW
353
+
#define STN_SPI_SR SPI_SR
354
+
#define BP_SPI_SR_CTSIZE 16
355
+
#define BM_SPI_SR_CTSIZE 0xffff0000
356
+
#define BF_SPI_SR_CTSIZE(v) (((v) & 0xffff) << 16)
357
+
#define BFM_SPI_SR_CTSIZE(v) BM_SPI_SR_CTSIZE
358
+
#define BF_SPI_SR_CTSIZE_V(e) BF_SPI_SR_CTSIZE(BV_SPI_SR_CTSIZE__##e)
359
+
#define BFM_SPI_SR_CTSIZE_V(v) BM_SPI_SR_CTSIZE
360
+
#define BP_SPI_SR_RXPLVL 13
361
+
#define BM_SPI_SR_RXPLVL 0x6000
362
+
#define BF_SPI_SR_RXPLVL(v) (((v) & 0x3) << 13)
363
+
#define BFM_SPI_SR_RXPLVL(v) BM_SPI_SR_RXPLVL
364
+
#define BF_SPI_SR_RXPLVL_V(e) BF_SPI_SR_RXPLVL(BV_SPI_SR_RXPLVL__##e)
365
+
#define BFM_SPI_SR_RXPLVL_V(v) BM_SPI_SR_RXPLVL
366
+
#define BP_SPI_SR_RXWNE 15
367
+
#define BM_SPI_SR_RXWNE 0x8000
368
+
#define BF_SPI_SR_RXWNE(v) (((v) & 0x1) << 15)
369
+
#define BFM_SPI_SR_RXWNE(v) BM_SPI_SR_RXWNE
370
+
#define BF_SPI_SR_RXWNE_V(e) BF_SPI_SR_RXWNE(BV_SPI_SR_RXWNE__##e)
371
+
#define BFM_SPI_SR_RXWNE_V(v) BM_SPI_SR_RXWNE
372
+
#define BP_SPI_SR_TXC 12
373
+
#define BM_SPI_SR_TXC 0x1000
374
+
#define BF_SPI_SR_TXC(v) (((v) & 0x1) << 12)
375
+
#define BFM_SPI_SR_TXC(v) BM_SPI_SR_TXC
376
+
#define BF_SPI_SR_TXC_V(e) BF_SPI_SR_TXC(BV_SPI_SR_TXC__##e)
377
+
#define BFM_SPI_SR_TXC_V(v) BM_SPI_SR_TXC
378
+
#define BP_SPI_SR_SUSP 11
379
+
#define BM_SPI_SR_SUSP 0x800
380
+
#define BF_SPI_SR_SUSP(v) (((v) & 0x1) << 11)
381
+
#define BFM_SPI_SR_SUSP(v) BM_SPI_SR_SUSP
382
+
#define BF_SPI_SR_SUSP_V(e) BF_SPI_SR_SUSP(BV_SPI_SR_SUSP__##e)
383
+
#define BFM_SPI_SR_SUSP_V(v) BM_SPI_SR_SUSP
384
+
#define BP_SPI_SR_TSERF 10
385
+
#define BM_SPI_SR_TSERF 0x400
386
+
#define BF_SPI_SR_TSERF(v) (((v) & 0x1) << 10)
387
+
#define BFM_SPI_SR_TSERF(v) BM_SPI_SR_TSERF
388
+
#define BF_SPI_SR_TSERF_V(e) BF_SPI_SR_TSERF(BV_SPI_SR_TSERF__##e)
389
+
#define BFM_SPI_SR_TSERF_V(v) BM_SPI_SR_TSERF
390
+
#define BP_SPI_SR_MODF 9
391
+
#define BM_SPI_SR_MODF 0x200
392
+
#define BF_SPI_SR_MODF(v) (((v) & 0x1) << 9)
393
+
#define BFM_SPI_SR_MODF(v) BM_SPI_SR_MODF
394
+
#define BF_SPI_SR_MODF_V(e) BF_SPI_SR_MODF(BV_SPI_SR_MODF__##e)
395
+
#define BFM_SPI_SR_MODF_V(v) BM_SPI_SR_MODF
396
+
#define BP_SPI_SR_TIFRE 8
397
+
#define BM_SPI_SR_TIFRE 0x100
398
+
#define BF_SPI_SR_TIFRE(v) (((v) & 0x1) << 8)
399
+
#define BFM_SPI_SR_TIFRE(v) BM_SPI_SR_TIFRE
400
+
#define BF_SPI_SR_TIFRE_V(e) BF_SPI_SR_TIFRE(BV_SPI_SR_TIFRE__##e)
401
+
#define BFM_SPI_SR_TIFRE_V(v) BM_SPI_SR_TIFRE
402
+
#define BP_SPI_SR_CRCE 7
403
+
#define BM_SPI_SR_CRCE 0x80
404
+
#define BF_SPI_SR_CRCE(v) (((v) & 0x1) << 7)
405
+
#define BFM_SPI_SR_CRCE(v) BM_SPI_SR_CRCE
406
+
#define BF_SPI_SR_CRCE_V(e) BF_SPI_SR_CRCE(BV_SPI_SR_CRCE__##e)
407
+
#define BFM_SPI_SR_CRCE_V(v) BM_SPI_SR_CRCE
408
+
#define BP_SPI_SR_OVR 6
409
+
#define BM_SPI_SR_OVR 0x40
410
+
#define BF_SPI_SR_OVR(v) (((v) & 0x1) << 6)
411
+
#define BFM_SPI_SR_OVR(v) BM_SPI_SR_OVR
412
+
#define BF_SPI_SR_OVR_V(e) BF_SPI_SR_OVR(BV_SPI_SR_OVR__##e)
413
+
#define BFM_SPI_SR_OVR_V(v) BM_SPI_SR_OVR
414
+
#define BP_SPI_SR_UDR 5
415
+
#define BM_SPI_SR_UDR 0x20
416
+
#define BF_SPI_SR_UDR(v) (((v) & 0x1) << 5)
417
+
#define BFM_SPI_SR_UDR(v) BM_SPI_SR_UDR
418
+
#define BF_SPI_SR_UDR_V(e) BF_SPI_SR_UDR(BV_SPI_SR_UDR__##e)
419
+
#define BFM_SPI_SR_UDR_V(v) BM_SPI_SR_UDR
420
+
#define BP_SPI_SR_TXTF 4
421
+
#define BM_SPI_SR_TXTF 0x10
422
+
#define BF_SPI_SR_TXTF(v) (((v) & 0x1) << 4)
423
+
#define BFM_SPI_SR_TXTF(v) BM_SPI_SR_TXTF
424
+
#define BF_SPI_SR_TXTF_V(e) BF_SPI_SR_TXTF(BV_SPI_SR_TXTF__##e)
425
+
#define BFM_SPI_SR_TXTF_V(v) BM_SPI_SR_TXTF
426
+
#define BP_SPI_SR_EOT 3
427
+
#define BM_SPI_SR_EOT 0x8
428
+
#define BF_SPI_SR_EOT(v) (((v) & 0x1) << 3)
429
+
#define BFM_SPI_SR_EOT(v) BM_SPI_SR_EOT
430
+
#define BF_SPI_SR_EOT_V(e) BF_SPI_SR_EOT(BV_SPI_SR_EOT__##e)
431
+
#define BFM_SPI_SR_EOT_V(v) BM_SPI_SR_EOT
432
+
#define BP_SPI_SR_DXP 2
433
+
#define BM_SPI_SR_DXP 0x4
434
+
#define BF_SPI_SR_DXP(v) (((v) & 0x1) << 2)
435
+
#define BFM_SPI_SR_DXP(v) BM_SPI_SR_DXP
436
+
#define BF_SPI_SR_DXP_V(e) BF_SPI_SR_DXP(BV_SPI_SR_DXP__##e)
437
+
#define BFM_SPI_SR_DXP_V(v) BM_SPI_SR_DXP
438
+
#define BP_SPI_SR_TXP 1
439
+
#define BM_SPI_SR_TXP 0x2
440
+
#define BF_SPI_SR_TXP(v) (((v) & 0x1) << 1)
441
+
#define BFM_SPI_SR_TXP(v) BM_SPI_SR_TXP
442
+
#define BF_SPI_SR_TXP_V(e) BF_SPI_SR_TXP(BV_SPI_SR_TXP__##e)
443
+
#define BFM_SPI_SR_TXP_V(v) BM_SPI_SR_TXP
444
+
#define BP_SPI_SR_RXP 0
445
+
#define BM_SPI_SR_RXP 0x1
446
+
#define BF_SPI_SR_RXP(v) (((v) & 0x1) << 0)
447
+
#define BFM_SPI_SR_RXP(v) BM_SPI_SR_RXP
448
+
#define BF_SPI_SR_RXP_V(e) BF_SPI_SR_RXP(BV_SPI_SR_RXP__##e)
449
+
#define BFM_SPI_SR_RXP_V(v) BM_SPI_SR_RXP
450
+
451
+
#define REG_SPI_IFCR st_reg(SPI_IFCR)
452
+
#define STO_SPI_IFCR (0x18)
453
+
#define STT_SPI_IFCR STIO_32_RW
454
+
#define STN_SPI_IFCR SPI_IFCR
455
+
#define BP_SPI_IFCR_SUSPC 11
456
+
#define BM_SPI_IFCR_SUSPC 0x800
457
+
#define BF_SPI_IFCR_SUSPC(v) (((v) & 0x1) << 11)
458
+
#define BFM_SPI_IFCR_SUSPC(v) BM_SPI_IFCR_SUSPC
459
+
#define BF_SPI_IFCR_SUSPC_V(e) BF_SPI_IFCR_SUSPC(BV_SPI_IFCR_SUSPC__##e)
460
+
#define BFM_SPI_IFCR_SUSPC_V(v) BM_SPI_IFCR_SUSPC
461
+
#define BP_SPI_IFCR_TSERFC 10
462
+
#define BM_SPI_IFCR_TSERFC 0x400
463
+
#define BF_SPI_IFCR_TSERFC(v) (((v) & 0x1) << 10)
464
+
#define BFM_SPI_IFCR_TSERFC(v) BM_SPI_IFCR_TSERFC
465
+
#define BF_SPI_IFCR_TSERFC_V(e) BF_SPI_IFCR_TSERFC(BV_SPI_IFCR_TSERFC__##e)
466
+
#define BFM_SPI_IFCR_TSERFC_V(v) BM_SPI_IFCR_TSERFC
467
+
#define BP_SPI_IFCR_MODFC 9
468
+
#define BM_SPI_IFCR_MODFC 0x200
469
+
#define BF_SPI_IFCR_MODFC(v) (((v) & 0x1) << 9)
470
+
#define BFM_SPI_IFCR_MODFC(v) BM_SPI_IFCR_MODFC
471
+
#define BF_SPI_IFCR_MODFC_V(e) BF_SPI_IFCR_MODFC(BV_SPI_IFCR_MODFC__##e)
472
+
#define BFM_SPI_IFCR_MODFC_V(v) BM_SPI_IFCR_MODFC
473
+
#define BP_SPI_IFCR_TIFREC 8
474
+
#define BM_SPI_IFCR_TIFREC 0x100
475
+
#define BF_SPI_IFCR_TIFREC(v) (((v) & 0x1) << 8)
476
+
#define BFM_SPI_IFCR_TIFREC(v) BM_SPI_IFCR_TIFREC
477
+
#define BF_SPI_IFCR_TIFREC_V(e) BF_SPI_IFCR_TIFREC(BV_SPI_IFCR_TIFREC__##e)
478
+
#define BFM_SPI_IFCR_TIFREC_V(v) BM_SPI_IFCR_TIFREC
479
+
#define BP_SPI_IFCR_CRCEC 7
480
+
#define BM_SPI_IFCR_CRCEC 0x80
481
+
#define BF_SPI_IFCR_CRCEC(v) (((v) & 0x1) << 7)
482
+
#define BFM_SPI_IFCR_CRCEC(v) BM_SPI_IFCR_CRCEC
483
+
#define BF_SPI_IFCR_CRCEC_V(e) BF_SPI_IFCR_CRCEC(BV_SPI_IFCR_CRCEC__##e)
484
+
#define BFM_SPI_IFCR_CRCEC_V(v) BM_SPI_IFCR_CRCEC
485
+
#define BP_SPI_IFCR_OVRC 6
486
+
#define BM_SPI_IFCR_OVRC 0x40
487
+
#define BF_SPI_IFCR_OVRC(v) (((v) & 0x1) << 6)
488
+
#define BFM_SPI_IFCR_OVRC(v) BM_SPI_IFCR_OVRC
489
+
#define BF_SPI_IFCR_OVRC_V(e) BF_SPI_IFCR_OVRC(BV_SPI_IFCR_OVRC__##e)
490
+
#define BFM_SPI_IFCR_OVRC_V(v) BM_SPI_IFCR_OVRC
491
+
#define BP_SPI_IFCR_UDRC 5
492
+
#define BM_SPI_IFCR_UDRC 0x20
493
+
#define BF_SPI_IFCR_UDRC(v) (((v) & 0x1) << 5)
494
+
#define BFM_SPI_IFCR_UDRC(v) BM_SPI_IFCR_UDRC
495
+
#define BF_SPI_IFCR_UDRC_V(e) BF_SPI_IFCR_UDRC(BV_SPI_IFCR_UDRC__##e)
496
+
#define BFM_SPI_IFCR_UDRC_V(v) BM_SPI_IFCR_UDRC
497
+
#define BP_SPI_IFCR_TXTFC 4
498
+
#define BM_SPI_IFCR_TXTFC 0x10
499
+
#define BF_SPI_IFCR_TXTFC(v) (((v) & 0x1) << 4)
500
+
#define BFM_SPI_IFCR_TXTFC(v) BM_SPI_IFCR_TXTFC
501
+
#define BF_SPI_IFCR_TXTFC_V(e) BF_SPI_IFCR_TXTFC(BV_SPI_IFCR_TXTFC__##e)
502
+
#define BFM_SPI_IFCR_TXTFC_V(v) BM_SPI_IFCR_TXTFC
503
+
#define BP_SPI_IFCR_EOTC 3
504
+
#define BM_SPI_IFCR_EOTC 0x8
505
+
#define BF_SPI_IFCR_EOTC(v) (((v) & 0x1) << 3)
506
+
#define BFM_SPI_IFCR_EOTC(v) BM_SPI_IFCR_EOTC
507
+
#define BF_SPI_IFCR_EOTC_V(e) BF_SPI_IFCR_EOTC(BV_SPI_IFCR_EOTC__##e)
508
+
#define BFM_SPI_IFCR_EOTC_V(v) BM_SPI_IFCR_EOTC
509
+
510
+
#define REG_SPI_TXDR8 st_reg(SPI_TXDR8)
511
+
#define STO_SPI_TXDR8 (0x20)
512
+
#define STT_SPI_TXDR8 STIO_8_RW
513
+
#define STN_SPI_TXDR8 SPI_TXDR8
514
+
515
+
#define REG_SPI_TXDR16 st_reg(SPI_TXDR16)
516
+
#define STO_SPI_TXDR16 (0x20)
517
+
#define STT_SPI_TXDR16 STIO_16_RW
518
+
#define STN_SPI_TXDR16 SPI_TXDR16
519
+
520
+
#define REG_SPI_TXDR32 st_reg(SPI_TXDR32)
521
+
#define STO_SPI_TXDR32 (0x20)
522
+
#define STT_SPI_TXDR32 STIO_32_RW
523
+
#define STN_SPI_TXDR32 SPI_TXDR32
524
+
525
+
#define REG_SPI_RXDR8 st_reg(SPI_RXDR8)
526
+
#define STO_SPI_RXDR8 (0x30)
527
+
#define STT_SPI_RXDR8 STIO_8_RW
528
+
#define STN_SPI_RXDR8 SPI_RXDR8
529
+
530
+
#define REG_SPI_RXDR16 st_reg(SPI_RXDR16)
531
+
#define STO_SPI_RXDR16 (0x30)
532
+
#define STT_SPI_RXDR16 STIO_16_RW
533
+
#define STN_SPI_RXDR16 SPI_RXDR16
534
+
535
+
#define REG_SPI_RXDR32 st_reg(SPI_RXDR32)
536
+
#define STO_SPI_RXDR32 (0x30)
537
+
#define STT_SPI_RXDR32 STIO_32_RW
538
+
#define STN_SPI_RXDR32 SPI_RXDR32
539
+
540
+
#define REG_SPI_CRCPOLY st_reg(SPI_CRCPOLY)
541
+
#define STO_SPI_CRCPOLY (0x40)
542
+
#define STT_SPI_CRCPOLY STIO_32_RW
543
+
#define STN_SPI_CRCPOLY SPI_CRCPOLY
544
+
545
+
#define REG_SPI_TXCRC st_reg(SPI_TXCRC)
546
+
#define STO_SPI_TXCRC (0x44)
547
+
#define STT_SPI_TXCRC STIO_32_RW
548
+
#define STN_SPI_TXCRC SPI_TXCRC
549
+
550
+
#define REG_SPI_RXCRC st_reg(SPI_RXCRC)
551
+
#define STO_SPI_RXCRC (0x48)
552
+
#define STT_SPI_RXCRC STIO_32_RW
553
+
#define STN_SPI_RXCRC SPI_RXCRC
554
+
555
+
#define REG_SPI_UDRDR st_reg(SPI_UDRDR)
556
+
#define STO_SPI_UDRDR (0x4c)
557
+
#define STT_SPI_UDRDR STIO_32_RW
558
+
#define STN_SPI_UDRDR SPI_UDRDR
559
+
560
+
#define REG_SPI_I2SCFGR st_reg(SPI_I2SCFGR)
561
+
#define STO_SPI_I2SCFGR (0x50)
562
+
#define STT_SPI_I2SCFGR STIO_32_RW
563
+
#define STN_SPI_I2SCFGR SPI_I2SCFGR
564
+
#define BP_SPI_I2SCFGR_I2SDIV 16
565
+
#define BM_SPI_I2SCFGR_I2SDIV 0xff0000
566
+
#define BF_SPI_I2SCFGR_I2SDIV(v) (((v) & 0xff) << 16)
567
+
#define BFM_SPI_I2SCFGR_I2SDIV(v) BM_SPI_I2SCFGR_I2SDIV
568
+
#define BF_SPI_I2SCFGR_I2SDIV_V(e) BF_SPI_I2SCFGR_I2SDIV(BV_SPI_I2SCFGR_I2SDIV__##e)
569
+
#define BFM_SPI_I2SCFGR_I2SDIV_V(v) BM_SPI_I2SCFGR_I2SDIV
570
+
#define BP_SPI_I2SCFGR_DATLEN 8
571
+
#define BM_SPI_I2SCFGR_DATLEN 0x300
572
+
#define BV_SPI_I2SCFGR_DATLEN__16BIT 0x0
573
+
#define BV_SPI_I2SCFGR_DATLEN__24BIT 0x1
574
+
#define BV_SPI_I2SCFGR_DATLEN__32BIT 0x2
575
+
#define BF_SPI_I2SCFGR_DATLEN(v) (((v) & 0x3) << 8)
576
+
#define BFM_SPI_I2SCFGR_DATLEN(v) BM_SPI_I2SCFGR_DATLEN
577
+
#define BF_SPI_I2SCFGR_DATLEN_V(e) BF_SPI_I2SCFGR_DATLEN(BV_SPI_I2SCFGR_DATLEN__##e)
578
+
#define BFM_SPI_I2SCFGR_DATLEN_V(v) BM_SPI_I2SCFGR_DATLEN
579
+
#define BP_SPI_I2SCFGR_I2SSTD 4
580
+
#define BM_SPI_I2SCFGR_I2SSTD 0x30
581
+
#define BV_SPI_I2SCFGR_I2SSTD__I2S 0x0
582
+
#define BV_SPI_I2SCFGR_I2SSTD__MSB_JUSTIFIED 0x1
583
+
#define BV_SPI_I2SCFGR_I2SSTD__LSB_JUSTIFIED 0x2
584
+
#define BV_SPI_I2SCFGR_I2SSTD__PCM 0x3
585
+
#define BF_SPI_I2SCFGR_I2SSTD(v) (((v) & 0x3) << 4)
586
+
#define BFM_SPI_I2SCFGR_I2SSTD(v) BM_SPI_I2SCFGR_I2SSTD
587
+
#define BF_SPI_I2SCFGR_I2SSTD_V(e) BF_SPI_I2SCFGR_I2SSTD(BV_SPI_I2SCFGR_I2SSTD__##e)
588
+
#define BFM_SPI_I2SCFGR_I2SSTD_V(v) BM_SPI_I2SCFGR_I2SSTD
589
+
#define BP_SPI_I2SCFGR_I2SCFG 1
590
+
#define BM_SPI_I2SCFGR_I2SCFG 0xe
591
+
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_TX 0x0
592
+
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_RX 0x1
593
+
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_TX 0x2
594
+
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_RX 0x3
595
+
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_DUPLEX 0x4
596
+
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_DUPLEX 0x5
597
+
#define BF_SPI_I2SCFGR_I2SCFG(v) (((v) & 0x7) << 1)
598
+
#define BFM_SPI_I2SCFGR_I2SCFG(v) BM_SPI_I2SCFGR_I2SCFG
599
+
#define BF_SPI_I2SCFGR_I2SCFG_V(e) BF_SPI_I2SCFGR_I2SCFG(BV_SPI_I2SCFGR_I2SCFG__##e)
600
+
#define BFM_SPI_I2SCFGR_I2SCFG_V(v) BM_SPI_I2SCFGR_I2SCFG
601
+
#define BP_SPI_I2SCFGR_MCKOE 25
602
+
#define BM_SPI_I2SCFGR_MCKOE 0x2000000
603
+
#define BF_SPI_I2SCFGR_MCKOE(v) (((v) & 0x1) << 25)
604
+
#define BFM_SPI_I2SCFGR_MCKOE(v) BM_SPI_I2SCFGR_MCKOE
605
+
#define BF_SPI_I2SCFGR_MCKOE_V(e) BF_SPI_I2SCFGR_MCKOE(BV_SPI_I2SCFGR_MCKOE__##e)
606
+
#define BFM_SPI_I2SCFGR_MCKOE_V(v) BM_SPI_I2SCFGR_MCKOE
607
+
#define BP_SPI_I2SCFGR_ODD 24
608
+
#define BM_SPI_I2SCFGR_ODD 0x1000000
609
+
#define BF_SPI_I2SCFGR_ODD(v) (((v) & 0x1) << 24)
610
+
#define BFM_SPI_I2SCFGR_ODD(v) BM_SPI_I2SCFGR_ODD
611
+
#define BF_SPI_I2SCFGR_ODD_V(e) BF_SPI_I2SCFGR_ODD(BV_SPI_I2SCFGR_ODD__##e)
612
+
#define BFM_SPI_I2SCFGR_ODD_V(v) BM_SPI_I2SCFGR_ODD
613
+
#define BP_SPI_I2SCFGR_DATFMT 14
614
+
#define BM_SPI_I2SCFGR_DATFMT 0x4000
615
+
#define BV_SPI_I2SCFGR_DATFMT__RIGHT_ALIGNED 0x0
616
+
#define BV_SPI_I2SCFGR_DATFMT__LEFT_ALIGNED 0x1
617
+
#define BF_SPI_I2SCFGR_DATFMT(v) (((v) & 0x1) << 14)
618
+
#define BFM_SPI_I2SCFGR_DATFMT(v) BM_SPI_I2SCFGR_DATFMT
619
+
#define BF_SPI_I2SCFGR_DATFMT_V(e) BF_SPI_I2SCFGR_DATFMT(BV_SPI_I2SCFGR_DATFMT__##e)
620
+
#define BFM_SPI_I2SCFGR_DATFMT_V(v) BM_SPI_I2SCFGR_DATFMT
621
+
#define BP_SPI_I2SCFGR_WSINV 13
622
+
#define BM_SPI_I2SCFGR_WSINV 0x2000
623
+
#define BF_SPI_I2SCFGR_WSINV(v) (((v) & 0x1) << 13)
624
+
#define BFM_SPI_I2SCFGR_WSINV(v) BM_SPI_I2SCFGR_WSINV
625
+
#define BF_SPI_I2SCFGR_WSINV_V(e) BF_SPI_I2SCFGR_WSINV(BV_SPI_I2SCFGR_WSINV__##e)
626
+
#define BFM_SPI_I2SCFGR_WSINV_V(v) BM_SPI_I2SCFGR_WSINV
627
+
#define BP_SPI_I2SCFGR_FIXCH 12
628
+
#define BM_SPI_I2SCFGR_FIXCH 0x1000
629
+
#define BF_SPI_I2SCFGR_FIXCH(v) (((v) & 0x1) << 12)
630
+
#define BFM_SPI_I2SCFGR_FIXCH(v) BM_SPI_I2SCFGR_FIXCH
631
+
#define BF_SPI_I2SCFGR_FIXCH_V(e) BF_SPI_I2SCFGR_FIXCH(BV_SPI_I2SCFGR_FIXCH__##e)
632
+
#define BFM_SPI_I2SCFGR_FIXCH_V(v) BM_SPI_I2SCFGR_FIXCH
633
+
#define BP_SPI_I2SCFGR_CKPOL 11
634
+
#define BM_SPI_I2SCFGR_CKPOL 0x800
635
+
#define BF_SPI_I2SCFGR_CKPOL(v) (((v) & 0x1) << 11)
636
+
#define BFM_SPI_I2SCFGR_CKPOL(v) BM_SPI_I2SCFGR_CKPOL
637
+
#define BF_SPI_I2SCFGR_CKPOL_V(e) BF_SPI_I2SCFGR_CKPOL(BV_SPI_I2SCFGR_CKPOL__##e)
638
+
#define BFM_SPI_I2SCFGR_CKPOL_V(v) BM_SPI_I2SCFGR_CKPOL
639
+
#define BP_SPI_I2SCFGR_CHLEN 10
640
+
#define BM_SPI_I2SCFGR_CHLEN 0x400
641
+
#define BV_SPI_I2SCFGR_CHLEN__16BIT 0x0
642
+
#define BV_SPI_I2SCFGR_CHLEN__32BIT 0x1
643
+
#define BF_SPI_I2SCFGR_CHLEN(v) (((v) & 0x1) << 10)
644
+
#define BFM_SPI_I2SCFGR_CHLEN(v) BM_SPI_I2SCFGR_CHLEN
645
+
#define BF_SPI_I2SCFGR_CHLEN_V(e) BF_SPI_I2SCFGR_CHLEN(BV_SPI_I2SCFGR_CHLEN__##e)
646
+
#define BFM_SPI_I2SCFGR_CHLEN_V(v) BM_SPI_I2SCFGR_CHLEN
647
+
#define BP_SPI_I2SCFGR_PCMSYNC 7
648
+
#define BM_SPI_I2SCFGR_PCMSYNC 0x80
649
+
#define BV_SPI_I2SCFGR_PCMSYNC__SHORT 0x0
650
+
#define BV_SPI_I2SCFGR_PCMSYNC__LONG 0x1
651
+
#define BF_SPI_I2SCFGR_PCMSYNC(v) (((v) & 0x1) << 7)
652
+
#define BFM_SPI_I2SCFGR_PCMSYNC(v) BM_SPI_I2SCFGR_PCMSYNC
653
+
#define BF_SPI_I2SCFGR_PCMSYNC_V(e) BF_SPI_I2SCFGR_PCMSYNC(BV_SPI_I2SCFGR_PCMSYNC__##e)
654
+
#define BFM_SPI_I2SCFGR_PCMSYNC_V(v) BM_SPI_I2SCFGR_PCMSYNC
655
+
#define BP_SPI_I2SCFGR_I2SMOD 0
656
+
#define BM_SPI_I2SCFGR_I2SMOD 0x1
657
+
#define BF_SPI_I2SCFGR_I2SMOD(v) (((v) & 0x1) << 0)
658
+
#define BFM_SPI_I2SCFGR_I2SMOD(v) BM_SPI_I2SCFGR_I2SMOD
659
+
#define BF_SPI_I2SCFGR_I2SMOD_V(e) BF_SPI_I2SCFGR_I2SMOD(BV_SPI_I2SCFGR_I2SMOD__##e)
660
+
#define BFM_SPI_I2SCFGR_I2SMOD_V(v) BM_SPI_I2SCFGR_I2SMOD
661
+
662
+
#endif /* __HEADERGEN_SPI_H__*/
+43
firmware/target/arm/stm32/stm32h7/syscfg.h
+43
firmware/target/arm/stm32/stm32h7/syscfg.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* This file was automatically generated by headergen, DO NOT EDIT it.
9
+
* headergen version: 3.0.0
10
+
* stm32h743 version: 1.0
11
+
* stm32h743 authors: Aidan MacDonald
12
+
*
13
+
* Copyright (C) 2015 by the authors
14
+
*
15
+
* This program is free software; you can redistribute it and/or
16
+
* modify it under the terms of the GNU General Public License
17
+
* as published by the Free Software Foundation; either version 2
18
+
* of the License, or (at your option) any later version.
19
+
*
20
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
21
+
* KIND, either express or implied.
22
+
*
23
+
****************************************************************************/
24
+
#ifndef __HEADERGEN_SYSCFG_H__
25
+
#define __HEADERGEN_SYSCFG_H__
26
+
27
+
#include "macro.h"
28
+
29
+
#define STA_SYSCFG (0x58000400)
30
+
31
+
#define REG_SYSCFG_PWRCFG st_reg(SYSCFG_PWRCFG)
32
+
#define STA_SYSCFG_PWRCFG (0x58000400 + 0x2c)
33
+
#define STO_SYSCFG_PWRCFG (0x2c)
34
+
#define STT_SYSCFG_PWRCFG STIO_32_RW
35
+
#define STN_SYSCFG_PWRCFG SYSCFG_PWRCFG
36
+
#define BP_SYSCFG_PWRCFG_ODEN 0
37
+
#define BM_SYSCFG_PWRCFG_ODEN 0x1
38
+
#define BF_SYSCFG_PWRCFG_ODEN(v) (((v) & 0x1) << 0)
39
+
#define BFM_SYSCFG_PWRCFG_ODEN(v) BM_SYSCFG_PWRCFG_ODEN
40
+
#define BF_SYSCFG_PWRCFG_ODEN_V(e) BF_SYSCFG_PWRCFG_ODEN(BV_SYSCFG_PWRCFG_ODEN__##e)
41
+
#define BFM_SYSCFG_PWRCFG_ODEN_V(v) BM_SYSCFG_PWRCFG_ODEN
42
+
43
+
#endif /* __HEADERGEN_SYSCFG_H__*/
+685
utils/reggen-ng/stm32h743.reggen
+685
utils/reggen-ng/stm32h743.reggen
···
1
+
name "stm32h743"
2
+
title "STM32H743"
3
+
isa "armv7-m"
4
+
version "1.0"
5
+
author "Aidan MacDonald"
6
+
7
+
node FLASH {
8
+
title "Embedded flash memory"
9
+
addr 0x52002000
10
+
11
+
reg ACR 0x00 {
12
+
fld 5 3 WRHIGHFREQ
13
+
fld 3 0 LATENCY
14
+
}
15
+
}
16
+
17
+
node PWR {
18
+
title "Power control"
19
+
addr 0x58024800
20
+
21
+
reg CR1 0x00 {
22
+
fld 18 17 ALS
23
+
bit 16 AVDEN
24
+
fld 15 14 SVOS
25
+
bit 9 FLPS
26
+
bit 8 DBP
27
+
fld 7 5 PLS
28
+
bit 4 PVDE
29
+
bit 0 LPDS
30
+
}
31
+
32
+
reg CSR1 0x04 {
33
+
bit 16 AVDO
34
+
fld 15 14 ACTVOS
35
+
bit 13 ACTVOSRDY
36
+
bit 4 PVDO
37
+
}
38
+
39
+
reg CR3 0x0c {
40
+
bit 26 USB33RDY
41
+
bit 25 USBREGEN
42
+
bit 24 USB33DEN
43
+
bit 9 VBRS
44
+
bit 8 VBE
45
+
bit 2 SCUEN
46
+
bit 1 LDOEN
47
+
bit 0 BYPASS
48
+
}
49
+
50
+
reg D3CR 0x18 {
51
+
fld 15 14 VOS { enum VOS3 1; enum VOS2 2; enum VOS1 3; }
52
+
bit 13 VOSRDY
53
+
}
54
+
}
55
+
56
+
node RCC {
57
+
title "Reset and clock control"
58
+
addr 0x58024400
59
+
60
+
reg CR 0x00 {
61
+
bit 29 PLL3RDY
62
+
bit 28 PLL3ON
63
+
bit 27 PLL2RDY
64
+
bit 26 PLL2ON
65
+
bit 25 PLL1RDY
66
+
bit 24 PLL1ON
67
+
bit 19 HSECSSON
68
+
bit 18 HSEBYP
69
+
bit 17 HSERDY
70
+
bit 16 HSEON
71
+
bit 15 D2CKRDY
72
+
bit 14 D1CKRDY
73
+
bit 13 HSI48RDY
74
+
bit 12 HSI48ON
75
+
bit 9 CSIKERON
76
+
bit 8 CSIRDY
77
+
bit 7 CSION
78
+
bit 5 HSIDIVF
79
+
fld 4 3 HSIDIV
80
+
bit 2 HSIRDY
81
+
bit 1 HSIKERON
82
+
bit 0 HSION
83
+
}
84
+
85
+
reg CFGR 0x10 {
86
+
fld 31 29 MCO2 { enum SYSCLK 0; enum PLL2P 1; enum HSE 2; enum PLL1P 3; enum CSI 4; enum LSI 5 }
87
+
fld 28 25 MCO2PRE
88
+
fld 24 22 MCO1 { enum HSI 0; enum LSE 1; enum HSE 2; enum PLL1Q 3; enum HSI48 4 }
89
+
fld 21 18 MCO1PRE
90
+
bit 15 TIMPRE
91
+
bit 14 HRTIMSEL
92
+
fld 13 8 RTCPRE
93
+
bit 7 STOPKERWUCK
94
+
bit 6 STOPWUCK
95
+
fld 5 3 SWS
96
+
fld 2 0 SW { enum HSI 0; enum CSI 1; enum HSE 2; enum PLL1P 3; }
97
+
}
98
+
99
+
reg D1CFGR 0x18 {
100
+
fld 11 8 D1CPRE
101
+
fld 6 4 D1PPRE
102
+
fld 4 0 HPRE
103
+
}
104
+
105
+
reg D2CFGR 0x1c {
106
+
fld 10 8 D2PPRE2
107
+
fld 6 4 D2PPRE1
108
+
}
109
+
110
+
reg D3CFGR 0x20 {
111
+
fld 6 4 D3PPRE
112
+
}
113
+
114
+
reg PLLCKSELR 0x28 {
115
+
fld 25 20 DIVM3
116
+
fld 17 12 DIVM2
117
+
fld 9 4 DIVM1
118
+
fld 1 0 PLLSRC { enum HSI 0; enum CSI 1; enum HSE 2; enum NONE 3; }
119
+
}
120
+
121
+
reg PLLCFGR 0x2c {
122
+
bit 24 DIVR3EN
123
+
bit 23 DIVQ3EN
124
+
bit 22 DIVP3EN
125
+
bit 21 DIVR2EN
126
+
bit 20 DIVQ2EN
127
+
bit 19 DIVP2EN
128
+
bit 18 DIVR1EN
129
+
bit 17 DIVQ1EN
130
+
bit 16 DIVP1EN
131
+
fld 11 10 PLL3RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; }
132
+
bit 9 PLL3VCOSEL { enum WIDE 0; enum MEDIUM 1; }
133
+
bit 8 PLL3FRACEN
134
+
fld 7 6 PLL2RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; }
135
+
bit 5 PLL2VCOSEL { enum WIDE 0; enum MEDIUM 1; }
136
+
bit 4 PLL2FRACEN
137
+
fld 3 2 PLL1RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; }
138
+
bit 1 PLL1VCOSEL { enum WIDE 0; enum MEDIUM 1; }
139
+
bit 0 PLL1FRACEN
140
+
}
141
+
142
+
reg PLLxDIVR {
143
+
instance PLL1DIVR 0x30
144
+
instance PLL2DIVR 0x38
145
+
instance PLL3DIVR 0x40
146
+
147
+
fld 30 24 DIVR
148
+
fld 22 16 DIVQ
149
+
fld 15 9 DIVP
150
+
fld 8 0 DIVN
151
+
}
152
+
153
+
reg PLLxFRACR {
154
+
instance PLL1FRACR 0x34
155
+
instance PLL2FRACR 0x3c
156
+
instance PLL3FRACR 0x44
157
+
158
+
fld 15 3 FRACN
159
+
}
160
+
161
+
reg D1CCIPR 0x4c {
162
+
fld 29 28 CKPERSEL { enum HSI 0; enum CSI 1; enum HSE 2; }
163
+
bit 16 SDMMCSEL { enum PLL1Q 0; enum PLL2R 1; }
164
+
fld 5 4 QSPISEL { enum AHB 0; enum PLL1Q 1; enum PLL2R 2; enum PER 3; }
165
+
fld 1 0 FMCSEL { enum AHB 0; enum PLL1Q 1; enum PLL2R 2; enum PER 3; }
166
+
}
167
+
168
+
reg D2CCIP1R 0x50 {
169
+
bit 31 SWPSEL { enum APB1 0; enum HSI 1; }
170
+
fld 29 28 FDCANSEL { enum HSE 0; enum PLL1Q 1; enum PLL2Q 1; }
171
+
bit 24 DFSDM1SEL { enum APB2 0; enum SYSCLK 1; }
172
+
fld 21 20 SPDIFSEL { enum PLL1Q 0; enum PLL2R 1; enum PLL3R 2; enum HSI 3; }
173
+
fld 18 16 SPI45SEL { enum APB2 0; enum PLL2Q 1; enum PLL3Q 2; enum HSI 3;
174
+
enum CSI 4; enum HSE 5; }
175
+
fld 14 12 SPI123SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 3;
176
+
enum PER 4; }
177
+
fld 8 6 SAI23SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 4;
178
+
enum PER 4; }
179
+
fld 2 0 SAI1SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 4;
180
+
enum PER 4; }
181
+
}
182
+
183
+
reg D2CCIP2R 0x54 {
184
+
fld 30 28 LPTIM1SEL { enum APB1 0; enum PLL2P 1; enum PLL3R 2;
185
+
enum LSE 3; enum LSI 4; enum PER 5; }
186
+
fld 23 22 CECSEL { enum LSE 0; enum LSI 1; enum CSI 2; }
187
+
fld 21 20 USBSEL { enum DISABLE 0; enum PLL1Q 1; enum PLL3Q 2; enum HSI48 3; }
188
+
fld 13 12 I2C123SEL { enum APB1 0; enum PLL3R 1; enum HSI 2; enum CSI 3; }
189
+
fld 9 8 RNGSEL { enum HSI 0; enum PLL1Q 1; enum LSE 2; enum LSI 3; }
190
+
fld 5 3 USART16SEL { enum APB2 0; enum PLL2Q 1; enum PLL3Q 2;
191
+
enum HSI 3; enum CSI 4; enum LSE 5; }
192
+
fld 2 0 USART234578SEL { enum APB1 0; enum PLL2Q 1; enum PLL3Q 2;
193
+
enum HSI 3; enum CSI 4; enum LSE 5; }
194
+
}
195
+
196
+
reg D3CCIPR 0x58 {
197
+
fld 30 28 SPI6SEL { enum APB4 0; enum PLL2Q 1; enum PLL3Q 2;
198
+
enum HSI 3; enum CSI 4; enum HSE 5; }
199
+
fld 26 24 SAI4BSEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2;
200
+
enum I2S_CKIN 3; enum PER 4; }
201
+
fld 23 21 SAI4ASEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2;
202
+
enum I2S_CKIN 3; enum PER 4; }
203
+
fld 17 16 ADCSEL { enum PLL2P 0; enum PLL3R 1; enum PER 2; }
204
+
fld 15 13 LPTIM345SEL { enum APB4 0; enum PLL2P 1; enum PLL3R 2;
205
+
enum LSE 3; enum LSI 4; enum PER 5; }
206
+
fld 12 10 LPTIM2SEL { enum APB4 0; enum PLL2P 1; enum PLL3R 2;
207
+
enum LSE 3; enum LSI 4; enum PER 5; }
208
+
fld 9 8 I2C4SEL { enum APB4 0; enum PLL3R 1; enum HSI 2; enum CSI 3; }
209
+
fld 2 0 LPUART1SEL { enum APB4 0; enum PLL2Q 1; enum PLL3Q 2;
210
+
enum HSI 3; enum CSI 4; enum LSE 5; }
211
+
}
212
+
213
+
reg BDCR 0x70 {
214
+
bit 16 BDRST
215
+
bit 15 RTCEN
216
+
fld 9 8 RTCSEL { enum NONE 0; enum LSE 1; enum LSI 2; enum HSE 3; }
217
+
bit 6 LSECSSD
218
+
bit 5 LSECSSON
219
+
fld 4 3 LSEDRV { enum LOW 0; enum MED_LOW 1; enum MED_HIGH 2; enum HIGH 3; }
220
+
bit 2 LSEBYP
221
+
bit 1 LSERDY
222
+
bit 0 LSEON
223
+
}
224
+
225
+
reg CSR 0x74 {
226
+
bit 1 LSIRDY
227
+
bit 0 LSION
228
+
}
229
+
230
+
reg AHB3EN {
231
+
instance AHB3ENR 0xd4
232
+
instance AHB3LPENR 0xfc
233
+
234
+
# note:
235
+
# - bits 8 and 28-31 exist in AHB3LPENR only
236
+
# - all other bits are common
237
+
238
+
bit 31 AXISRAMEN
239
+
bit 30 ITCMEN
240
+
bit 29 DTCM2EN
241
+
bit 28 D1DTCM1EN
242
+
bit 16 SDMMC1EN
243
+
bit 14 QSPIEN
244
+
bit 12 FMCEN
245
+
bit 8 FLASHEN
246
+
bit 5 JPEGDECEN
247
+
bit 4 DMA2DEN
248
+
bit 0 MDMAEN
249
+
}
250
+
251
+
reg AHB4EN {
252
+
instance AHB4ENR 0xe0
253
+
instance AHB4LPENR 0x108
254
+
255
+
# note:
256
+
# - bit 29 exists in AHB4LPENR only
257
+
# - bit 25 exists in AHB4ENR only
258
+
# - all other bits are common
259
+
260
+
bit 29 SRAM4EN
261
+
bit 28 BKPRAMEN
262
+
bit 25 HSEMEN
263
+
bit 24 ADC3EN
264
+
bit 21 BDMAEN
265
+
bit 19 CRCEN
266
+
bit 10 GPIOKEN
267
+
bit 9 GPIOJEN
268
+
bit 8 GPIOIEN
269
+
bit 7 GPIOHEN
270
+
bit 6 GPIOGEN
271
+
bit 5 GPIOFEN
272
+
bit 4 GPIOEEN
273
+
bit 3 GPIODEN
274
+
bit 2 GPIOCEN
275
+
bit 1 GPIOBEN
276
+
bit 0 GPIOAEN
277
+
}
278
+
279
+
reg APB3EN {
280
+
instance APB3ENR 0xe4
281
+
instance APB3LPENR 0x10c
282
+
283
+
bit 6 WWDG1EN
284
+
bit 3 LTDCEN
285
+
}
286
+
287
+
reg APB1LEN {
288
+
instance APB1LENR 0xe8
289
+
instance APB1LLPENR 0x110
290
+
291
+
bit 31 UART8EN
292
+
bit 30 UART7EN
293
+
bit 29 DAC12EN
294
+
bit 27 CECEN
295
+
bit 23 I2C3EN
296
+
bit 22 I2C2EN
297
+
bit 21 I2C1EN
298
+
bit 20 UART5EN
299
+
bit 19 UART4EN
300
+
bit 18 USART3EN
301
+
bit 17 USART2EN
302
+
bit 16 SPDIFRXEN
303
+
bit 15 SPI3EN
304
+
bit 14 SPI2EN
305
+
bit 9 LPTIM1EN
306
+
bit 8 TIM14EN
307
+
bit 7 TIM13EN
308
+
bit 6 TIM12EN
309
+
bit 5 TIM7EN
310
+
bit 4 TIM6EN
311
+
bit 3 TIM5EN
312
+
bit 2 TIM4EN
313
+
bit 1 TIM3EN
314
+
bit 0 TIM2EN
315
+
}
316
+
317
+
reg APB1HEN {
318
+
instance APB1HENR 0xec
319
+
instance APB1HLPENR 0x114
320
+
321
+
bit 8 FDCANEN
322
+
bit 5 MDIOSEN
323
+
bit 4 OPAMPEN
324
+
bit 2 SWPEN
325
+
bit 1 CRSEN
326
+
}
327
+
328
+
reg APB2EN {
329
+
instance APB2ENR 0xf0
330
+
instance APB2LPENR 0x118
331
+
332
+
bit 29 HRTIMEN
333
+
bit 28 DFSDM1EN
334
+
bit 24 SAI3EN
335
+
bit 23 SAI2EN
336
+
bit 22 SAI1EN
337
+
bit 20 SPI5EN
338
+
bit 18 TIM17EN
339
+
bit 17 TIM16EN
340
+
bit 16 TIM15EN
341
+
bit 13 SPI4EN
342
+
bit 12 SPI1EN
343
+
bit 5 USART6EN
344
+
bit 4 USART1EN
345
+
bit 1 TIM8EN
346
+
bit 0 TIM1EN
347
+
}
348
+
349
+
reg APB4EN {
350
+
instance APB4ENR 0xf4
351
+
instance APB4LPENR 0x11c
352
+
353
+
bit 21 SAI4EN
354
+
bit 16 RTCAPBEN
355
+
bit 15 VREFEN
356
+
bit 14 COMP12EN
357
+
bit 12 LPTIM5EN
358
+
bit 11 LPTIM4EN
359
+
bit 10 LPTIM3EN
360
+
bit 9 LPTIM2EN
361
+
bit 7 I2C4EN
362
+
bit 5 SPI6EN
363
+
bit 3 LPUART1EN
364
+
bit 1 SYSCFGEN
365
+
}
366
+
}
367
+
368
+
node GPIO {
369
+
title "General-purpose I/Os"
370
+
instance 0x58020000 0x400 11
371
+
372
+
reg MODER 0x00
373
+
reg OTYPER 0x04
374
+
reg OSPEEDR 0x08
375
+
reg PUPDR 0x0c
376
+
reg IDR 0x10
377
+
reg ODR 0x14
378
+
reg BSRR 0x18
379
+
reg LCKR 0x1c
380
+
reg AFRL 0x20
381
+
reg AFRH 0x24
382
+
}
383
+
384
+
node SYSCFG {
385
+
title "System configuration controller"
386
+
addr 0x58000400
387
+
388
+
reg PWRCFG 0x2c {
389
+
bit 0 ODEN
390
+
}
391
+
}
392
+
393
+
node FMC {
394
+
title "Flexible memory controller"
395
+
addr 0x52004000
396
+
397
+
reg BCR {
398
+
instance 0x000 0x8 4
399
+
400
+
bit 31 FMCEN
401
+
fld 25 24 BMAP
402
+
bit 21 WFDIS
403
+
}
404
+
405
+
reg SDCR {
406
+
instance 0x140 0x4 2
407
+
408
+
fld 14 13 RPIPE
409
+
bit 12 RBURST
410
+
fld 11 10 SDCLK
411
+
bit 9 WP
412
+
fld 8 7 CAS
413
+
bit 6 NB
414
+
fld 5 4 MWID
415
+
fld 3 2 NR
416
+
fld 1 0 NC
417
+
}
418
+
419
+
reg SDTR {
420
+
instance 0x148 0x4 2
421
+
422
+
fld 27 24 TRCD
423
+
fld 23 20 TRP
424
+
fld 19 16 TWR
425
+
fld 15 12 TRC
426
+
fld 11 8 TRAS
427
+
fld 7 4 TXSR
428
+
fld 3 0 TMRD
429
+
}
430
+
431
+
reg SDCMR 0x150 {
432
+
fld 22 9 MRD
433
+
fld 8 5 NRFS
434
+
bit 4 CTB1
435
+
bit 3 CTB2
436
+
fld 2 0 MODE
437
+
}
438
+
439
+
reg SDRTR 0x154 {
440
+
bit 14 REIE
441
+
fld 13 1 COUNT
442
+
bit 0 CRE
443
+
}
444
+
445
+
reg SDSR 0x158 {
446
+
fld 4 3 MODES2
447
+
fld 2 1 MODES1
448
+
bit 0 RE
449
+
}
450
+
}
451
+
452
+
node RTC {
453
+
title "Real time clock"
454
+
addr 0x58004000
455
+
456
+
reg TR {
457
+
instance TR 0x00
458
+
instance TSTR 0x30
459
+
460
+
bit 22 PM
461
+
fld 21 20 HT
462
+
fld 19 16 HU
463
+
fld 14 12 MNT
464
+
fld 11 8 MNU
465
+
fld 6 4 ST
466
+
fld 3 0 SU
467
+
}
468
+
469
+
reg DR {
470
+
instance DR 0x04
471
+
instance DRTR 0x34
472
+
473
+
fld 23 20 YT
474
+
fld 19 16 YU
475
+
fld 15 13 WDU
476
+
bit 12 MT
477
+
fld 11 8 MU
478
+
fld 5 4 DT
479
+
fld 3 0 DU
480
+
}
481
+
482
+
reg CR 0x08 {
483
+
bit 24 ITSE
484
+
bit 23 COE
485
+
fld 22 21 OSEL { enum DISABLED 0; enum ALARM_A 1; enum ALARM_B 2; enum WAKEUP 3; }
486
+
bit 20 POL
487
+
bit 19 COSEL
488
+
bit 18 BKP
489
+
bit 17 SUB1H
490
+
bit 16 ADD1H
491
+
bit 15 TSIE
492
+
bit 14 WUTIE
493
+
bit 13 ALRBIE
494
+
bit 12 ALRAIE
495
+
bit 11 TSE
496
+
bit 10 WUTE
497
+
bit 9 ALRBE
498
+
bit 8 ALRAE
499
+
bit 6 FMT
500
+
bit 5 BYPSHAD
501
+
bit 4 REFCKON
502
+
bit 3 TSEDGE
503
+
bit 2 0 WUCKSEL { enum RTC_16 0; enum RTC_8 1; enum RTC_4 2; enum RTC_2 3;
504
+
enum CK_SPRE 4; enum CK_SPRE_ADDWUT 6; }
505
+
}
506
+
507
+
reg ISR 0x0c {
508
+
bit 17 ITSF
509
+
bit 16 RECALPF
510
+
bit 15 TAMP3F
511
+
bit 14 TAMP2F
512
+
bit 13 TAMP1F
513
+
bit 12 TSOVF
514
+
bit 11 TSF
515
+
bit 10 WUTF
516
+
bit 9 ALRBF
517
+
bit 8 ALRAF
518
+
bit 7 INIT
519
+
bit 6 INITF
520
+
bit 5 RSF
521
+
bit 4 INITS
522
+
bit 3 SHPF
523
+
bit 2 WUTWF
524
+
bit 1 ALRBWF
525
+
bit 0 ALRAWF
526
+
}
527
+
528
+
reg PRER 0x10 {
529
+
fld 22 16 PREDIV_A
530
+
fld 14 0 PREDIV_S
531
+
}
532
+
533
+
reg WPR 0x24 {
534
+
fld 7 0 KEY { enum KEY1 0xCA; enum KEY2 0x53; }
535
+
}
536
+
537
+
reg SSR {
538
+
instance SSR 0x28
539
+
instance TSSSR 0x38
540
+
541
+
fld 15 0 SS
542
+
}
543
+
544
+
reg OR 0x4c {
545
+
bit 1 RTC_OUT_RMP
546
+
bit 0 RTC_ALARM_TYPE { enum OPEN_DRAIN 0; enum PUSH_PULL 1; }
547
+
}
548
+
549
+
reg BKPR {
550
+
instance 0x50 0x4 32
551
+
}
552
+
}
553
+
554
+
node SPI {
555
+
title "Serial peripheral interface"
556
+
instance nochild SPI1 0x40013000
557
+
instance nochild SPI2 0x40003800
558
+
instance nochild SPI3 0x40003c00
559
+
instance nochild SPI4 0x40013400
560
+
instance nochild SPI5 0x40015000
561
+
instance nochild SPI6 0x58001400
562
+
instance floating
563
+
564
+
reg CR1 0x00 {
565
+
bit 16 IO_LOCK
566
+
bit 15 TCRCINI
567
+
bit 14 RCRCINI
568
+
bit 13 CRC33_17
569
+
bit 12 SSI
570
+
bit 11 HDDIR
571
+
bit 10 CSUSP
572
+
bit 9 CSTART
573
+
bit 8 MASRX
574
+
bit 0 SPE
575
+
}
576
+
577
+
reg CR2 0x04 {
578
+
fld 31 16 TSER
579
+
fld 15 0 TSIZE
580
+
}
581
+
582
+
reg CFG1 0x08 {
583
+
fld 30 28 MBR
584
+
bit 22 CRCEN
585
+
fld 20 16 CRCSIZE
586
+
bit 15 TXDMAEN
587
+
bit 14 RXDMAEN
588
+
fld 12 11 UDRDET
589
+
fld 10 9 UDRCFG
590
+
fld 8 5 FTHLV
591
+
fld 4 0 DSIZE
592
+
}
593
+
594
+
reg CFG2 0x0c {
595
+
bit 31 AFCNTR
596
+
bit 30 SSOM
597
+
bit 29 SSOE
598
+
bit 28 SSIOP
599
+
bit 26 SSM { enum SS_PAD 0; enum SSI_BIT 1; }
600
+
bit 25 CPOL
601
+
bit 24 CPHA
602
+
bit 23 LSBFIRST
603
+
bit 22 MASTER
604
+
fld 21 19 SP { enum MOTOROLA 0; enum TI 1; }
605
+
fld 18 17 COMM { enum DUPLEX 0; enum TXONLY 1; enum RXONLY 2; enum HALF_DUPLEX 3; }
606
+
bit 15 IOSWP
607
+
fld 7 4 MIDI
608
+
fld 3 0 MSSI
609
+
}
610
+
611
+
reg IER 0x10 {
612
+
bit 10 TSERFIE
613
+
bit 9 MODFIE
614
+
bit 8 TIFREIE
615
+
bit 7 CRCEIE
616
+
bit 6 OVRIE
617
+
bit 5 UDRIE
618
+
bit 4 TXTFIE
619
+
bit 3 EOTIE
620
+
bit 2 DXPIE
621
+
bit 1 TXPIE
622
+
bit 0 RXPIE
623
+
}
624
+
625
+
reg SR 0x14 {
626
+
fld 31 16 CTSIZE
627
+
bit 15 RXWNE
628
+
fld 14 13 RXPLVL
629
+
bit 12 TXC
630
+
bit 11 SUSP
631
+
bit 10 TSERF
632
+
bit 9 MODF
633
+
bit 8 TIFRE
634
+
bit 7 CRCE
635
+
bit 6 OVR
636
+
bit 5 UDR
637
+
bit 4 TXTF
638
+
bit 3 EOT
639
+
bit 2 DXP
640
+
bit 1 TXP
641
+
bit 0 RXP
642
+
}
643
+
644
+
reg IFCR 0x18 {
645
+
bit 11 SUSPC
646
+
bit 10 TSERFC
647
+
bit 9 MODFC
648
+
bit 8 TIFREC
649
+
bit 7 CRCEC
650
+
bit 6 OVRC
651
+
bit 5 UDRC
652
+
bit 4 TXTFC
653
+
bit 3 EOTC
654
+
}
655
+
656
+
reg 8 TXDR8 0x20
657
+
reg 16 TXDR16 0x20
658
+
reg 32 TXDR32 0x20
659
+
reg 8 RXDR8 0x30
660
+
reg 16 RXDR16 0x30
661
+
reg 32 RXDR32 0x30
662
+
663
+
reg CRCPOLY 0x40
664
+
reg TXCRC 0x44
665
+
reg RXCRC 0x48
666
+
reg UDRDR 0x4c
667
+
668
+
reg I2SCFGR 0x50 {
669
+
bit 25 MCKOE
670
+
bit 24 ODD
671
+
fld 23 16 I2SDIV
672
+
bit 14 DATFMT { enum RIGHT_ALIGNED 0; enum LEFT_ALIGNED 1; }
673
+
bit 13 WSINV
674
+
bit 12 FIXCH
675
+
bit 11 CKPOL
676
+
bit 10 CHLEN { enum 16BIT 0; enum 32BIT 1; }
677
+
fld 9 8 DATLEN { enum 16BIT 0; enum 24BIT 1; enum 32BIT 2; }
678
+
bit 7 PCMSYNC { enum SHORT 0; enum LONG 1; }
679
+
fld 5 4 I2SSTD { enum I2S 0; enum MSB_JUSTIFIED 1; enum LSB_JUSTIFIED 2; enum PCM 3; }
680
+
fld 3 1 I2SCFG { enum SLAVE_TX 0; enum SLAVE_RX 1;
681
+
enum MASTER_TX 2; enum MASTER_RX 3;
682
+
enum SLAVE_DUPLEX 4; enum MASTER_DUPLEX 5; }
683
+
bit 0 I2SMOD
684
+
}
685
+
}