+130

src/Cpu.zig

··· 771 771 inline fn rti(self: *Cpu, pins: *zesty.Pins) void { 772 772 switch (self.cycle) { 773 773 0 => { 774 774 + // Dummy read 774 775 pins.cpu_addr = self.pc; 775 776 }, 776 777 1 => { ··· 803 804 else => { 804 805 self.hilo.hi = pins.cpu_data; 805 806 self.fetchAt(pins, self.hilo.addr()); 807 807 + }, 808 808 + } 809 809 + } 810 810 + 811 811 + /// Jump (JMP) 812 812 + inline fn jmp(self: *Cpu, pins: *zesty.Pins) void { 813 813 + switch (self.cycle) { 814 814 + 0 => { 815 815 + self.pc +%= 1; 816 816 + pins.cpu_addr = self.pc; 817 817 + }, 818 818 + 1 => { 819 819 + self.pc +%= 1; 820 820 + pins.cpu_addr = self.pc; 821 821 + self.hilo = .{ .lo = pins.cpu_data }; 822 822 + }, 823 823 + else => { 824 824 + self.hilo.hi = pins.cpu_data; 825 825 + self.fetchAt(pins, self.hilo.addr()); 826 826 + }, 827 827 + } 828 828 + } 829 829 + 830 830 + /// Jump indirect (JMP) 831 831 + inline fn jmpInd(self: *Cpu, pins: *zesty.Pins) void { 832 832 + switch (self.cycle) { 833 833 + 0 => { 834 834 + self.pc +%= 1; 835 835 + pins.cpu_addr = self.pc; 836 836 + }, 837 837 + 1 => { 838 838 + // Fetch indirect lo 839 839 + self.pc +%= 1; 840 840 + pins.cpu_addr = self.pc; 841 841 + self.hilo = .{ .lo = pins.cpu_data }; 842 842 + }, 843 843 + 2 => { 844 844 + // Fetch indirect hi 845 845 + self.hilo.hi = pins.cpu_data; 846 846 + pins.cpu_addr = self.hilo.addr(); 847 847 + }, 848 848 + 3 => { 849 849 + // Fetch target lo 850 850 + self.hilo.lo +%= 1; 851 851 + pins.cpu_addr = self.hilo.addr(); 852 852 + self.hilo = .{ .lo = pins.cpu_data }; 853 853 + }, 854 854 + else => { 855 855 + // Fetch target hi 856 856 + self.hilo.hi = pins.cpu_data; 857 857 + self.fetchAt(pins, self.hilo.addr()); 858 858 + }, 859 859 + } 860 860 + } 861 861 + 862 862 + /// Jump to subroutine (JSR) 863 863 + inline fn jsr(self: *Cpu, pins: *zesty.Pins) void { 864 864 + const pc: Addr = .from(self.pc); 865 865 + const stack: Addr = .stack(self.sp); 866 866 + 867 867 + switch (self.cycle) { 868 868 + 0 => { 869 869 + self.pc +%= 1; 870 870 + pins.cpu_addr = self.pc; 871 871 + }, 872 872 + 1 => { 873 873 + // Fetch target lo 874 874 + self.hilo = .{ .lo = pins.cpu_data }; 875 875 + pins.cpu_addr = stack.addr(); 876 876 + }, 877 877 + 2 => { 878 878 + // Store PC hi 879 879 + pins.cpu_addr = stack.addr(); 880 880 + pins.cpu_data = pc.hi; 881 881 + pins.cpu_rw = .write; 882 882 + self.sp -%= 1; 883 883 + }, 884 884 + 3 => { 885 885 + // Store PC lo 886 886 + pins.cpu_addr = stack.addr(); 887 887 + pins.cpu_data = pc.lo; 888 888 + pins.cpu_rw = .write; 889 889 + self.sp -%= 1; 890 890 + }, 891 891 + 4 => { 892 892 + // Reposition back to PC 893 893 + self.pc +%= 1; 894 894 + pins.cpu_addr = self.pc; 895 895 + }, 896 896 + else => { 897 897 + // Fetch target hi 898 898 + self.hilo.hi = pins.cpu_data; 899 899 + self.fetchAt(pins, self.hilo.addr()); 900 900 + }, 901 901 + } 902 902 + } 903 903 + 904 904 + /// RTS (return from subroutine) 905 905 + inline fn rts(self: *Cpu, pins: *zesty.Pins) void { 906 906 + const stack: Addr = .stack(self.sp); 907 907 + switch (self.cycle) { 908 908 + 0 => { 909 909 + // Dummy read 910 910 + pins.cpu_addr = self.pc; 911 911 + }, 912 912 + 1 => { 913 913 + // Dummy read 914 914 + pins.cpu_addr = stack.addr(); 915 915 + self.sp +%= 1; 916 916 + }, 917 917 + 2 => { 918 918 + // Dummy read 919 919 + pins.cpu_addr = stack.addr(); 920 920 + self.sp +%= 1; 921 921 + }, 922 922 + 3 => { 923 923 + // Pop PC lo 924 924 + self.hilo = .{ .lo = pins.cpu_data }; 925 925 + pins.cpu_addr = stack.addr(); 926 926 + }, 927 927 + 4 => { 928 928 + // Pop PC hi 929 929 + self.hilo.hi = pins.cpu_data; 930 930 + self.pc = self.hilo.addr(); 931 931 + pins.cpu_addr = self.pc; 932 932 + self.pc +%= 1; 933 933 + }, 934 934 + else => { 935 935 + self.fetch(pins); 806 936 }, 807 937 } 808 938 }

+3 -5

src/tests/cpu/assembler.zig

··· 42 42 .absolute, 43 43 .absolute_x, 44 44 .absolute_y, 45 45 - .indexed, 45 45 + .indirect, 46 46 => |v| try writer.writeInt(u16, v, .little), 47 47 } 48 48 } ··· 431 431 absolute_x: u16, 432 432 absolute_y: u16, 433 433 immediate: u8, 434 434 - indexed: u16, 434 434 + indirect: u16, 435 435 indexed_indirect: u8, 436 436 indirect_indexed: u8, 437 437 ··· 509 509 }; 510 510 } 511 511 512 512 - if (r_paren != s.len) return error.InvalidSyntax; 513 513 - 514 512 // (ind) 515 513 return .{ 516 516 - .indexed = try parseInt(u16, std.mem.trim( 514 514 + .indirect = try parseInt(u16, std.mem.trim( 517 515 u8, 518 516 s[1..r_paren], 519 517 whitespace,

+92 -1

src/tests/cpu/control_flow.zig

··· 114 114 } 115 115 116 116 test "branches" { 117 117 - // TODO: Test overflow as well 118 117 var z = cpu.testZes(.{ .rom = &.{ 119 118 .{ 120 119 0x8000, cpu.assemble( ··· 159 158 z.stepCpu(); // BMI 160 159 z.stepCpu(); // BMI 161 160 try std.testing.expectEqual(0x800c, z.cpu.pc); 161 161 + 162 162 + cpu.run(&z); // BIT 163 163 + try std.testing.expectEqual(0x800e, z.cpu.pc); 164 164 + try std.testing.expect(z.cpu.status.overflow); 165 165 + 166 166 + z.stepCpu(); // BVS 167 167 + z.stepCpu(); // BVS 168 168 + z.stepCpu(); // BVS 169 169 + try std.testing.expectEqual(0x8011, z.cpu.pc); 170 170 + 171 171 + // Never hit BRK 172 172 + try std.testing.expect(!z.cpu.status.brk); 173 173 + } 174 174 + 175 175 + test "subroutines" { 176 176 + var z = cpu.testZes(.{ .rom = &.{ 177 177 + .{ 178 178 + 0x8000, cpu.assemble( 179 179 + \\jsr $8007 180 180 + \\cmp $8008 181 181 + \\brk 182 182 + \\lda #$80 183 183 + \\rts 184 184 + ), 185 185 + }, 186 186 + } }); 187 187 + 188 188 + try std.testing.expectEqual(0xfd, z.cpu.sp); 189 189 + cpu.run(&z); // JSR 190 190 + try std.testing.expectEqual(0x8007, z.cpu.pc); 191 191 + try std.testing.expectEqual(0xfb, z.cpu.sp); 192 192 + try std.testing.expectEqual(0x01, z.ram[0x1fc]); 193 193 + try std.testing.expectEqual(0x80, z.ram[0x1fd]); 194 194 + 195 195 + cpu.run(&z); // LDA 196 196 + try std.testing.expectEqual(0x8009, z.cpu.pc); 197 197 + try std.testing.expectEqual(0x80, z.cpu.a); 198 198 + try std.testing.expect(z.cpu.status.negative); 199 199 + 200 200 + // TODO: figure out why the run harness runs two commands at once 201 201 + cpu.run(&z); // RTS, CMP 202 202 + try std.testing.expectEqual(0x8006, z.cpu.pc); 203 203 + try std.testing.expectEqual(0xfd, z.cpu.sp); 204 204 + try std.testing.expect(z.cpu.status.zero); // Should be equal 205 205 + 206 206 + // Never hit BRK 207 207 + try std.testing.expect(!z.cpu.status.brk); 208 208 + } 209 209 + 210 210 + test "JMP" { 211 211 + var z = cpu.testZes(.{ .rom = &.{ 212 212 + .{ 213 213 + 0x8000, cpu.assemble( 214 214 + \\jmp $8004 215 215 + \\brk 216 216 + \\lda $8000 217 217 + ), 218 218 + }, 219 219 + } }); 220 220 + 221 221 + cpu.run(&z); // JMP 222 222 + try std.testing.expectEqual(0x8004, z.cpu.pc); 223 223 + 224 224 + cpu.run(&z); // LDA 225 225 + try std.testing.expectEqual(0x8007, z.cpu.pc); 226 226 + try std.testing.expectEqual(0x4c, z.cpu.a); 227 227 + 228 228 + // Never hit BRK 229 229 + try std.testing.expect(!z.cpu.status.brk); 230 230 + } 231 231 + 232 232 + test "JMP indirect" { 233 233 + var z = cpu.testZes(.{ .rom = &.{ 234 234 + .{ 235 235 + 0x8000, cpu.assemble( 236 236 + \\jmp ($aabb) 237 237 + \\brk 238 238 + \\lda $8000 239 239 + ), 240 240 + }, 241 241 + .{ 0xaabb, &.{ 0x04, 0x80 } }, 242 242 + } }); 243 243 + 244 244 + cpu.run(&z); // JMP 245 245 + try std.testing.expectEqual(0x8004, z.cpu.pc); 246 246 + 247 247 + cpu.run(&z); // LDA 248 248 + try std.testing.expectEqual(0x8007, z.cpu.pc); 249 249 + try std.testing.expectEqual(0x6c, z.cpu.a); 250 250 + 251 251 + // Never hit BRK 252 252 + try std.testing.expect(!z.cpu.status.brk); 162 253 }