+69 -2

src/Cpu.zig

··· 112 112 0x01 => if (self.zpXInd(pins)) |_| self.ora(pins, v), // ORA (zp,X) 113 113 0x05 => if (self.zp(pins)) |_| self.ora(pins, v), // ORA zp 114 114 0x06 => if (self.zp(pins)) |_| self.asl(pins, .mem), // ASL zp 115 115 + 0x08 => self.php(pins), // PHP 115 116 0x09 => if (self.imm(pins)) |_| self.ora(pins, v), // ORA # 116 117 0x0a => if (self.imm(pins)) |_| self.asl(pins, .acc), // ASL A 117 118 0x0d => if (self.abs(pins)) |_| self.ora(pins, v), // ORA abs ··· 131 132 0x24 => if (self.zp(pins)) |_| self.bit(pins), // BIT zp 132 133 0x25 => if (self.zp(pins)) |_| self._and(pins, v), // AND zp 133 134 0x26 => if (self.zp(pins)) |_| self.rol(pins, .mem), // ROL zp 135 135 + 0x28 => self.plp(pins), // PLP 134 136 0x29 => if (self.imm(pins)) |_| self._and(pins, v), // AND # 135 137 0x2a => if (self.imm(pins)) |_| self.rol(pins, .acc), // ROL A 136 138 0x2c => if (self.abs(pins)) |_| self.bit(pins), // BIT abs ··· 150 152 0x41 => if (self.zpXInd(pins)) |_| self.eor(pins, v), // EOR (zp,X) 151 153 0x45 => if (self.zp(pins)) |_| self.eor(pins, v), // EOR zp 152 154 0x46 => if (self.zp(pins)) |_| self.lsr(pins, .mem), // LSR zp 155 155 + 0x48 => self.pha(pins), // PHA 153 156 0x49 => if (self.imm(pins)) |_| self.eor(pins, v), // EOR # 154 157 0x4a => if (self.imm(pins)) |_| self.lsr(pins, .acc), // LSR A 155 158 0x4c => self.jmp(pins), // JMP abs ··· 169 172 0x61 => if (self.zpXInd(pins)) |_| self.adc(pins, v), // ADC (zp,X) 170 173 0x65 => if (self.zp(pins)) |_| self.adc(pins, v), // ADC zp 171 174 0x66 => if (self.zp(pins)) |_| self.ror(pins, .mem), // ROR zp 175 175 + 0x68 => self.pla(pins), // PLA 172 176 0x69 => if (self.imm(pins)) |_| self.adc(pins, v), // ADC # 173 177 0x6a => if (self.imm(pins)) |_| self.ror(pins, .acc), // ROR A 174 178 0x6c => self.jmpInd(pins), // JMP (ind) ··· 425 429 } 426 430 427 431 //------------------------------------------------------ 428 428 - // Opcodes: Load/Store & Arithmetic 429 429 - const Dst = enum { acc, mem }; 432 432 + // Opcodes: Load/Store 430 433 431 434 inline fn ld(self: *Cpu, pins: *zesty.Pins, to: *u8, from: u8) void { 432 435 to.* = from; ··· 438 441 pins.cpu_rw = .write; 439 442 self.fetch(pins); 440 443 } 444 444 + inline fn push(self: *Cpu, pins: *zesty.Pins, v: u8) void { 445 445 + switch (self.cycle) { 446 446 + // Dummy read 447 447 + 0 => pins.cpu_addr = self.pc, 448 448 + 1 => { 449 449 + self.hilo = .stack(self.sp); 450 450 + pins.cpu_addr = self.hilo.addr(); 451 451 + pins.cpu_data = v; 452 452 + pins.cpu_rw = .write; 453 453 + self.sp -%= 1; 454 454 + }, 455 455 + else => self.fetch(pins), 456 456 + } 457 457 + } 458 458 + inline fn pull(self: *Cpu, pins: *zesty.Pins) ?u8 { 459 459 + switch (self.cycle) { 460 460 + // Dummy read 461 461 + 0 => pins.cpu_addr = self.pc, 462 462 + 1 => { 463 463 + self.hilo = .stack(self.sp); 464 464 + pins.cpu_addr = self.hilo.addr(); 465 465 + self.sp +%= 1; 466 466 + }, 467 467 + 2 => { 468 468 + self.hilo = .stack(self.sp); 469 469 + pins.cpu_addr = self.hilo.addr(); 470 470 + }, 471 471 + else => { 472 472 + self.fetch(pins); 473 473 + return pins.cpu_data; 474 474 + }, 475 475 + } 476 476 + return null; 477 477 + } 478 478 + inline fn pha(self: *Cpu, pins: *zesty.Pins) void { 479 479 + self.push(pins, self.a); 480 480 + } 481 481 + inline fn php(self: *Cpu, pins: *zesty.Pins) void { 482 482 + var status = self.status; 483 483 + // BRK is always set to true here 484 484 + status.brk = true; 485 485 + self.push(pins, status.toByte()); 486 486 + } 487 487 + inline fn pla(self: *Cpu, pins: *zesty.Pins) void { 488 488 + self.a = self.pull(pins) orelse return; 489 489 + self.setNZ(self.a); 490 490 + } 491 491 + inline fn plp(self: *Cpu, pins: *zesty.Pins) void { 492 492 + const status: Status = .from(self.pull(pins) orelse return); 493 493 + self.status = .{ 494 494 + .negative = status.negative, 495 495 + .overflow = status.overflow, 496 496 + .brk = self.status.brk, // Do not inherit BRK. 497 497 + .decimal = status.decimal, 498 498 + .irq_disabled = status.irq_disabled, 499 499 + .zero = status.zero, 500 500 + .carry = status.carry, 501 501 + }; 502 502 + } 503 503 + 504 504 + //------------------------------------------------------ 505 505 + // Opcodes: Arithmetic 506 506 + 507 507 + const Dst = enum { acc, mem }; 441 508 inline fn ora(self: *Cpu, pins: *zesty.Pins, v: u8) void { 442 509 self.a |= v; 443 510 self.setNZ(self.a);

+1

src/tests/cpu.zig

··· 9 9 _ = @import("cpu/addressing.zig"); 10 10 _ = @import("cpu/alu.zig"); 11 11 _ = @import("cpu/control_flow.zig"); 12 12 + _ = @import("cpu/stack.zig"); 12 13 } 13 14 14 15 //------------------------------------------------------

+34

src/tests/cpu/assembler.zig

··· 73 73 stx, 74 74 sty, 75 75 76 76 + php, 77 77 + plp, 78 78 + pha, 79 79 + pla, 80 80 + 76 81 ora, 77 82 @"and", 78 83 eor, ··· 380 385 }, 381 386 .nop => switch (opr) { 382 387 .implied => 0xea, 388 388 + else => null, 389 389 + }, 390 390 + .pha => switch (opr) { 391 391 + .implied => 0x48, 392 392 + else => null, 393 393 + }, 394 394 + .pla => switch (opr) { 395 395 + .implied => 0x68, 396 396 + else => null, 397 397 + }, 398 398 + .php => switch (opr) { 399 399 + .implied => 0x08, 400 400 + else => null, 401 401 + }, 402 402 + .plp => switch (opr) { 403 403 + .implied => 0x28, 404 404 + else => null, 405 405 + }, 406 406 + .jmp => switch (opr) { 407 407 + .absolute => 0x4c, 408 408 + .indirect => 0x6c, 409 409 + else => null, 410 410 + }, 411 411 + .jsr => switch (opr) { 412 412 + .absolute => 0x20, 413 413 + else => null, 414 414 + }, 415 415 + .rts => switch (opr) { 416 416 + .implied => 0x60, 383 417 else => null, 384 418 }, 385 419 };

+96

src/tests/cpu/stack.zig

··· 1 1 + //! Stack-related tests. 2 2 + const std = @import("std"); 3 3 + const cpu = @import("../cpu.zig"); 4 4 + 5 5 + test "PHA/PLA" { 6 6 + var z = cpu.testZes(.{ .rom = &.{ 7 7 + .{ 8 8 + 0x8000, cpu.assemble( 9 9 + \\LDA #$89 10 10 + \\PHA 11 11 + \\LDA #0 12 12 + \\PLA 13 13 + ), 14 14 + }, 15 15 + } }); 16 16 + cpu.run(&z); // Setup A register 17 17 + 18 18 + try std.testing.expectEqual(0xfd, z.cpu.sp); 19 19 + cpu.run(&z); // PHA 20 20 + try std.testing.expectEqual(0xfc, z.cpu.sp); 21 21 + try std.testing.expectEqual(0x8003, z.cpu.pc); 22 22 + try std.testing.expectEqual(0x89, z.ram[0x1fd]); 23 23 + try std.testing.expect(z.cpu.status.negative); 24 24 + try std.testing.expect(!z.cpu.status.zero); 25 25 + 26 26 + cpu.run(&z); // Reset A register 27 27 + try std.testing.expectEqual(0x8005, z.cpu.pc); 28 28 + try std.testing.expectEqual(0x00, z.cpu.a); 29 29 + try std.testing.expect(!z.cpu.status.negative); 30 30 + try std.testing.expect(z.cpu.status.zero); 31 31 + 32 32 + cpu.run(&z); // PLA 33 33 + try std.testing.expectEqual(0x8006, z.cpu.pc); 34 34 + try std.testing.expectEqual(0x89, z.cpu.a); 35 35 + try std.testing.expectEqual(0xfd, z.cpu.sp); 36 36 + try std.testing.expect(z.cpu.status.negative); 37 37 + try std.testing.expect(!z.cpu.status.zero); 38 38 + } 39 39 + 40 40 + test "PHP/PLP" { 41 41 + var z = cpu.testZes(.{ .rom = &.{ 42 42 + .{ 43 43 + 0x8000, cpu.assemble( 44 44 + \\CLI 45 45 + \\SED 46 46 + \\LDA #0 47 47 + \\PHP 48 48 + \\ 49 49 + \\SEI 50 50 + \\CLD 51 51 + \\LDA #$ff 52 52 + \\PLP 53 53 + ), 54 54 + }, 55 55 + } }); 56 56 + 57 57 + // Prepare flags 58 58 + cpu.run(&z); // Clear I 59 59 + cpu.run(&z); // Set D 60 60 + cpu.run(&z); // Set Z 61 61 + try std.testing.expect(!z.cpu.status.negative); 62 62 + try std.testing.expect(z.cpu.status.zero); 63 63 + try std.testing.expect(z.cpu.status.decimal); 64 64 + try std.testing.expect(!z.cpu.status.irq_disabled); 65 65 + 66 66 + try std.testing.expectEqual(0xfd, z.cpu.sp); 67 67 + cpu.run(&z); // PHP 68 68 + try std.testing.expectEqual(0xfc, z.cpu.sp); 69 69 + 70 70 + try std.testing.expectEqual(0x8005, z.cpu.pc); 71 71 + try std.testing.expectEqual(0b00111010, z.ram[0x1fd]); 72 72 + 73 73 + // Reset flags 74 74 + cpu.run(&z); // Set I 75 75 + cpu.run(&z); // Clear D 76 76 + cpu.run(&z); // Clear Z; Set N 77 77 + try std.testing.expect(z.cpu.status.negative); 78 78 + try std.testing.expect(!z.cpu.status.zero); 79 79 + try std.testing.expect(!z.cpu.status.decimal); 80 80 + try std.testing.expect(z.cpu.status.irq_disabled); 81 81 + 82 82 + try std.testing.expectEqual(0xfc, z.cpu.sp); 83 83 + cpu.run(&z); // PLP 84 84 + try std.testing.expectEqual(0xfd, z.cpu.sp); 85 85 + 86 86 + try std.testing.expectEqual(0x800a, z.cpu.pc); 87 87 + 88 88 + // Check if flags are restored 89 89 + try std.testing.expect(!z.cpu.status.negative); 90 90 + try std.testing.expect(z.cpu.status.zero); 91 91 + try std.testing.expect(z.cpu.status.decimal); 92 92 + try std.testing.expect(!z.cpu.status.irq_disabled); 93 93 + 94 94 + // BRK should not be restored. 95 95 + try std.testing.expect(!z.cpu.status.brk); 96 96 + }