jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/arm: Split VMINMAXNM decode
Passing the raw op field from the manual is less instructive
than it might be. Do the full decode and use the existing
helpers to perform the expansion.
Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Richard Henderson
and committed by
Peter Maydell
f2eafb75
d486f830
+44
-77
+36
-73
target/arm/translate-vfp.inc.c
+36
-73
target/arm/translate-vfp.inc.c
···
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return true;
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}
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-
static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
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-
{
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uint32_t rd, rn, rm;
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bool dp = a->dp;
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bool vmin = a->op;
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TCGv_ptr fpst;
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if (!dc_isar_feature(aa32_vminmaxnm, s)) {
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return false;
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}
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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return false;
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}
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rd = a->vd;
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rn = a->vn;
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rm = a->vm;
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if (!vfp_access_check(s)) {
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return true;
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}
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fpst = get_fpstatus_ptr(0);
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if (dp) {
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TCGv_i64 frn, frm, dest;
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frn = tcg_temp_new_i64();
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frm = tcg_temp_new_i64();
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dest = tcg_temp_new_i64();
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-
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neon_load_reg64(frn, rn);
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neon_load_reg64(frm, rm);
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if (vmin) {
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gen_helper_vfp_minnumd(dest, frn, frm, fpst);
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} else {
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gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
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}
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neon_store_reg64(dest, rd);
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tcg_temp_free_i64(frn);
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tcg_temp_free_i64(frm);
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tcg_temp_free_i64(dest);
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} else {
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TCGv_i32 frn, frm, dest;
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-
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frn = tcg_temp_new_i32();
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frm = tcg_temp_new_i32();
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dest = tcg_temp_new_i32();
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-
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neon_load_reg32(frn, rn);
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neon_load_reg32(frm, rm);
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if (vmin) {
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gen_helper_vfp_minnums(dest, frn, frm, fpst);
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} else {
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gen_helper_vfp_maxnums(dest, frn, frm, fpst);
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}
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neon_store_reg32(dest, rd);
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tcg_temp_free_i32(frn);
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tcg_temp_free_i32(frm);
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tcg_temp_free_i32(dest);
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}
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tcg_temp_free_ptr(fpst);
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return true;
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}
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-
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/*
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* Table for converting the most common AArch32 encoding of
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* rounding mode to arm_fprounding order (which matches the
···
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static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
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{
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return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
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+
}
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+
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static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
1715
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{
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if (!dc_isar_feature(aa32_vminmaxnm, s)) {
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return false;
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}
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return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
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a->vd, a->vn, a->vm, false);
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}
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+
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static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
1724
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{
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if (!dc_isar_feature(aa32_vminmaxnm, s)) {
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return false;
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}
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return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
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a->vd, a->vn, a->vm, false);
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}
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+
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static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
1733
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{
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if (!dc_isar_feature(aa32_vminmaxnm, s)) {
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return false;
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}
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return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
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a->vd, a->vn, a->vm, false);
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}
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+
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static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
1742
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{
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if (!dc_isar_feature(aa32_vminmaxnm, s)) {
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return false;
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}
1746
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return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
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a->vd, a->vn, a->vm, false);
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}
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static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
+8
-4
target/arm/vfp-uncond.decode
+8
-4
target/arm/vfp-uncond.decode
···
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%vd_dp 22:1 12:4
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%vd_sp 12:4 22:1
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@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
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@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
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+
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VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
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VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
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-
VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
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VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
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VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
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+
VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s
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+
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+
VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
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+
VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d
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VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
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vm=%vm_sp vd=%vd_sp dp=0