jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
linux-headers: update to 4.15-rc1
Update headers against v4.15-rc1.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1511883692-11511-4-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Eric Auger
and committed by
Peter Maydell
dd873966
c9aedf8c
+74
-411
+1
include/standard-headers/asm-s390/virtio-ccw.h
+1
include/standard-headers/asm-s390/virtio-ccw.h
+1
-393
include/standard-headers/asm-x86/hyperv.h
+1
-393
include/standard-headers/asm-x86/hyperv.h
···
1
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#ifndef _ASM_X86_HYPERV_H
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#define _ASM_X86_HYPERV_H
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#include "standard-headers/linux/types.h"
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/*
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* The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
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* is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
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*/
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#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
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#define HYPERV_CPUID_INTERFACE 0x40000001
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#define HYPERV_CPUID_VERSION 0x40000002
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#define HYPERV_CPUID_FEATURES 0x40000003
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#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
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#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
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#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
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#define HYPERV_CPUID_MIN 0x40000005
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#define HYPERV_CPUID_MAX 0x4000ffff
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/*
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* Feature identification. EAX indicates which features are available
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* to the partition based upon the current partition privileges.
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*/
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/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
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#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
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/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
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#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
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/* Partition reference TSC MSR is available */
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#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9)
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/* A partition's reference time stamp counter (TSC) page */
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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/*
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* There is a single feature flag that signifies if the partition has access
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* to MSRs with local APIC and TSC frequencies.
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*/
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#define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11)
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/*
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* Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
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* and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
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*/
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#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
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/*
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* Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
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* HV_X64_MSR_STIMER3_COUNT) available
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*/
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#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
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/*
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* APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
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* are available
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*/
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#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
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/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
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#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
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/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
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#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
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/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
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#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
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/*
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* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
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* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
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* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
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*/
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#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
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/* Frequency MSRs available */
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#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8)
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/* Crash MSR available */
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#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
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/*
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* Feature identification: EBX indicates which flags were specified at
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* partition creation. The format is the same as the partition creation
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* flag structure defined in section Partition Creation Flags.
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*/
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#define HV_X64_CREATE_PARTITIONS (1 << 0)
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#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
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#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
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#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
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#define HV_X64_POST_MESSAGES (1 << 4)
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#define HV_X64_SIGNAL_EVENTS (1 << 5)
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#define HV_X64_CREATE_PORT (1 << 6)
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#define HV_X64_CONNECT_PORT (1 << 7)
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#define HV_X64_ACCESS_STATS (1 << 8)
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#define HV_X64_DEBUGGING (1 << 11)
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#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
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#define HV_X64_CONFIGURE_PROFILER (1 << 13)
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/*
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* Feature identification. EDX indicates which miscellaneous features
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* are available to the partition.
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*/
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/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
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#define HV_X64_MWAIT_AVAILABLE (1 << 0)
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/* Guest debugging support is available */
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#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
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/* Performance Monitor support is available*/
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#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
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/* Support for physical CPU dynamic partitioning events is available*/
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#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
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/*
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* Support for passing hypercall input parameter block via XMM
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* registers is available
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*/
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#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
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/* Support for a virtual guest idle state is available */
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#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
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/* Guest crash data handler available */
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#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
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/*
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* Implementation recommendations. Indicates which behaviors the hypervisor
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* recommends the OS implement for optimal performance.
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*/
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/*
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* Recommend using hypercall for address space switches rather
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* than MOV to CR3 instruction
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*/
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#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0)
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/* Recommend using hypercall for local TLB flushes rather
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* than INVLPG or MOV to CR3 instructions */
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#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
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/*
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* Recommend using hypercall for remote TLB flushes rather
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* than inter-processor interrupts
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*/
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#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
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/*
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* Recommend using MSRs for accessing APIC registers
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* EOI, ICR and TPR rather than their memory-mapped counterparts
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*/
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#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
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/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
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#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
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/*
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* Recommend using relaxed timing for this partition. If used,
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* the VM should disable any watchdog timeouts that rely on the
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* timely delivery of external interrupts
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*/
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#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
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-
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/*
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* Virtual APIC support
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*/
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#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9)
151
-
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/* Recommend using the newer ExProcessorMasks interface */
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#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11)
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/*
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* Crash notification flag.
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*/
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#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
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/* MSR used to identify the guest OS. */
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#define HV_X64_MSR_GUEST_OS_ID 0x40000000
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/* MSR used to setup pages used to communicate with the hypervisor. */
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#define HV_X64_MSR_HYPERCALL 0x40000001
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/* MSR used to provide vcpu index */
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#define HV_X64_MSR_VP_INDEX 0x40000002
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/* MSR used to reset the guest OS. */
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#define HV_X64_MSR_RESET 0x40000003
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172
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/* MSR used to provide vcpu runtime in 100ns units */
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#define HV_X64_MSR_VP_RUNTIME 0x40000010
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175
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/* MSR used to read the per-partition time reference counter */
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
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178
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/* MSR used to retrieve the TSC frequency */
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
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-
181
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/* MSR used to retrieve the local APIC timer frequency */
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#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
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184
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/* Define the virtual APIC registers */
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#define HV_X64_MSR_EOI 0x40000070
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#define HV_X64_MSR_ICR 0x40000071
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#define HV_X64_MSR_TPR 0x40000072
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#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
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/* Define synthetic interrupt controller model specific registers. */
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#define HV_X64_MSR_SCONTROL 0x40000080
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#define HV_X64_MSR_SVERSION 0x40000081
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#define HV_X64_MSR_SIEFP 0x40000082
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#define HV_X64_MSR_SIMP 0x40000083
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#define HV_X64_MSR_EOM 0x40000084
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#define HV_X64_MSR_SINT0 0x40000090
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#define HV_X64_MSR_SINT1 0x40000091
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#define HV_X64_MSR_SINT2 0x40000092
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#define HV_X64_MSR_SINT3 0x40000093
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#define HV_X64_MSR_SINT4 0x40000094
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#define HV_X64_MSR_SINT5 0x40000095
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#define HV_X64_MSR_SINT6 0x40000096
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#define HV_X64_MSR_SINT7 0x40000097
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#define HV_X64_MSR_SINT8 0x40000098
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#define HV_X64_MSR_SINT9 0x40000099
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#define HV_X64_MSR_SINT10 0x4000009A
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#define HV_X64_MSR_SINT11 0x4000009B
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#define HV_X64_MSR_SINT12 0x4000009C
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#define HV_X64_MSR_SINT13 0x4000009D
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#define HV_X64_MSR_SINT14 0x4000009E
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#define HV_X64_MSR_SINT15 0x4000009F
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/*
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* Synthetic Timer MSRs. Four timers per vcpu.
215
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*/
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#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
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#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
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#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
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#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
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#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
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#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
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#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
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#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
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/* Hyper-V guest crash notification MSR's */
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#define HV_X64_MSR_CRASH_P0 0x40000100
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#define HV_X64_MSR_CRASH_P1 0x40000101
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#define HV_X64_MSR_CRASH_P2 0x40000102
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#define HV_X64_MSR_CRASH_P3 0x40000103
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#define HV_X64_MSR_CRASH_P4 0x40000104
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#define HV_X64_MSR_CRASH_CTL 0x40000105
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#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63)
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#define HV_X64_MSR_CRASH_PARAMS \
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(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
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#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
237
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#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
238
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#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
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(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
240
-
241
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/* Declare the various hypercall operations. */
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
243
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
244
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#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
245
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
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#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
247
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#define HVCALL_POST_MESSAGE 0x005c
248
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#define HVCALL_SIGNAL_EVENT 0x005d
249
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250
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
251
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
252
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#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
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(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
254
-
255
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#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
256
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#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
257
-
258
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#define HV_PROCESSOR_POWER_STATE_C0 0
259
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#define HV_PROCESSOR_POWER_STATE_C1 1
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#define HV_PROCESSOR_POWER_STATE_C2 2
261
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#define HV_PROCESSOR_POWER_STATE_C3 3
262
-
263
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#define HV_FLUSH_ALL_PROCESSORS BIT(0)
264
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#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
265
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#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
266
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#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
267
-
268
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enum HV_GENERIC_SET_FORMAT {
269
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HV_GENERIC_SET_SPARCE_4K,
270
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HV_GENERIC_SET_ALL,
271
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};
272
-
273
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/* hypercall status code */
274
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#define HV_STATUS_SUCCESS 0
275
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#define HV_STATUS_INVALID_HYPERCALL_CODE 2
276
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#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
277
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#define HV_STATUS_INVALID_ALIGNMENT 4
278
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#define HV_STATUS_INSUFFICIENT_MEMORY 11
279
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#define HV_STATUS_INVALID_CONNECTION_ID 18
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#define HV_STATUS_INSUFFICIENT_BUFFERS 19
281
-
282
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typedef struct _HV_REFERENCE_TSC_PAGE {
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uint32_t tsc_sequence;
284
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uint32_t res1;
285
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uint64_t tsc_scale;
286
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int64_t tsc_offset;
287
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} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
288
-
289
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/* Define the number of synthetic interrupt sources. */
290
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#define HV_SYNIC_SINT_COUNT (16)
291
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/* Define the expected SynIC version. */
292
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#define HV_SYNIC_VERSION_1 (0x1)
293
-
294
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#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
295
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#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
296
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#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
297
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#define HV_SYNIC_SINT_MASKED (1ULL << 16)
298
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#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
299
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#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
300
-
301
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#define HV_SYNIC_STIMER_COUNT (4)
302
-
303
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/* Define synthetic interrupt controller message constants. */
304
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#define HV_MESSAGE_SIZE (256)
305
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#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
306
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#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
307
-
308
-
/* Define hypervisor message types. */
309
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enum hv_message_type {
310
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HVMSG_NONE = 0x00000000,
311
-
312
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/* Memory access messages. */
313
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HVMSG_UNMAPPED_GPA = 0x80000000,
314
-
HVMSG_GPA_INTERCEPT = 0x80000001,
315
-
316
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/* Timer notification messages. */
317
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HVMSG_TIMER_EXPIRED = 0x80000010,
318
-
319
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/* Error messages. */
320
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HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
321
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HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
322
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HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
323
-
324
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/* Trace buffer complete messages. */
325
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HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
326
-
327
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/* Platform-specific processor intercept messages. */
328
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HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
329
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HVMSG_X64_MSR_INTERCEPT = 0x80010001,
330
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HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
331
-
HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
332
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HVMSG_X64_APIC_EOI = 0x80010004,
333
-
HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
334
-
};
335
-
336
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/* Define synthetic interrupt controller message flags. */
337
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union hv_message_flags {
338
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uint8_t asu8;
339
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struct {
340
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uint8_t msg_pending:1;
341
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uint8_t reserved:7;
342
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};
343
-
};
344
-
345
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/* Define port identifier type. */
346
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union hv_port_id {
347
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uint32_t asu32;
348
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struct {
349
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uint32_t id:24;
350
-
uint32_t reserved:8;
351
-
} u;
352
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};
353
-
354
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/* Define synthetic interrupt controller message header. */
355
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struct hv_message_header {
356
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uint32_t message_type;
357
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uint8_t payload_size;
358
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union hv_message_flags message_flags;
359
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uint8_t reserved[2];
360
-
union {
361
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uint64_t sender;
362
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union hv_port_id port;
363
-
};
364
-
};
365
-
366
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/* Define synthetic interrupt controller message format. */
367
-
struct hv_message {
368
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struct hv_message_header header;
369
-
union {
370
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uint64_t payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
371
-
} u;
372
-
};
373
-
374
-
/* Define the synthetic interrupt message page layout. */
375
-
struct hv_message_page {
376
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struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
377
-
};
378
-
379
-
/* Define timer message payload structure. */
380
-
struct hv_timer_message_payload {
381
-
uint32_t timer_index;
382
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uint32_t reserved;
383
-
uint64_t expiration_time; /* When the timer expired */
384
-
uint64_t delivery_time; /* When the message was delivered */
385
-
};
386
-
387
-
#define HV_STIMER_ENABLE (1ULL << 0)
388
-
#define HV_STIMER_PERIODIC (1ULL << 1)
389
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#define HV_STIMER_LAZY (1ULL << 2)
390
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#define HV_STIMER_AUTOENABLE (1ULL << 3)
391
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#define HV_STIMER_SINT(config) (uint8_t)(((config) >> 16) & 0x0F)
392
-
393
-
#endif
1
+
/* this is a temporary placeholder until kvm_para.h stops including it */
+2
include/standard-headers/linux/input-event-codes.h
+2
include/standard-headers/linux/input-event-codes.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
/*
2
3
* Input event codes
3
4
*
···
406
407
#define BTN_TOOL_MOUSE 0x146
407
408
#define BTN_TOOL_LENS 0x147
408
409
#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
410
+
#define BTN_STYLUS3 0x149
409
411
#define BTN_TOUCH 0x14a
410
412
#define BTN_STYLUS 0x14b
411
413
#define BTN_STYLUS2 0x14c
+1
include/standard-headers/linux/input.h
+1
include/standard-headers/linux/input.h
+29
-16
include/standard-headers/linux/pci_regs.h
+29
-16
include/standard-headers/linux/pci_regs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
/*
2
3
* pci_regs.h
3
4
*
···
746
747
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
747
748
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
748
749
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
750
+
#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
749
751
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
750
752
751
753
/* Virtual Channel */
···
939
941
#define PCI_SATA_SIZEOF_LONG 16
940
942
941
943
/* Resizable BARs */
944
+
#define PCI_REBAR_CAP 4 /* capability register */
945
+
#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */
942
946
#define PCI_REBAR_CTRL 8 /* control register */
943
-
#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
944
-
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
947
+
#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */
948
+
#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */
949
+
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */
950
+
#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */
945
951
946
952
/* Dynamic Power Allocation */
947
953
#define PCI_DPA_CAP 4 /* capability register */
···
960
966
961
967
/* Downstream Port Containment */
962
968
#define PCI_EXP_DPC_CAP 4 /* DPC Capability */
969
+
#define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */
963
970
#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
964
971
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
965
972
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
···
995
1002
#define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */
996
1003
#define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */
997
1004
998
-
/* L1 PM Substates */
999
-
#define PCI_L1SS_CAP 4 /* capability register */
1000
-
#define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */
1001
-
#define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */
1002
-
#define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */
1003
-
#define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */
1004
-
#define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */
1005
-
#define PCI_L1SS_CTL1 8 /* Control Register 1 */
1006
-
#define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */
1007
-
#define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */
1008
-
#define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */
1009
-
#define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */
1010
-
#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F
1011
-
#define PCI_L1SS_CTL2 0xC /* Control Register 2 */
1005
+
/* ASPM L1 PM Substates */
1006
+
#define PCI_L1SS_CAP 0x04 /* Capabilities Register */
1007
+
#define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1008
+
#define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1009
+
#define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */
1010
+
#define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */
1011
+
#define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */
1012
+
#define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */
1013
+
#define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */
1014
+
#define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */
1015
+
#define PCI_L1SS_CTL1 0x08 /* Control 1 Register */
1016
+
#define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1017
+
#define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1018
+
#define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */
1019
+
#define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */
1020
+
#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f
1021
+
#define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */
1022
+
#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */
1023
+
#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
1024
+
#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
1012
1025
1013
1026
#endif /* LINUX_PCI_REGS_H */
+8
linux-headers/asm-arm/kvm.h
+8
linux-headers/asm-arm/kvm.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
/*
2
3
* Copyright (C) 2012 - Virtual Open Systems and Columbia University
3
4
* Author: Christoffer Dall <c.dall@virtualopensystems.com>
···
151
152
(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
152
153
#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
153
154
155
+
/* PL1 Physical Timer Registers */
156
+
#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
157
+
#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
158
+
#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
159
+
160
+
/* Virtual Timer Registers */
154
161
#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
155
162
#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
156
163
#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
···
215
222
#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
216
223
#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
217
224
#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
225
+
#define KVM_DEV_ARM_ITS_CTRL_RESET 4
218
226
219
227
/* KVM_IRQ_LINE irq field index values */
220
228
#define KVM_ARM_IRQ_TYPE_SHIFT 24
+1
linux-headers/asm-arm/kvm_para.h
+1
linux-headers/asm-arm/kvm_para.h
+2
linux-headers/asm-arm/unistd.h
+2
linux-headers/asm-arm/unistd.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
/*
2
3
* arch/arm/include/asm/unistd.h
3
4
*
···
35
36
#define __ARM_NR_usr26 (__ARM_NR_BASE+3)
36
37
#define __ARM_NR_usr32 (__ARM_NR_BASE+4)
37
38
#define __ARM_NR_set_tls (__ARM_NR_BASE+5)
39
+
#define __ARM_NR_get_tls (__ARM_NR_BASE+6)
38
40
39
41
#endif /* __ASM_ARM_UNISTD_H */
+8
linux-headers/asm-arm64/kvm.h
+8
linux-headers/asm-arm64/kvm.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
/*
2
3
* Copyright (C) 2012,2013 - ARM Ltd
3
4
* Author: Marc Zyngier <marc.zyngier@arm.com>
···
195
196
196
197
#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
197
198
199
+
/* Physical Timer EL0 Registers */
200
+
#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
201
+
#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
202
+
#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
203
+
204
+
/* EL0 Virtual Timer Registers */
198
205
#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
199
206
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
200
207
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
···
227
234
#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
228
235
#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
229
236
#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
237
+
#define KVM_DEV_ARM_ITS_CTRL_RESET 4
230
238
231
239
/* Device Control API on vcpu fd */
232
240
#define KVM_ARM_VCPU_PMU_V3_CTRL 0
+1
linux-headers/asm-arm64/unistd.h
+1
linux-headers/asm-arm64/unistd.h
+1
linux-headers/asm-powerpc/epapr_hcalls.h
+1
linux-headers/asm-powerpc/epapr_hcalls.h
+1
linux-headers/asm-powerpc/kvm.h
+1
linux-headers/asm-powerpc/kvm.h
+1
linux-headers/asm-powerpc/kvm_para.h
+1
linux-headers/asm-powerpc/kvm_para.h
+1
linux-headers/asm-powerpc/unistd.h
+1
linux-headers/asm-powerpc/unistd.h
+1
linux-headers/asm-s390/kvm.h
+1
linux-headers/asm-s390/kvm.h
+1
linux-headers/asm-s390/kvm_para.h
+1
linux-headers/asm-s390/kvm_para.h
+3
-1
linux-headers/asm-s390/unistd.h
+3
-1
linux-headers/asm-s390/unistd.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
/*
2
3
* S390 version
3
4
*
···
315
316
#define __NR_pwritev2 377
316
317
#define __NR_s390_guarded_storage 378
317
318
#define __NR_statx 379
318
-
#define NR_syscalls 380
319
+
#define __NR_s390_sthyi 380
320
+
#define NR_syscalls 381
319
321
320
322
/*
321
323
* There are some system calls that are not present on 64 bit, some
+1
linux-headers/asm-x86/kvm.h
+1
linux-headers/asm-x86/kvm.h
+1
-1
linux-headers/asm-x86/kvm_para.h
+1
-1
linux-headers/asm-x86/kvm_para.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
#ifndef _ASM_X86_KVM_PARA_H
2
3
#define _ASM_X86_KVM_PARA_H
3
4
···
108
109
#define KVM_PV_EOI_MASK (0x1 << KVM_PV_EOI_BIT)
109
110
#define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK
110
111
#define KVM_PV_EOI_DISABLED 0x0
111
-
112
112
113
113
#endif /* _ASM_X86_KVM_PARA_H */
+1
linux-headers/asm-x86/unistd.h
+1
linux-headers/asm-x86/unistd.h
+2
linux-headers/linux/kvm.h
+2
linux-headers/linux/kvm.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
2
#ifndef __LINUX_KVM_H
2
3
#define __LINUX_KVM_H
3
4
···
930
931
#define KVM_CAP_PPC_SMT_POSSIBLE 147
931
932
#define KVM_CAP_HYPERV_SYNIC2 148
932
933
#define KVM_CAP_HYPERV_VP_INDEX 149
934
+
#define KVM_CAP_S390_AIS_MIGRATION 150
933
935
934
936
#ifdef KVM_CAP_IRQ_ROUTING
935
937
+1
linux-headers/linux/kvm_para.h
+1
linux-headers/linux/kvm_para.h
+1
linux-headers/linux/psci.h
+1
linux-headers/linux/psci.h
+1
linux-headers/linux/userfaultfd.h
+1
linux-headers/linux/userfaultfd.h
+1
linux-headers/linux/vfio.h
+1
linux-headers/linux/vfio.h
+1
linux-headers/linux/vfio_ccw.h
+1
linux-headers/linux/vfio_ccw.h