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ppc: Add support for 'mffsce' instruction

ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.

'mffsce' is identical to 'mffs', except that it also clears the exception
enable bits in the FPSCR.

On CPUs without support for 'mffsce' (below ISA 3.0), the
instruction will execute identically to 'mffs'.

Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

authored by

Paul A. Clarke and committed by
David Gibson bc7a45ab a2735cf4

+32
+30
target/ppc/translate/fp-impl.inc.c
··· 639 639 tcg_temp_free_i64(t0); 640 640 } 641 641 642 + /* mffsce */ 643 + static void gen_mffsce(DisasContext *ctx) 644 + { 645 + TCGv_i64 t0; 646 + TCGv_i32 mask; 647 + 648 + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { 649 + return gen_mffs(ctx); 650 + } 651 + 652 + if (unlikely(!ctx->fpu_enabled)) { 653 + gen_exception(ctx, POWERPC_EXCP_FPU); 654 + return; 655 + } 656 + 657 + t0 = tcg_temp_new_i64(); 658 + 659 + gen_reset_fpstatus(); 660 + tcg_gen_extu_tl_i64(t0, cpu_fpscr); 661 + set_fpr(rD(ctx->opcode), t0); 662 + 663 + /* Clear exception enable bits in the FPSCR. */ 664 + tcg_gen_andi_i64(t0, t0, ~FP_ENABLES); 665 + mask = tcg_const_i32(0x0003); 666 + gen_helper_store_fpscr(cpu_env, t0, mask); 667 + 668 + tcg_temp_free_i32(mask); 669 + tcg_temp_free_i64(t0); 670 + } 671 + 642 672 static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1) 643 673 { 644 674 TCGv_i64 t0 = tcg_temp_new_i64();
+2
target/ppc/translate/fp-ops.inc.c
··· 105 105 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), 106 106 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), 107 107 GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE), 108 + GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT, 109 + PPC2_ISA300), 108 110 GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT, 109 111 PPC2_ISA300), 110 112 GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,