jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
ppc: Add support for 'mffscrn','mffscrni' instructions
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffscrn' and 'mffscrni' instructions.
'mffscrn' and 'mffscrni' are similar to 'mffsl', except they do not return
the status bits (FI, FR, FPRF) and they also set the rounding mode in the
FPSCR.
On CPUs without support for 'mffscrn'/'mffscrni' (below ISA 3.0), the
instructions will execute identically to 'mffs'.
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Message-Id: <1568817081-1345-1-git-send-email-pc@us.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
authored by
Paul A. Clarke
and committed by
David Gibson
a2735cf4
4c3539d4
+84
-3
+8
-1
target/ppc/cpu.h
+8
-1
target/ppc/cpu.h
···
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/*****************************************************************************/
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/* Floating point status and control register */
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+
#define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
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+
#define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
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+
#define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
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#define FPSCR_FX 31 /* Floating-point exception summary */
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#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
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#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
···
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#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
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#define FPSCR_RN1 1
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#define FPSCR_RN0 0 /* Floating-point rounding control */
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#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
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#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
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#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
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#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
···
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#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
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0x1F)
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+
#define FP_DRN2 (1ull << FPSCR_DRN2)
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#define FP_DRN1 (1ull << FPSCR_DRN1)
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#define FP_DRN0 (1ull << FPSCR_DRN0)
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#define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
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#define FP_FX (1ull << FPSCR_FX)
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#define FP_FEX (1ull << FPSCR_FEX)
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#define FP_VX (1ull << FPSCR_VX)
···
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#define FP_RN0 (1ull << FPSCR_RN0)
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#define FP_RN (FP_RN1 | FP_RN0)
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-
#define FP_MODE FP_RN
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#define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
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#define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
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+1
-1
target/ppc/dfp_helper.c
+1
-1
target/ppc/dfp_helper.c
+3
target/ppc/internal.h
+3
target/ppc/internal.h
+68
-1
target/ppc/translate/fp-impl.inc.c
+68
-1
target/ppc/translate/fp-impl.inc.c
···
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gen_reset_fpstatus();
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tcg_gen_extu_tl_i64(t0, cpu_fpscr);
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/* Mask everything except mode, status, and enables. */
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-
tcg_gen_andi_i64(t0, t0, FP_MODE | FP_STATUS | FP_ENABLES);
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tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
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set_fpr(rD(ctx->opcode), t0);
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tcg_temp_free_i64(t0);
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+
}
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+
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+
static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
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+
{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i32 mask = tcg_const_i32(0x0001);
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+
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gen_reset_fpstatus();
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tcg_gen_extu_tl_i64(t0, cpu_fpscr);
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tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN);
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set_fpr(rD(ctx->opcode), t0);
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+
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/* Mask FPSCR value to clear RN. */
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tcg_gen_andi_i64(t0, t0, ~FP_RN);
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+
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/* Merge RN into FPSCR value. */
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tcg_gen_or_i64(t0, t0, t1);
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+
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gen_helper_store_fpscr(cpu_env, t0, mask);
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+
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tcg_temp_free_i32(mask);
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tcg_temp_free_i64(t0);
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}
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+
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/* mffscrn */
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+
static void gen_mffscrn(DisasContext *ctx)
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+
{
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TCGv_i64 t1;
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+
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if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
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+
return gen_mffs(ctx);
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+
}
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+
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+
if (unlikely(!ctx->fpu_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_FPU);
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+
return;
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}
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+
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t1 = tcg_temp_new_i64();
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get_fpr(t1, rB(ctx->opcode));
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/* Mask FRB to get just RN. */
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tcg_gen_andi_i64(t1, t1, FP_RN);
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+
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gen_helper_mffscrn(ctx, t1);
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+
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tcg_temp_free_i64(t1);
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}
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+
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/* mffscrni */
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static void gen_mffscrni(DisasContext *ctx)
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{
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TCGv_i64 t1;
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+
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if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
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return gen_mffs(ctx);
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}
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+
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if (unlikely(!ctx->fpu_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_FPU);
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return;
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}
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+
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t1 = tcg_const_i64((uint64_t)RM(ctx->opcode));
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gen_helper_mffscrn(ctx, t1);
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+
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tcg_temp_free_i64(t1);
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}
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/* mtfsb0 */
+4
target/ppc/translate/fp-ops.inc.c
+4
target/ppc/translate/fp-ops.inc.c
···
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GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
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GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
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PPC2_ISA300),
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GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
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+
PPC_NONE),
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GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT,
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PPC_NONE),
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GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
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GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
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GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),