target/xtensa: add linux-user support

+1

default-configs/xtensa-linux-user.mak

··· 1 + # Default configuration for xtensa-linux-user

+1

default-configs/xtensaeb-linux-user.mak

··· 1 + # Default configuration for xtensa-linux-user

+58

linux-user/elfload.c

··· 1341 1341 1342 1342 #endif /* TARGET_HPPA */ 1343 1343 1344 + #ifdef TARGET_XTENSA 1345 + 1346 + #define ELF_START_MMAP 0x20000000 1347 + 1348 + #define ELF_CLASS ELFCLASS32 1349 + #define ELF_ARCH EM_XTENSA 1350 + 1351 + static inline void init_thread(struct target_pt_regs *regs, 1352 + struct image_info *infop) 1353 + { 1354 + regs->windowbase = 0; 1355 + regs->windowstart = 1; 1356 + regs->areg[1] = infop->start_stack; 1357 + regs->pc = infop->entry; 1358 + } 1359 + 1360 + /* See linux kernel: arch/xtensa/include/asm/elf.h. */ 1361 + #define ELF_NREG 128 1362 + typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; 1363 + 1364 + enum { 1365 + TARGET_REG_PC, 1366 + TARGET_REG_PS, 1367 + TARGET_REG_LBEG, 1368 + TARGET_REG_LEND, 1369 + TARGET_REG_LCOUNT, 1370 + TARGET_REG_SAR, 1371 + TARGET_REG_WINDOWSTART, 1372 + TARGET_REG_WINDOWBASE, 1373 + TARGET_REG_THREADPTR, 1374 + TARGET_REG_AR0 = 64, 1375 + }; 1376 + 1377 + static void elf_core_copy_regs(target_elf_gregset_t *regs, 1378 + const CPUXtensaState *env) 1379 + { 1380 + unsigned i; 1381 + 1382 + (*regs)[TARGET_REG_PC] = tswapreg(env->pc); 1383 + (*regs)[TARGET_REG_PS] = tswapreg(env->sregs[PS] & ~PS_EXCM); 1384 + (*regs)[TARGET_REG_LBEG] = tswapreg(env->sregs[LBEG]); 1385 + (*regs)[TARGET_REG_LEND] = tswapreg(env->sregs[LEND]); 1386 + (*regs)[TARGET_REG_LCOUNT] = tswapreg(env->sregs[LCOUNT]); 1387 + (*regs)[TARGET_REG_SAR] = tswapreg(env->sregs[SAR]); 1388 + (*regs)[TARGET_REG_WINDOWSTART] = tswapreg(env->sregs[WINDOW_START]); 1389 + (*regs)[TARGET_REG_WINDOWBASE] = tswapreg(env->sregs[WINDOW_BASE]); 1390 + (*regs)[TARGET_REG_THREADPTR] = tswapreg(env->uregs[THREADPTR]); 1391 + xtensa_sync_phys_from_window((CPUXtensaState *)env); 1392 + for (i = 0; i < env->config->nareg; ++i) { 1393 + (*regs)[TARGET_REG_AR0 + i] = tswapreg(env->phys_regs[i]); 1394 + } 1395 + } 1396 + 1397 + #define USE_ELF_CORE_DUMP 1398 + #define ELF_EXEC_PAGESIZE 4096 1399 + 1400 + #endif /* TARGET_XTENSA */ 1401 + 1344 1402 #ifndef ELF_PLATFORM 1345 1403 #define ELF_PLATFORM (NULL) 1346 1404 #endif

+245

linux-user/main.c

··· 3930 3930 3931 3931 #endif /* TARGET_HPPA */ 3932 3932 3933 + #ifdef TARGET_XTENSA 3934 + 3935 + static void xtensa_rfw(CPUXtensaState *env) 3936 + { 3937 + xtensa_restore_owb(env); 3938 + env->pc = env->sregs[EPC1]; 3939 + } 3940 + 3941 + static void xtensa_rfwu(CPUXtensaState *env) 3942 + { 3943 + env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]); 3944 + xtensa_rfw(env); 3945 + } 3946 + 3947 + static void xtensa_rfwo(CPUXtensaState *env) 3948 + { 3949 + env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]); 3950 + xtensa_rfw(env); 3951 + } 3952 + 3953 + static void xtensa_overflow4(CPUXtensaState *env) 3954 + { 3955 + put_user_ual(env->regs[0], env->regs[5] - 16); 3956 + put_user_ual(env->regs[1], env->regs[5] - 12); 3957 + put_user_ual(env->regs[2], env->regs[5] - 8); 3958 + put_user_ual(env->regs[3], env->regs[5] - 4); 3959 + xtensa_rfwo(env); 3960 + } 3961 + 3962 + static void xtensa_underflow4(CPUXtensaState *env) 3963 + { 3964 + get_user_ual(env->regs[0], env->regs[5] - 16); 3965 + get_user_ual(env->regs[1], env->regs[5] - 12); 3966 + get_user_ual(env->regs[2], env->regs[5] - 8); 3967 + get_user_ual(env->regs[3], env->regs[5] - 4); 3968 + xtensa_rfwu(env); 3969 + } 3970 + 3971 + static void xtensa_overflow8(CPUXtensaState *env) 3972 + { 3973 + put_user_ual(env->regs[0], env->regs[9] - 16); 3974 + get_user_ual(env->regs[0], env->regs[1] - 12); 3975 + put_user_ual(env->regs[1], env->regs[9] - 12); 3976 + put_user_ual(env->regs[2], env->regs[9] - 8); 3977 + put_user_ual(env->regs[3], env->regs[9] - 4); 3978 + put_user_ual(env->regs[4], env->regs[0] - 32); 3979 + put_user_ual(env->regs[5], env->regs[0] - 28); 3980 + put_user_ual(env->regs[6], env->regs[0] - 24); 3981 + put_user_ual(env->regs[7], env->regs[0] - 20); 3982 + xtensa_rfwo(env); 3983 + } 3984 + 3985 + static void xtensa_underflow8(CPUXtensaState *env) 3986 + { 3987 + get_user_ual(env->regs[0], env->regs[9] - 16); 3988 + get_user_ual(env->regs[1], env->regs[9] - 12); 3989 + get_user_ual(env->regs[2], env->regs[9] - 8); 3990 + get_user_ual(env->regs[7], env->regs[1] - 12); 3991 + get_user_ual(env->regs[3], env->regs[9] - 4); 3992 + get_user_ual(env->regs[4], env->regs[7] - 32); 3993 + get_user_ual(env->regs[5], env->regs[7] - 28); 3994 + get_user_ual(env->regs[6], env->regs[7] - 24); 3995 + get_user_ual(env->regs[7], env->regs[7] - 20); 3996 + xtensa_rfwu(env); 3997 + } 3998 + 3999 + static void xtensa_overflow12(CPUXtensaState *env) 4000 + { 4001 + put_user_ual(env->regs[0], env->regs[13] - 16); 4002 + get_user_ual(env->regs[0], env->regs[1] - 12); 4003 + put_user_ual(env->regs[1], env->regs[13] - 12); 4004 + put_user_ual(env->regs[2], env->regs[13] - 8); 4005 + put_user_ual(env->regs[3], env->regs[13] - 4); 4006 + put_user_ual(env->regs[4], env->regs[0] - 48); 4007 + put_user_ual(env->regs[5], env->regs[0] - 44); 4008 + put_user_ual(env->regs[6], env->regs[0] - 40); 4009 + put_user_ual(env->regs[7], env->regs[0] - 36); 4010 + put_user_ual(env->regs[8], env->regs[0] - 32); 4011 + put_user_ual(env->regs[9], env->regs[0] - 28); 4012 + put_user_ual(env->regs[10], env->regs[0] - 24); 4013 + put_user_ual(env->regs[11], env->regs[0] - 20); 4014 + xtensa_rfwo(env); 4015 + } 4016 + 4017 + static void xtensa_underflow12(CPUXtensaState *env) 4018 + { 4019 + get_user_ual(env->regs[0], env->regs[13] - 16); 4020 + get_user_ual(env->regs[1], env->regs[13] - 12); 4021 + get_user_ual(env->regs[2], env->regs[13] - 8); 4022 + get_user_ual(env->regs[11], env->regs[1] - 12); 4023 + get_user_ual(env->regs[3], env->regs[13] - 4); 4024 + get_user_ual(env->regs[4], env->regs[11] - 48); 4025 + get_user_ual(env->regs[5], env->regs[11] - 44); 4026 + get_user_ual(env->regs[6], env->regs[11] - 40); 4027 + get_user_ual(env->regs[7], env->regs[11] - 36); 4028 + get_user_ual(env->regs[8], env->regs[11] - 32); 4029 + get_user_ual(env->regs[9], env->regs[11] - 28); 4030 + get_user_ual(env->regs[10], env->regs[11] - 24); 4031 + get_user_ual(env->regs[11], env->regs[11] - 20); 4032 + xtensa_rfwu(env); 4033 + } 4034 + 4035 + void cpu_loop(CPUXtensaState *env) 4036 + { 4037 + CPUState *cs = CPU(xtensa_env_get_cpu(env)); 4038 + target_siginfo_t info; 4039 + abi_ulong ret; 4040 + int trapnr; 4041 + 4042 + while (1) { 4043 + cpu_exec_start(cs); 4044 + trapnr = cpu_exec(cs); 4045 + cpu_exec_end(cs); 4046 + process_queued_cpu_work(cs); 4047 + 4048 + env->sregs[PS] &= ~PS_EXCM; 4049 + switch (trapnr) { 4050 + case EXCP_INTERRUPT: 4051 + break; 4052 + 4053 + case EXC_WINDOW_OVERFLOW4: 4054 + xtensa_overflow4(env); 4055 + break; 4056 + case EXC_WINDOW_UNDERFLOW4: 4057 + xtensa_underflow4(env); 4058 + break; 4059 + case EXC_WINDOW_OVERFLOW8: 4060 + xtensa_overflow8(env); 4061 + break; 4062 + case EXC_WINDOW_UNDERFLOW8: 4063 + xtensa_underflow8(env); 4064 + break; 4065 + case EXC_WINDOW_OVERFLOW12: 4066 + xtensa_overflow12(env); 4067 + break; 4068 + case EXC_WINDOW_UNDERFLOW12: 4069 + xtensa_underflow12(env); 4070 + break; 4071 + 4072 + case EXC_USER: 4073 + switch (env->sregs[EXCCAUSE]) { 4074 + case ILLEGAL_INSTRUCTION_CAUSE: 4075 + case PRIVILEGED_CAUSE: 4076 + info.si_signo = TARGET_SIGILL; 4077 + info.si_errno = 0; 4078 + info.si_code = 4079 + env->sregs[EXCCAUSE] == ILLEGAL_INSTRUCTION_CAUSE ? 4080 + TARGET_ILL_ILLOPC : TARGET_ILL_PRVOPC; 4081 + info._sifields._sigfault._addr = env->sregs[EPC1]; 4082 + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 4083 + break; 4084 + 4085 + case SYSCALL_CAUSE: 4086 + env->pc += 3; 4087 + ret = do_syscall(env, env->regs[2], 4088 + env->regs[6], env->regs[3], 4089 + env->regs[4], env->regs[5], 4090 + env->regs[8], env->regs[9], 0, 0); 4091 + switch (ret) { 4092 + default: 4093 + env->regs[2] = ret; 4094 + break; 4095 + 4096 + case -TARGET_ERESTARTSYS: 4097 + case -TARGET_QEMU_ESIGRETURN: 4098 + break; 4099 + } 4100 + break; 4101 + 4102 + case ALLOCA_CAUSE: 4103 + env->sregs[PS] = deposit32(env->sregs[PS], 4104 + PS_OWB_SHIFT, 4105 + PS_OWB_LEN, 4106 + env->sregs[WINDOW_BASE]); 4107 + 4108 + switch (env->regs[0] & 0xc0000000) { 4109 + case 0x00000000: 4110 + case 0x40000000: 4111 + xtensa_rotate_window(env, -1); 4112 + xtensa_underflow4(env); 4113 + break; 4114 + 4115 + case 0x80000000: 4116 + xtensa_rotate_window(env, -2); 4117 + xtensa_underflow8(env); 4118 + break; 4119 + 4120 + case 0xc0000000: 4121 + xtensa_rotate_window(env, -3); 4122 + xtensa_underflow12(env); 4123 + break; 4124 + } 4125 + break; 4126 + 4127 + case INTEGER_DIVIDE_BY_ZERO_CAUSE: 4128 + info.si_signo = TARGET_SIGFPE; 4129 + info.si_errno = 0; 4130 + info.si_code = TARGET_FPE_INTDIV; 4131 + info._sifields._sigfault._addr = env->sregs[EPC1]; 4132 + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 4133 + break; 4134 + 4135 + case LOAD_PROHIBITED_CAUSE: 4136 + case STORE_PROHIBITED_CAUSE: 4137 + info.si_signo = TARGET_SIGSEGV; 4138 + info.si_errno = 0; 4139 + info.si_code = TARGET_SEGV_ACCERR; 4140 + info._sifields._sigfault._addr = env->sregs[EXCVADDR]; 4141 + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 4142 + break; 4143 + 4144 + default: 4145 + fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]); 4146 + g_assert_not_reached(); 4147 + } 4148 + break; 4149 + case EXCP_DEBUG: 4150 + trapnr = gdb_handlesig(cs, TARGET_SIGTRAP); 4151 + if (trapnr) { 4152 + info.si_signo = trapnr; 4153 + info.si_errno = 0; 4154 + info.si_code = TARGET_TRAP_BRKPT; 4155 + queue_signal(env, trapnr, QEMU_SI_FAULT, &info); 4156 + } 4157 + break; 4158 + case EXC_DEBUG: 4159 + default: 4160 + fprintf(stderr, "trapnr = %d\n", trapnr); 4161 + g_assert_not_reached(); 4162 + } 4163 + process_pending_signals(env); 4164 + } 4165 + } 4166 + 4167 + #endif /* TARGET_XTENSA */ 4168 + 3933 4169 __thread CPUState *thread_cpu; 3934 4170 3935 4171 bool qemu_cpu_is_self(CPUState *cpu) ··· 4969 5205 } 4970 5206 env->iaoq_f = regs->iaoq[0]; 4971 5207 env->iaoq_b = regs->iaoq[1]; 5208 + } 5209 + #elif defined(TARGET_XTENSA) 5210 + { 5211 + int i; 5212 + for (i = 0; i < 16; ++i) { 5213 + env->regs[i] = regs->areg[i]; 5214 + } 5215 + env->sregs[WINDOW_START] = regs->windowstart; 5216 + env->pc = regs->pc; 4972 5217 } 4973 5218 #else 4974 5219 #error unsupported target CPU

+255 -1

linux-user/signal.c

··· 7051 7051 return -TARGET_QEMU_ESIGRETURN; 7052 7052 } 7053 7053 7054 + #elif defined(TARGET_XTENSA) 7055 + 7056 + struct target_sigcontext { 7057 + abi_ulong sc_pc; 7058 + abi_ulong sc_ps; 7059 + abi_ulong sc_lbeg; 7060 + abi_ulong sc_lend; 7061 + abi_ulong sc_lcount; 7062 + abi_ulong sc_sar; 7063 + abi_ulong sc_acclo; 7064 + abi_ulong sc_acchi; 7065 + abi_ulong sc_a[16]; 7066 + abi_ulong sc_xtregs; 7067 + }; 7068 + 7069 + struct target_ucontext { 7070 + abi_ulong tuc_flags; 7071 + abi_ulong tuc_link; 7072 + target_stack_t tuc_stack; 7073 + struct target_sigcontext tuc_mcontext; 7074 + target_sigset_t tuc_sigmask; 7075 + }; 7076 + 7077 + struct target_rt_sigframe { 7078 + target_siginfo_t info; 7079 + struct target_ucontext uc; 7080 + /* TODO: xtregs */ 7081 + uint8_t retcode[6]; 7082 + abi_ulong window[4]; 7083 + }; 7084 + 7085 + static abi_ulong get_sigframe(struct target_sigaction *sa, 7086 + CPUXtensaState *env, 7087 + unsigned long framesize) 7088 + { 7089 + abi_ulong sp = env->regs[1]; 7090 + 7091 + /* This is the X/Open sanctioned signal stack switching. */ 7092 + if ((sa->sa_flags & TARGET_SA_ONSTACK) != 0 && !sas_ss_flags(sp)) { 7093 + sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size; 7094 + } 7095 + return (sp - framesize) & -16; 7096 + } 7097 + 7098 + static int flush_window_regs(CPUXtensaState *env) 7099 + { 7100 + const uint32_t nareg_mask = env->config->nareg - 1; 7101 + uint32_t wb = env->sregs[WINDOW_BASE]; 7102 + uint32_t ws = (xtensa_replicate_windowstart(env) >> (wb + 1)) & 7103 + ((1 << env->config->nareg / 4) - 1); 7104 + uint32_t d = ctz32(ws) + 1; 7105 + uint32_t sp; 7106 + abi_long ret = 0; 7107 + 7108 + wb += d; 7109 + ws >>= d; 7110 + 7111 + xtensa_sync_phys_from_window(env); 7112 + sp = env->phys_regs[(wb * 4 + 1) & nareg_mask]; 7113 + 7114 + while (ws && ret == 0) { 7115 + int d; 7116 + int i; 7117 + int idx; 7118 + 7119 + if (ws & 0x1) { 7120 + ws >>= 1; 7121 + d = 1; 7122 + } else if (ws & 0x2) { 7123 + ws >>= 2; 7124 + d = 2; 7125 + for (i = 0; i < 4; ++i) { 7126 + idx = (wb * 4 + 4 + i) & nareg_mask; 7127 + ret |= put_user_ual(env->phys_regs[idx], sp + (i - 12) * 4); 7128 + } 7129 + } else if (ws & 0x4) { 7130 + ws >>= 3; 7131 + d = 3; 7132 + for (i = 0; i < 8; ++i) { 7133 + idx = (wb * 4 + 4 + i) & nareg_mask; 7134 + ret |= put_user_ual(env->phys_regs[idx], sp + (i - 16) * 4); 7135 + } 7136 + } else { 7137 + g_assert_not_reached(); 7138 + } 7139 + sp = env->phys_regs[((wb + d) * 4 + 1) & nareg_mask]; 7140 + for (i = 0; i < 4; ++i) { 7141 + idx = (wb * 4 + i) & nareg_mask; 7142 + ret |= put_user_ual(env->phys_regs[idx], sp + (i - 4) * 4); 7143 + } 7144 + wb += d; 7145 + } 7146 + return ret == 0; 7147 + } 7148 + 7149 + static int setup_sigcontext(struct target_rt_sigframe *frame, 7150 + CPUXtensaState *env) 7151 + { 7152 + struct target_sigcontext *sc = &frame->uc.tuc_mcontext; 7153 + int i; 7154 + 7155 + __put_user(env->pc, &sc->sc_pc); 7156 + __put_user(env->sregs[PS], &sc->sc_ps); 7157 + __put_user(env->sregs[LBEG], &sc->sc_lbeg); 7158 + __put_user(env->sregs[LEND], &sc->sc_lend); 7159 + __put_user(env->sregs[LCOUNT], &sc->sc_lcount); 7160 + if (!flush_window_regs(env)) { 7161 + return 0; 7162 + } 7163 + for (i = 0; i < 16; ++i) { 7164 + __put_user(env->regs[i], sc->sc_a + i); 7165 + } 7166 + __put_user(0, &sc->sc_xtregs); 7167 + /* TODO: xtregs */ 7168 + return 1; 7169 + } 7170 + 7171 + static void setup_rt_frame(int sig, struct target_sigaction *ka, 7172 + target_siginfo_t *info, 7173 + target_sigset_t *set, CPUXtensaState *env) 7174 + { 7175 + abi_ulong frame_addr; 7176 + struct target_rt_sigframe *frame; 7177 + uint32_t ra; 7178 + int i; 7179 + 7180 + frame_addr = get_sigframe(ka, env, sizeof(*frame)); 7181 + trace_user_setup_rt_frame(env, frame_addr); 7182 + 7183 + if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { 7184 + goto give_sigsegv; 7185 + } 7186 + 7187 + if (ka->sa_flags & SA_SIGINFO) { 7188 + tswap_siginfo(&frame->info, info); 7189 + } 7190 + 7191 + __put_user(0, &frame->uc.tuc_flags); 7192 + __put_user(0, &frame->uc.tuc_link); 7193 + __put_user(target_sigaltstack_used.ss_sp, 7194 + &frame->uc.tuc_stack.ss_sp); 7195 + __put_user(sas_ss_flags(env->regs[1]), 7196 + &frame->uc.tuc_stack.ss_flags); 7197 + __put_user(target_sigaltstack_used.ss_size, 7198 + &frame->uc.tuc_stack.ss_size); 7199 + if (!setup_sigcontext(frame, env)) { 7200 + unlock_user_struct(frame, frame_addr, 0); 7201 + goto give_sigsegv; 7202 + } 7203 + for (i = 0; i < TARGET_NSIG_WORDS; ++i) { 7204 + __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); 7205 + } 7206 + 7207 + if (ka->sa_flags & TARGET_SA_RESTORER) { 7208 + ra = ka->sa_restorer; 7209 + } else { 7210 + ra = frame_addr + offsetof(struct target_rt_sigframe, retcode); 7211 + #ifdef TARGET_WORDS_BIGENDIAN 7212 + /* Generate instruction: MOVI a2, __NR_rt_sigreturn */ 7213 + __put_user(0x22, &frame->retcode[0]); 7214 + __put_user(0x0a, &frame->retcode[1]); 7215 + __put_user(TARGET_NR_rt_sigreturn, &frame->retcode[2]); 7216 + /* Generate instruction: SYSCALL */ 7217 + __put_user(0x00, &frame->retcode[3]); 7218 + __put_user(0x05, &frame->retcode[4]); 7219 + __put_user(0x00, &frame->retcode[5]); 7220 + #else 7221 + /* Generate instruction: MOVI a2, __NR_rt_sigreturn */ 7222 + __put_user(0x22, &frame->retcode[0]); 7223 + __put_user(0xa0, &frame->retcode[1]); 7224 + __put_user(TARGET_NR_rt_sigreturn, &frame->retcode[2]); 7225 + /* Generate instruction: SYSCALL */ 7226 + __put_user(0x00, &frame->retcode[3]); 7227 + __put_user(0x50, &frame->retcode[4]); 7228 + __put_user(0x00, &frame->retcode[5]); 7229 + #endif 7230 + } 7231 + env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 7232 + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER)) { 7233 + env->sregs[PS] |= PS_WOE | (1 << PS_CALLINC_SHIFT); 7234 + } 7235 + memset(env->regs, 0, sizeof(env->regs)); 7236 + env->pc = ka->_sa_handler; 7237 + env->regs[1] = frame_addr; 7238 + env->sregs[WINDOW_BASE] = 0; 7239 + env->sregs[WINDOW_START] = 1; 7240 + 7241 + env->regs[4] = (ra & 0x3fffffff) | 0x40000000; 7242 + env->regs[6] = sig; 7243 + env->regs[7] = frame_addr + offsetof(struct target_rt_sigframe, info); 7244 + env->regs[8] = frame_addr + offsetof(struct target_rt_sigframe, uc); 7245 + unlock_user_struct(frame, frame_addr, 1); 7246 + return; 7247 + 7248 + give_sigsegv: 7249 + force_sigsegv(sig); 7250 + return; 7251 + } 7252 + 7253 + static void restore_sigcontext(CPUXtensaState *env, 7254 + struct target_rt_sigframe *frame) 7255 + { 7256 + struct target_sigcontext *sc = &frame->uc.tuc_mcontext; 7257 + uint32_t ps; 7258 + int i; 7259 + 7260 + __get_user(env->pc, &sc->sc_pc); 7261 + __get_user(ps, &sc->sc_ps); 7262 + __get_user(env->sregs[LBEG], &sc->sc_lbeg); 7263 + __get_user(env->sregs[LEND], &sc->sc_lend); 7264 + __get_user(env->sregs[LCOUNT], &sc->sc_lcount); 7265 + 7266 + env->sregs[WINDOW_BASE] = 0; 7267 + env->sregs[WINDOW_START] = 1; 7268 + env->sregs[PS] = deposit32(env->sregs[PS], 7269 + PS_CALLINC_SHIFT, 7270 + PS_CALLINC_LEN, 7271 + extract32(ps, PS_CALLINC_SHIFT, 7272 + PS_CALLINC_LEN)); 7273 + for (i = 0; i < 16; ++i) { 7274 + __get_user(env->regs[i], sc->sc_a + i); 7275 + } 7276 + /* TODO: xtregs */ 7277 + } 7278 + 7279 + long do_rt_sigreturn(CPUXtensaState *env) 7280 + { 7281 + abi_ulong frame_addr = env->regs[1]; 7282 + struct target_rt_sigframe *frame; 7283 + sigset_t set; 7284 + 7285 + trace_user_do_rt_sigreturn(env, frame_addr); 7286 + if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { 7287 + goto badframe; 7288 + } 7289 + target_to_host_sigset(&set, &frame->uc.tuc_sigmask); 7290 + set_sigmask(&set); 7291 + 7292 + restore_sigcontext(env, frame); 7293 + 7294 + if (do_sigaltstack(frame_addr + 7295 + offsetof(struct target_rt_sigframe, uc.tuc_stack), 7296 + 0, get_sp_from_cpustate(env)) == -TARGET_EFAULT) { 7297 + goto badframe; 7298 + } 7299 + unlock_user_struct(frame, frame_addr, 0); 7300 + return -TARGET_QEMU_ESIGRETURN; 7301 + 7302 + badframe: 7303 + unlock_user_struct(frame, frame_addr, 0); 7304 + force_sig(TARGET_SIGSEGV); 7305 + return -TARGET_QEMU_ESIGRETURN; 7306 + } 7307 + 7054 7308 #else 7055 7309 7056 7310 static void setup_frame(int sig, struct target_sigaction *ka, ··· 7154 7408 || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) \ 7155 7409 || defined(TARGET_PPC64) || defined(TARGET_HPPA) \ 7156 7410 || defined(TARGET_NIOS2) || defined(TARGET_X86_64) \ 7157 - || defined(TARGET_RISCV) 7411 + || defined(TARGET_RISCV) || defined(TARGET_XTENSA) 7158 7412 /* These targets do not have traditional signals. */ 7159 7413 setup_rt_frame(sig, sa, &k->info, &target_old_set, cpu_env); 7160 7414 #else

+2

linux-user/syscall.c

··· 709 709 return 0; 710 710 } 711 711 } 712 + #elif defined(TARGET_XTENSA) 713 + static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } 712 714 #else 713 715 static inline int regpairs_aligned(void *cpu_env, int num) { return 0; } 714 716 #endif

+62 -3

linux-user/syscall_defs.h

··· 71 71 || defined(TARGET_M68K) || defined(TARGET_CRIS) \ 72 72 || defined(TARGET_UNICORE32) || defined(TARGET_S390X) \ 73 73 || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) \ 74 - || defined(TARGET_NIOS2) || defined(TARGET_RISCV) 74 + || defined(TARGET_NIOS2) || defined(TARGET_RISCV) \ 75 + || defined(TARGET_XTENSA) 75 76 76 77 #define TARGET_IOC_SIZEBITS 14 77 78 #define TARGET_IOC_DIRBITS 2 ··· 436 437 || defined(TARGET_MICROBLAZE) || defined(TARGET_UNICORE32) \ 437 438 || defined(TARGET_S390X) || defined(TARGET_OPENRISC) \ 438 439 || defined(TARGET_TILEGX) || defined(TARGET_HPPA) || defined(TARGET_NIOS2) \ 439 - || defined(TARGET_RISCV) 440 + || defined(TARGET_RISCV) || defined(TARGET_XTENSA) 440 441 441 442 #if defined(TARGET_SPARC) 442 443 #define TARGET_SA_NOCLDSTOP 8u ··· 1392 1393 #define TARGET_MAP_NONBLOCK 0x20000 /* do not block on IO */ 1393 1394 #define TARGET_MAP_STACK 0x40000 /* ignored */ 1394 1395 #define TARGET_MAP_HUGETLB 0x80000 /* create a huge page mapping */ 1396 + #elif defined(TARGET_XTENSA) 1397 + #define TARGET_MAP_FIXED 0x10 /* Interpret addr exactly */ 1398 + #define TARGET_MAP_ANONYMOUS 0x0800 /* don't use a file */ 1399 + #define TARGET_MAP_GROWSDOWN 0x1000 /* stack-like segment */ 1400 + #define TARGET_MAP_DENYWRITE 0x2000 /* ETXTBSY */ 1401 + #define TARGET_MAP_EXECUTABLE 0x4000 /* mark it as an executable */ 1402 + #define TARGET_MAP_LOCKED 0x8000 /* pages are locked */ 1403 + #define TARGET_MAP_NORESERVE 0x0400 /* don't check for reservations */ 1404 + #define TARGET_MAP_POPULATE 0x10000 /* populate (prefault) pagetables */ 1405 + #define TARGET_MAP_NONBLOCK 0x20000 /* do not block on IO */ 1406 + #define TARGET_MAP_STACK 0x40000 1407 + #define TARGET_MAP_HUGETLB 0x80000 /* create a huge page mapping */ 1395 1408 #else 1396 1409 #define TARGET_MAP_FIXED 0x10 /* Interpret addr exactly */ 1397 1410 #define TARGET_MAP_ANONYMOUS 0x20 /* don't use a file */ ··· 2093 2106 abi_ulong target_st_ctime_nsec; 2094 2107 unsigned int __unused[2]; 2095 2108 }; 2109 + #elif defined(TARGET_XTENSA) 2110 + struct target_stat { 2111 + abi_ulong st_dev; 2112 + abi_ulong st_ino; 2113 + unsigned int st_mode; 2114 + unsigned int st_nlink; 2115 + unsigned int st_uid; 2116 + unsigned int st_gid; 2117 + abi_ulong st_rdev; 2118 + abi_long st_size; 2119 + abi_ulong st_blksize; 2120 + abi_ulong st_blocks; 2121 + abi_ulong target_st_atime; 2122 + abi_ulong target_st_atime_nsec; 2123 + abi_ulong target_st_mtime; 2124 + abi_ulong target_st_mtime_nsec; 2125 + abi_ulong target_st_ctime; 2126 + abi_ulong target_st_ctime_nsec; 2127 + abi_ulong __unused4; 2128 + abi_ulong __unused5; 2129 + }; 2130 + 2131 + #define TARGET_HAS_STRUCT_STAT64 2132 + struct target_stat64 { 2133 + uint64_t st_dev; /* Device */ 2134 + uint64_t st_ino; /* File serial number */ 2135 + unsigned int st_mode; /* File mode. */ 2136 + unsigned int st_nlink; /* Link count. */ 2137 + unsigned int st_uid; /* User ID of the file's owner. */ 2138 + unsigned int st_gid; /* Group ID of the file's group. */ 2139 + uint64_t st_rdev; /* Device number, if device. */ 2140 + int64_t st_size; /* Size of file, in bytes. */ 2141 + abi_ulong st_blksize; /* Optimal block size for I/O. */ 2142 + abi_ulong __unused2; 2143 + uint64_t st_blocks; /* Number 512-byte blocks allocated. */ 2144 + abi_ulong target_st_atime; /* Time of last access. */ 2145 + abi_ulong target_st_atime_nsec; 2146 + abi_ulong target_st_mtime; /* Time of last modification. */ 2147 + abi_ulong target_st_mtime_nsec; 2148 + abi_ulong target_st_ctime; /* Time of last status change. */ 2149 + abi_ulong target_st_ctime_nsec; 2150 + abi_ulong __unused4; 2151 + abi_ulong __unused5; 2152 + }; 2153 + 2096 2154 #elif defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) || \ 2097 2155 defined(TARGET_NIOS2) || defined(TARGET_RISCV) 2098 2156 ··· 2593 2651 short l_whence; 2594 2652 #if defined(TARGET_PPC) || defined(TARGET_X86_64) || defined(TARGET_MIPS) \ 2595 2653 || defined(TARGET_SPARC) || defined(TARGET_HPPA) \ 2596 - || defined(TARGET_MICROBLAZE) || defined(TARGET_TILEGX) 2654 + || defined(TARGET_MICROBLAZE) || defined(TARGET_TILEGX) \ 2655 + || defined(TARGET_XTENSA) 2597 2656 int __pad; 2598 2657 #endif 2599 2658 abi_llong l_start;

linux-user/xtensa/syscall.h

This is a binary file and will not be displayed.

+437

linux-user/xtensa/syscall_nr.h

··· 1 + /* 2 + * include/asm-xtensa/unistd.h 3 + * 4 + * This file is subject to the terms and conditions of the GNU General Public 5 + * License. See the file "COPYING" in the main directory of this archive 6 + * for more details. 7 + * 8 + * Copyright (C) 2001 - 2009 Tensilica Inc. 9 + */ 10 + 11 + #ifndef _XTENSA_UNISTD_H 12 + #define _XTENSA_UNISTD_H 13 + 14 + #define TARGET_NR_spill 0 15 + #define TARGET_NR_xtensa 1 16 + #define TARGET_NR_available4 2 17 + #define TARGET_NR_available5 3 18 + #define TARGET_NR_available6 4 19 + #define TARGET_NR_available7 5 20 + #define TARGET_NR_available8 6 21 + #define TARGET_NR_available9 7 22 + 23 + /* File Operations */ 24 + 25 + #define TARGET_NR_open 8 26 + #define TARGET_NR_close 9 27 + #define TARGET_NR_dup 10 28 + #define TARGET_NR_dup2 11 29 + #define TARGET_NR_read 12 30 + #define TARGET_NR_write 13 31 + #define TARGET_NR_select 14 32 + #define TARGET_NR_lseek 15 33 + #define TARGET_NR_poll 16 34 + #define TARGET_NR__llseek 17 35 + #define TARGET_NR_epoll_wait 18 36 + #define TARGET_NR_epoll_ctl 19 37 + #define TARGET_NR_epoll_create 20 38 + #define TARGET_NR_creat 21 39 + #define TARGET_NR_truncate 22 40 + #define TARGET_NR_ftruncate 23 41 + #define TARGET_NR_readv 24 42 + #define TARGET_NR_writev 25 43 + #define TARGET_NR_fsync 26 44 + #define TARGET_NR_fdatasync 27 45 + #define TARGET_NR_truncate64 28 46 + #define TARGET_NR_ftruncate64 29 47 + #define TARGET_NR_pread64 30 48 + #define TARGET_NR_pwrite64 31 49 + 50 + #define TARGET_NR_link 32 51 + #define TARGET_NR_rename 33 52 + #define TARGET_NR_symlink 34 53 + #define TARGET_NR_readlink 35 54 + #define TARGET_NR_mknod 36 55 + #define TARGET_NR_pipe 37 56 + #define TARGET_NR_unlink 38 57 + #define TARGET_NR_rmdir 39 58 + 59 + #define TARGET_NR_mkdir 40 60 + #define TARGET_NR_chdir 41 61 + #define TARGET_NR_fchdir 42 62 + #define TARGET_NR_getcwd 43 63 + 64 + #define TARGET_NR_chmod 44 65 + #define TARGET_NR_chown 45 66 + #define TARGET_NR_stat 46 67 + #define TARGET_NR_stat64 47 68 + 69 + #define TARGET_NR_lchown 48 70 + #define TARGET_NR_lstat 49 71 + #define TARGET_NR_lstat64 50 72 + #define TARGET_NR_available51 51 73 + 74 + #define TARGET_NR_fchmod 52 75 + #define TARGET_NR_fchown 53 76 + #define TARGET_NR_fstat 54 77 + #define TARGET_NR_fstat64 55 78 + 79 + #define TARGET_NR_flock 56 80 + #define TARGET_NR_access 57 81 + #define TARGET_NR_umask 58 82 + #define TARGET_NR_getdents 59 83 + #define TARGET_NR_getdents64 60 84 + #define TARGET_NR_fcntl64 61 85 + #define TARGET_NR_fallocate 62 86 + #define TARGET_NR_fadvise64_64 63 87 + #define TARGET_NR_utime 64 /* glibc 2.3.3 ?? */ 88 + #define TARGET_NR_utimes 65 89 + #define TARGET_NR_ioctl 66 90 + #define TARGET_NR_fcntl 67 91 + 92 + #define TARGET_NR_setxattr 68 93 + #define TARGET_NR_getxattr 69 94 + #define TARGET_NR_listxattr 70 95 + #define TARGET_NR_removexattr 71 96 + #define TARGET_NR_lsetxattr 72 97 + #define TARGET_NR_lgetxattr 73 98 + #define TARGET_NR_llistxattr 74 99 + #define TARGET_NR_lremovexattr 75 100 + #define TARGET_NR_fsetxattr 76 101 + #define TARGET_NR_fgetxattr 77 102 + #define TARGET_NR_flistxattr 78 103 + #define TARGET_NR_fremovexattr 79 104 + 105 + /* File Map / Shared Memory Operations */ 106 + 107 + #define TARGET_NR_mmap2 80 108 + #define TARGET_NR_munmap 81 109 + #define TARGET_NR_mprotect 82 110 + #define TARGET_NR_brk 83 111 + #define TARGET_NR_mlock 84 112 + #define TARGET_NR_munlock 85 113 + #define TARGET_NR_mlockall 86 114 + #define TARGET_NR_munlockall 87 115 + #define TARGET_NR_mremap 88 116 + #define TARGET_NR_msync 89 117 + #define TARGET_NR_mincore 90 118 + #define TARGET_NR_madvise 91 119 + #define TARGET_NR_shmget 92 120 + #define TARGET_NR_shmat 93 121 + #define TARGET_NR_shmctl 94 122 + #define TARGET_NR_shmdt 95 123 + 124 + /* Socket Operations */ 125 + 126 + #define TARGET_NR_socket 96 127 + #define TARGET_NR_setsockopt 97 128 + #define TARGET_NR_getsockopt 98 129 + #define TARGET_NR_shutdown 99 130 + 131 + #define TARGET_NR_bind 100 132 + #define TARGET_NR_connect 101 133 + #define TARGET_NR_listen 102 134 + #define TARGET_NR_accept 103 135 + 136 + #define TARGET_NR_getsockname 104 137 + #define TARGET_NR_getpeername 105 138 + #define TARGET_NR_sendmsg 106 139 + #define TARGET_NR_recvmsg 107 140 + #define TARGET_NR_send 108 141 + #define TARGET_NR_recv 109 142 + #define TARGET_NR_sendto 110 143 + #define TARGET_NR_recvfrom 111 144 + 145 + #define TARGET_NR_socketpair 112 146 + #define TARGET_NR_sendfile 113 147 + #define TARGET_NR_sendfile64 114 148 + #define TARGET_NR_sendmmsg 115 149 + 150 + /* Process Operations */ 151 + 152 + #define TARGET_NR_clone 116 153 + #define TARGET_NR_execve 117 154 + #define TARGET_NR_exit 118 155 + #define TARGET_NR_exit_group 119 156 + #define TARGET_NR_getpid 120 157 + #define TARGET_NR_wait4 121 158 + #define TARGET_NR_waitid 122 159 + #define TARGET_NR_kill 123 160 + #define TARGET_NR_tkill 124 161 + #define TARGET_NR_tgkill 125 162 + #define TARGET_NR_set_tid_address 126 163 + #define TARGET_NR_gettid 127 164 + #define TARGET_NR_setsid 128 165 + #define TARGET_NR_getsid 129 166 + #define TARGET_NR_prctl 130 167 + #define TARGET_NR_personality 131 168 + #define TARGET_NR_getpriority 132 169 + #define TARGET_NR_setpriority 133 170 + #define TARGET_NR_setitimer 134 171 + #define TARGET_NR_getitimer 135 172 + #define TARGET_NR_setuid 136 173 + #define TARGET_NR_getuid 137 174 + #define TARGET_NR_setgid 138 175 + #define TARGET_NR_getgid 139 176 + #define TARGET_NR_geteuid 140 177 + #define TARGET_NR_getegid 141 178 + #define TARGET_NR_setreuid 142 179 + #define TARGET_NR_setregid 143 180 + #define TARGET_NR_setresuid 144 181 + #define TARGET_NR_getresuid 145 182 + #define TARGET_NR_setresgid 146 183 + #define TARGET_NR_getresgid 147 184 + #define TARGET_NR_setpgid 148 185 + #define TARGET_NR_getpgid 149 186 + #define TARGET_NR_getppid 150 187 + #define TARGET_NR_getpgrp 151 188 + 189 + #define TARGET_NR_reserved152 152 /* set_thread_area */ 190 + #define TARGET_NR_reserved153 153 /* get_thread_area */ 191 + #define TARGET_NR_times 154 192 + #define TARGET_NR_acct 155 193 + #define TARGET_NR_sched_setaffinity 156 194 + #define TARGET_NR_sched_getaffinity 157 195 + #define TARGET_NR_capget 158 196 + #define TARGET_NR_capset 159 197 + #define TARGET_NR_ptrace 160 198 + #define TARGET_NR_semtimedop 161 199 + #define TARGET_NR_semget 162 200 + #define TARGET_NR_semop 163 201 + #define TARGET_NR_semctl 164 202 + #define TARGET_NR_available165 165 203 + #define TARGET_NR_msgget 166 204 + #define TARGET_NR_msgsnd 167 205 + #define TARGET_NR_msgrcv 168 206 + #define TARGET_NR_msgctl 169 207 + #define TARGET_NR_available170 170 208 + 209 + /* File System */ 210 + 211 + #define TARGET_NR_umount2 171 212 + #define TARGET_NR_mount 172 213 + #define TARGET_NR_swapon 173 214 + #define TARGET_NR_chroot 174 215 + #define TARGET_NR_pivot_root 175 216 + #define TARGET_NR_umount 176 217 + #define TARGET_NR_swapoff 177 218 + #define TARGET_NR_sync 178 219 + #define TARGET_NR_syncfs 179 220 + #define TARGET_NR_setfsuid 180 221 + #define TARGET_NR_setfsgid 181 222 + #define TARGET_NR_sysfs 182 223 + #define TARGET_NR_ustat 183 224 + #define TARGET_NR_statfs 184 225 + #define TARGET_NR_fstatfs 185 226 + #define TARGET_NR_statfs64 186 227 + #define TARGET_NR_fstatfs64 187 228 + 229 + /* System */ 230 + 231 + #define TARGET_NR_setrlimit 188 232 + #define TARGET_NR_getrlimit 189 233 + #define TARGET_NR_getrusage 190 234 + #define TARGET_NR_futex 191 235 + #define TARGET_NR_gettimeofday 192 236 + #define TARGET_NR_settimeofday 193 237 + #define TARGET_NR_adjtimex 194 238 + #define TARGET_NR_nanosleep 195 239 + #define TARGET_NR_getgroups 196 240 + #define TARGET_NR_setgroups 197 241 + #define TARGET_NR_sethostname 198 242 + #define TARGET_NR_setdomainname 199 243 + #define TARGET_NR_syslog 200 244 + #define TARGET_NR_vhangup 201 245 + #define TARGET_NR_uselib 202 246 + #define TARGET_NR_reboot 203 247 + #define TARGET_NR_quotactl 204 248 + #define TARGET_NR_nfsservctl 205 249 + #define TARGET_NR__sysctl 206 250 + #define TARGET_NR_bdflush 207 251 + #define TARGET_NR_uname 208 252 + #define TARGET_NR_sysinfo 209 253 + #define TARGET_NR_init_module 210 254 + #define TARGET_NR_delete_module 211 255 + 256 + #define TARGET_NR_sched_setparam 212 257 + #define TARGET_NR_sched_getparam 213 258 + #define TARGET_NR_sched_setscheduler 214 259 + #define TARGET_NR_sched_getscheduler 215 260 + #define TARGET_NR_sched_get_priority_max 216 261 + #define TARGET_NR_sched_get_priority_min 217 262 + #define TARGET_NR_sched_rr_get_interval 218 263 + #define TARGET_NR_sched_yield 219 264 + #define TARGET_NR_available222 222 265 + 266 + /* Signal Handling */ 267 + 268 + #define TARGET_NR_restart_syscall 223 269 + #define TARGET_NR_sigaltstack 224 270 + #define TARGET_NR_rt_sigreturn 225 271 + #define TARGET_NR_rt_sigaction 226 272 + #define TARGET_NR_rt_sigprocmask 227 273 + #define TARGET_NR_rt_sigpending 228 274 + #define TARGET_NR_rt_sigtimedwait 229 275 + #define TARGET_NR_rt_sigqueueinfo 230 276 + #define TARGET_NR_rt_sigsuspend 231 277 + 278 + /* Message */ 279 + 280 + #define TARGET_NR_mq_open 232 281 + #define TARGET_NR_mq_unlink 233 282 + #define TARGET_NR_mq_timedsend 234 283 + #define TARGET_NR_mq_timedreceive 235 284 + #define TARGET_NR_mq_notify 236 285 + #define TARGET_NR_mq_getsetattr 237 286 + #define TARGET_NR_available238 238 287 + 288 + /* IO */ 289 + 290 + #define TARGET_NR_io_setup 239 291 + #define TARGET_NR_io_destroy 240 292 + #define TARGET_NR_io_submit 241 293 + #define TARGET_NR_io_getevents 242 294 + #define TARGET_NR_io_cancel 243 295 + #define TARGET_NR_clock_settime 244 296 + #define TARGET_NR_clock_gettime 245 297 + #define TARGET_NR_clock_getres 246 298 + #define TARGET_NR_clock_nanosleep 247 299 + 300 + /* Timer */ 301 + 302 + #define TARGET_NR_timer_create 248 303 + #define TARGET_NR_timer_delete 249 304 + #define TARGET_NR_timer_settime 250 305 + #define TARGET_NR_timer_gettime 251 306 + #define TARGET_NR_timer_getoverrun 252 307 + 308 + /* System */ 309 + 310 + #define TARGET_NR_reserved253 253 311 + #define TARGET_NR_lookup_dcookie 254 312 + #define TARGET_NR_available255 255 313 + #define TARGET_NR_add_key 256 314 + #define TARGET_NR_request_key 257 315 + #define TARGET_NR_keyctl 258 316 + #define TARGET_NR_available259 259 317 + 318 + 319 + #define TARGET_NR_readahead 260 320 + #define TARGET_NR_remap_file_pages 261 321 + #define TARGET_NR_migrate_pages 262 322 + #define TARGET_NR_mbind 263 323 + #define TARGET_NR_get_mempolicy 264 324 + #define TARGET_NR_set_mempolicy 265 325 + #define TARGET_NR_unshare 266 326 + #define TARGET_NR_move_pages 267 327 + #define TARGET_NR_splice 268 328 + #define TARGET_NR_tee 269 329 + #define TARGET_NR_vmsplice 270 330 + #define TARGET_NR_available271 271 331 + 332 + #define TARGET_NR_pselect6 272 333 + #define TARGET_NR_ppoll 273 334 + #define TARGET_NR_epoll_pwait 274 335 + #define TARGET_NR_epoll_create1 275 336 + 337 + #define TARGET_NR_inotify_init 276 338 + #define TARGET_NR_inotify_add_watch 277 339 + #define TARGET_NR_inotify_rm_watch 278 340 + #define TARGET_NR_inotify_init1 279 341 + 342 + #define TARGET_NR_getcpu 280 343 + #define TARGET_NR_kexec_load 281 344 + 345 + #define TARGET_NR_ioprio_set 282 346 + #define TARGET_NR_ioprio_get 283 347 + 348 + #define TARGET_NR_set_robust_list 284 349 + #define TARGET_NR_get_robust_list 285 350 + #define TARGET_NR_available286 286 351 + #define TARGET_NR_available287 287 352 + 353 + /* Relative File Operations */ 354 + 355 + #define TARGET_NR_openat 288 356 + #define TARGET_NR_mkdirat 289 357 + #define TARGET_NR_mknodat 290 358 + #define TARGET_NR_unlinkat 291 359 + #define TARGET_NR_renameat 292 360 + #define TARGET_NR_linkat 293 361 + #define TARGET_NR_symlinkat 294 362 + #define TARGET_NR_readlinkat 295 363 + #define TARGET_NR_utimensat 296 364 + #define TARGET_NR_fchownat 297 365 + #define TARGET_NR_futimesat 298 366 + #define TARGET_NR_fstatat64 299 367 + #define TARGET_NR_fchmodat 300 368 + #define TARGET_NR_faccessat 301 369 + #define TARGET_NR_available302 302 370 + #define TARGET_NR_available303 303 371 + 372 + #define TARGET_NR_signalfd 304 373 + /* 305 was TARGET_NR_timerfd */ 374 + #define TARGET_NR_eventfd 306 375 + #define TARGET_NR_recvmmsg 307 376 + 377 + #define TARGET_NR_setns 308 378 + #define TARGET_NR_signalfd4 309 379 + #define TARGET_NR_dup3 310 380 + #define TARGET_NR_pipe2 311 381 + 382 + #define TARGET_NR_timerfd_create 312 383 + #define TARGET_NR_timerfd_settime 313 384 + #define TARGET_NR_timerfd_gettime 314 385 + #define TARGET_NR_available315 315 386 + 387 + #define TARGET_NR_eventfd2 316 388 + #define TARGET_NR_preadv 317 389 + #define TARGET_NR_pwritev 318 390 + #define TARGET_NR_available319 319 391 + 392 + #define TARGET_NR_fanotify_init 320 393 + #define TARGET_NR_fanotify_mark 321 394 + #define TARGET_NR_process_vm_readv 322 395 + #define TARGET_NR_process_vm_writev 323 396 + 397 + #define TARGET_NR_name_to_handle_at 324 398 + #define TARGET_NR_open_by_handle_at 325 399 + #define TARGET_NR_sync_file_range2 326 400 + #define TARGET_NR_perf_event_open 327 401 + 402 + #define TARGET_NR_rt_tgsigqueueinfo 328 403 + #define TARGET_NR_clock_adjtime 329 404 + #define TARGET_NR_prlimit64 330 405 + #define TARGET_NR_kcmp 331 406 + 407 + #define TARGET_NR_finit_module 332 408 + 409 + #define TARGET_NR_accept4 333 410 + 411 + #define TARGET_NR_sched_setattr 334 412 + #define TARGET_NR_sched_getattr 335 413 + 414 + #define TARGET_NR_renameat2 336 415 + 416 + #define TARGET_NR_seccomp 337 417 + #define TARGET_NR_getrandom 338 418 + #define TARGET_NR_memfd_create 339 419 + #define TARGET_NR_bpf 340 420 + #define TARGET_NR_execveat 341 421 + 422 + #define TARGET_NR_userfaultfd 342 423 + #define TARGET_NR_membarrier 343 424 + #define TARGET_NR_mlock2 344 425 + #define TARGET_NR_copy_file_range 345 426 + #define TARGET_NR_preadv2 346 427 + #define TARGET_NR_pwritev2 347 428 + 429 + #define TARGET_NR_pkey_mprotect 348 430 + #define TARGET_NR_pkey_alloc 349 431 + #define TARGET_NR_pkey_free 350 432 + 433 + #define TARGET_NR_statx 351 434 + 435 + #define TARGET_NR_syscall_count 352 436 + 437 + #endif /* _XTENSA_UNISTD_H */

+22

linux-user/xtensa/target_cpu.h

··· 1 + /* 2 + * Xtensa-specific CPU ABI and functions for linux-user 3 + */ 4 + #ifndef XTENSA_TARGET_CPU_H 5 + #define XTENSA_TARGET_CPU_H 6 + 7 + static inline void cpu_clone_regs(CPUXtensaState *env, target_ulong newsp) 8 + { 9 + if (newsp) { 10 + env->regs[1] = newsp; 11 + env->sregs[WINDOW_BASE] = 0; 12 + env->sregs[WINDOW_START] = 0x1; 13 + } 14 + env->regs[2] = 0; 15 + } 16 + 17 + static inline void cpu_set_tls(CPUXtensaState *env, target_ulong newtls) 18 + { 19 + env->uregs[THREADPTR] = newtls; 20 + } 21 + 22 + #endif

+16

linux-user/xtensa/target_elf.h

··· 1 + /* 2 + * This program is free software; you can redistribute it and/or modify 3 + * it under the terms of the GNU General Public License version 2 as 4 + * published by the Free Software Foundation, or (at your option) any 5 + * later version. See the COPYING file in the top-level directory. 6 + */ 7 + 8 + #ifndef XTENSA_TARGET_ELF_H 9 + #define XTENSA_TARGET_ELF_H 10 + 11 + static inline const char *cpu_get_model(uint32_t eflags) 12 + { 13 + return XTENSA_DEFAULT_CPU_MODEL; 14 + } 15 + 16 + #endif

+28

linux-user/xtensa/target_signal.h

··· 1 + #ifndef XTENSA_TARGET_SIGNAL_H 2 + #define XTENSA_TARGET_SIGNAL_H 3 + 4 + #include "cpu.h" 5 + 6 + /* this struct defines a stack used during syscall handling */ 7 + 8 + typedef struct target_sigaltstack { 9 + abi_ulong ss_sp; 10 + abi_int ss_flags; 11 + abi_ulong ss_size; 12 + } target_stack_t; 13 + 14 + /* 15 + * sigaltstack controls 16 + */ 17 + #define TARGET_SS_ONSTACK 1 18 + #define TARGET_SS_DISABLE 2 19 + 20 + #define TARGET_MINSIGSTKSZ 2048 21 + #define TARGET_SIGSTKSZ 8192 22 + 23 + static inline abi_ulong get_sp_from_cpustate(CPUXtensaState *state) 24 + { 25 + return state->regs[1]; 26 + } 27 + 28 + #endif

+28

linux-user/xtensa/target_structs.h

··· 1 + #ifndef XTENSA_TARGET_STRUCTS_T 2 + #define XTENSA_TARGET_STRUCTS_T 3 + 4 + struct target_ipc_perm { 5 + abi_int __key; /* Key. */ 6 + abi_uint uid; /* Owner's user ID. */ 7 + abi_uint gid; /* Owner's group ID. */ 8 + abi_uint cuid; /* Creator's user ID. */ 9 + abi_uint cgid; /* Creator's group ID. */ 10 + abi_uint mode; /* Read/write permission. */ 11 + abi_ushort __seq; /* Sequence number. */ 12 + }; 13 + 14 + struct target_shmid_ds { 15 + struct target_ipc_perm shm_perm; /* operation permission struct */ 16 + abi_int shm_segsz; /* size of segment in bytes */ 17 + abi_long shm_atime; /* time of last shmat() */ 18 + abi_long shm_dtime; /* time of last shmdt() */ 19 + abi_long shm_ctime; /* time of last change by shmctl() */ 20 + abi_ushort shm_cpid; /* pid of creator */ 21 + abi_ushort shm_lpid; /* pid of last shmop */ 22 + abi_ushort shm_nattch; /* number of current attaches */ 23 + abi_ushort shm_unused; /* compatibility */ 24 + abi_ulong __unused2; 25 + abi_ulong __unused3; 26 + }; 27 + 28 + #endif

+49

linux-user/xtensa/target_syscall.h

··· 1 + #ifndef XTENSA_TARGET_SYSCALL_H 2 + #define XTENSA_TARGET_SYSCALL_H 3 + 4 + #define UNAME_MACHINE "xtensa" 5 + 6 + #define UNAME_MINIMUM_RELEASE "3.19" 7 + #define TARGET_CLONE_BACKWARDS 8 + 9 + #define MMAP_SHIFT TARGET_PAGE_BITS 10 + 11 + typedef uint32_t xtensa_reg_t; 12 + typedef struct { 13 + } xtregs_opt_t; /* TODO */ 14 + 15 + struct target_pt_regs { 16 + xtensa_reg_t pc; /* 4 */ 17 + xtensa_reg_t ps; /* 8 */ 18 + xtensa_reg_t depc; /* 12 */ 19 + xtensa_reg_t exccause; /* 16 */ 20 + xtensa_reg_t excvaddr; /* 20 */ 21 + xtensa_reg_t debugcause; /* 24 */ 22 + xtensa_reg_t wmask; /* 28 */ 23 + xtensa_reg_t lbeg; /* 32 */ 24 + xtensa_reg_t lend; /* 36 */ 25 + xtensa_reg_t lcount; /* 40 */ 26 + xtensa_reg_t sar; /* 44 */ 27 + xtensa_reg_t windowbase; /* 48 */ 28 + xtensa_reg_t windowstart; /* 52 */ 29 + xtensa_reg_t syscall; /* 56 */ 30 + xtensa_reg_t icountlevel; /* 60 */ 31 + xtensa_reg_t scompare1; /* 64 */ 32 + xtensa_reg_t threadptr; /* 68 */ 33 + 34 + /* Additional configurable registers that are used by the compiler. */ 35 + xtregs_opt_t xtregs_opt; 36 + 37 + /* Make sure the areg field is 16 bytes aligned. */ 38 + int align[0] __attribute__ ((aligned(16))); 39 + 40 + /* current register frame. 41 + * Note: The ESF for kernel exceptions ends after 16 registers! 42 + */ 43 + xtensa_reg_t areg[16]; 44 + }; 45 + 46 + #define TARGET_MLOCKALL_MCL_CURRENT 1 47 + #define TARGET_MLOCKALL_MCL_FUTURE 2 48 + 49 + #endif

+328

linux-user/xtensa/termbits.h

··· 1 + /* 2 + * include/asm-xtensa/termbits.h 3 + * 4 + * Copied from SH. 5 + * 6 + * This file is subject to the terms and conditions of the GNU General Public 7 + * License. See the file "COPYING" in the main directory of this archive 8 + * for more details. 9 + * 10 + * Copyright (C) 2001 - 2005 Tensilica Inc. 11 + */ 12 + 13 + #ifndef _XTENSA_TERMBITS_H 14 + #define _XTENSA_TERMBITS_H 15 + 16 + #include <linux/posix_types.h> 17 + 18 + typedef unsigned char cc_t; 19 + typedef unsigned int speed_t; 20 + typedef unsigned int tcflag_t; 21 + 22 + #define TARGET_NCCS 19 23 + struct target_termios { 24 + tcflag_t c_iflag; /* input mode flags */ 25 + tcflag_t c_oflag; /* output mode flags */ 26 + tcflag_t c_cflag; /* control mode flags */ 27 + tcflag_t c_lflag; /* local mode flags */ 28 + cc_t c_line; /* line discipline */ 29 + cc_t c_cc[TARGET_NCCS]; /* control characters */ 30 + }; 31 + 32 + struct target_termios2 { 33 + tcflag_t c_iflag; /* input mode flags */ 34 + tcflag_t c_oflag; /* output mode flags */ 35 + tcflag_t c_cflag; /* control mode flags */ 36 + tcflag_t c_lflag; /* local mode flags */ 37 + cc_t c_line; /* line discipline */ 38 + cc_t c_cc[TARGET_NCCS]; /* control characters */ 39 + speed_t c_ispeed; /* input speed */ 40 + speed_t c_ospeed; /* output speed */ 41 + }; 42 + 43 + struct target_ktermios { 44 + tcflag_t c_iflag; /* input mode flags */ 45 + tcflag_t c_oflag; /* output mode flags */ 46 + tcflag_t c_cflag; /* control mode flags */ 47 + tcflag_t c_lflag; /* local mode flags */ 48 + cc_t c_line; /* line discipline */ 49 + cc_t c_cc[TARGET_NCCS]; /* control characters */ 50 + speed_t c_ispeed; /* input speed */ 51 + speed_t c_ospeed; /* output speed */ 52 + }; 53 + 54 + /* c_cc characters */ 55 + 56 + #define TARGET_VINTR 0 57 + #define TARGET_VQUIT 1 58 + #define TARGET_VERASE 2 59 + #define TARGET_VKILL 3 60 + #define TARGET_VEOF 4 61 + #define TARGET_VTIME 5 62 + #define TARGET_VMIN 6 63 + #define TARGET_VSWTC 7 64 + #define TARGET_VSTART 8 65 + #define TARGET_VSTOP 9 66 + #define TARGET_VSUSP 10 67 + #define TARGET_VEOL 11 68 + #define TARGET_VREPRINT 12 69 + #define TARGET_VDISCARD 13 70 + #define TARGET_VWERASE 14 71 + #define TARGET_VLNEXT 15 72 + #define TARGET_VEOL2 16 73 + 74 + /* c_iflag bits */ 75 + 76 + #define TARGET_IGNBRK 0000001 77 + #define TARGET_BRKINT 0000002 78 + #define TARGET_IGNPAR 0000004 79 + #define TARGET_PARMRK 0000010 80 + #define TARGET_INPCK 0000020 81 + #define TARGET_ISTRIP 0000040 82 + #define TARGET_INLCR 0000100 83 + #define TARGET_IGNCR 0000200 84 + #define TARGET_ICRNL 0000400 85 + #define TARGET_IUCLC 0001000 86 + #define TARGET_IXON 0002000 87 + #define TARGET_IXANY 0004000 88 + #define TARGET_IXOFF 0010000 89 + #define TARGET_IMAXBEL 0020000 90 + #define TARGET_IUTF8 0040000 91 + 92 + /* c_oflag bits */ 93 + 94 + #define TARGET_OPOST 0000001 95 + #define TARGET_OLCUC 0000002 96 + #define TARGET_ONLCR 0000004 97 + #define TARGET_OCRNL 0000010 98 + #define TARGET_ONOCR 0000020 99 + #define TARGET_ONLRET 0000040 100 + #define TARGET_OFILL 0000100 101 + #define TARGET_OFDEL 0000200 102 + #define TARGET_NLDLY 0000400 103 + #define TARGET_NL0 0000000 104 + #define TARGET_NL1 0000400 105 + #define TARGET_CRDLY 0003000 106 + #define TARGET_CR0 0000000 107 + #define TARGET_CR1 0001000 108 + #define TARGET_CR2 0002000 109 + #define TARGET_CR3 0003000 110 + #define TARGET_TABDLY 0014000 111 + #define TARGET_TAB0 0000000 112 + #define TARGET_TAB1 0004000 113 + #define TARGET_TAB2 0010000 114 + #define TARGET_TAB3 0014000 115 + #define TARGET_XTABS 0014000 116 + #define TARGET_BSDLY 0020000 117 + #define TARGET_BS0 0000000 118 + #define TARGET_BS1 0020000 119 + #define TARGET_VTDLY 0040000 120 + #define TARGET_VT0 0000000 121 + #define TARGET_VT1 0040000 122 + #define TARGET_FFDLY 0100000 123 + #define TARGET_FF0 0000000 124 + #define TARGET_FF1 0100000 125 + 126 + /* c_cflag bit meaning */ 127 + 128 + #define TARGET_CBAUD 0010017 129 + #define TARGET_B0 0000000 /* hang up */ 130 + #define TARGET_B50 0000001 131 + #define TARGET_B75 0000002 132 + #define TARGET_B110 0000003 133 + #define TARGET_B134 0000004 134 + #define TARGET_B150 0000005 135 + #define TARGET_B200 0000006 136 + #define TARGET_B300 0000007 137 + #define TARGET_B600 0000010 138 + #define TARGET_B1200 0000011 139 + #define TARGET_B1800 0000012 140 + #define TARGET_B2400 0000013 141 + #define TARGET_B4800 0000014 142 + #define TARGET_B9600 0000015 143 + #define TARGET_B19200 0000016 144 + #define TARGET_B38400 0000017 145 + #define TARGET_EXTA B19200 146 + #define TARGET_EXTB B38400 147 + #define TARGET_CSIZE 0000060 148 + #define TARGET_CS5 0000000 149 + #define TARGET_CS6 0000020 150 + #define TARGET_CS7 0000040 151 + #define TARGET_CS8 0000060 152 + #define TARGET_CSTOPB 0000100 153 + #define TARGET_CREAD 0000200 154 + #define TARGET_PARENB 0000400 155 + #define TARGET_PARODD 0001000 156 + #define TARGET_HUPCL 0002000 157 + #define TARGET_CLOCAL 0004000 158 + #define TARGET_CBAUDEX 0010000 159 + #define TARGET_BOTHER 0010000 160 + #define TARGET_B57600 0010001 161 + #define TARGET_B115200 0010002 162 + #define TARGET_B230400 0010003 163 + #define TARGET_B460800 0010004 164 + #define TARGET_B500000 0010005 165 + #define TARGET_B576000 0010006 166 + #define TARGET_B921600 0010007 167 + #define TARGET_B1000000 0010010 168 + #define TARGET_B1152000 0010011 169 + #define TARGET_B1500000 0010012 170 + #define TARGET_B2000000 0010013 171 + #define TARGET_B2500000 0010014 172 + #define TARGET_B3000000 0010015 173 + #define TARGET_B3500000 0010016 174 + #define TARGET_B4000000 0010017 175 + #define TARGET_CIBAUD 002003600000 /* input baud rate */ 176 + #define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */ 177 + #define TARGET_CRTSCTS 020000000000 /* flow control */ 178 + 179 + #define TARGET_IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ 180 + 181 + /* c_lflag bits */ 182 + 183 + #define TARGET_ISIG 0000001 184 + #define TARGET_ICANON 0000002 185 + #define TARGET_XCASE 0000004 186 + #define TARGET_ECHO 0000010 187 + #define TARGET_ECHOE 0000020 188 + #define TARGET_ECHOK 0000040 189 + #define TARGET_ECHONL 0000100 190 + #define TARGET_NOFLSH 0000200 191 + #define TARGET_TOSTOP 0000400 192 + #define TARGET_ECHOCTL 0001000 193 + #define TARGET_ECHOPRT 0002000 194 + #define TARGET_ECHOKE 0004000 195 + #define TARGET_FLUSHO 0010000 196 + #define TARGET_PENDIN 0040000 197 + #define TARGET_IEXTEN 0100000 198 + 199 + /* tcflow() and TCXONC use these */ 200 + 201 + #define TARGET_TCOOFF 0 202 + #define TARGET_TCOON 1 203 + #define TARGET_TCIOFF 2 204 + #define TARGET_TCION 3 205 + 206 + /* tcflush() and TCFLSH use these */ 207 + 208 + #define TARGET_TCIFLUSH 0 209 + #define TARGET_TCOFLUSH 1 210 + #define TARGET_TCIOFLUSH 2 211 + 212 + /* tcsetattr uses these */ 213 + 214 + #define TARGET_TCSANOW 0 215 + #define TARGET_TCSADRAIN 1 216 + #define TARGET_TCSAFLUSH 2 217 + 218 + /* from arch/xtensa/include/uapi/asm/ioctls.h */ 219 + 220 + #define TARGET_FIOCLEX _IO('f', 1) 221 + #define TARGET_FIONCLEX _IO('f', 2) 222 + #define TARGET_FIOASYNC _IOW('f', 125, int) 223 + #define TARGET_FIONBIO _IOW('f', 126, int) 224 + #define TARGET_FIONREAD _IOR('f', 127, int) 225 + #define TARGET_TIOCINQ FIONREAD 226 + #define TARGET_FIOQSIZE _IOR('f', 128, loff_t) 227 + 228 + #define TARGET_TCGETS 0x5401 229 + #define TARGET_TCSETS 0x5402 230 + #define TARGET_TCSETSW 0x5403 231 + #define TARGET_TCSETSF 0x5404 232 + 233 + #define TARGET_TCGETA 0x80127417 /* _IOR('t', 23, struct termio) */ 234 + #define TARGET_TCSETA 0x40127418 /* _IOW('t', 24, struct termio) */ 235 + #define TARGET_TCSETAW 0x40127419 /* _IOW('t', 25, struct termio) */ 236 + #define TARGET_TCSETAF 0x4012741C /* _IOW('t', 28, struct termio) */ 237 + 238 + #define TARGET_TCSBRK _IO('t', 29) 239 + #define TARGET_TCXONC _IO('t', 30) 240 + #define TARGET_TCFLSH _IO('t', 31) 241 + 242 + #define TARGET_TIOCSWINSZ 0x40087467 /* _IOW('t', 103, struct winsize) */ 243 + #define TARGET_TIOCGWINSZ 0x80087468 /* _IOR('t', 104, struct winsize) */ 244 + #define TARGET_TIOCSTART _IO('t', 110) /* start output, like ^Q */ 245 + #define TARGET_TIOCSTOP _IO('t', 111) /* stop output, like ^S */ 246 + #define TARGET_TIOCOUTQ _IOR('t', 115, int) /* output queue size */ 247 + 248 + #define TARGET_TIOCSPGRP _IOW('t', 118, int) 249 + #define TARGET_TIOCGPGRP _IOR('t', 119, int) 250 + 251 + #define TARGET_TIOCEXCL _IO('T', 12) 252 + #define TARGET_TIOCNXCL _IO('T', 13) 253 + #define TARGET_TIOCSCTTY _IO('T', 14) 254 + 255 + #define TARGET_TIOCSTI _IOW('T', 18, char) 256 + #define TARGET_TIOCMGET _IOR('T', 21, unsigned int) 257 + #define TARGET_TIOCMBIS _IOW('T', 22, unsigned int) 258 + #define TARGET_TIOCMBIC _IOW('T', 23, unsigned int) 259 + #define TARGET_TIOCMSET _IOW('T', 24, unsigned int) 260 + # define TARGET_TIOCM_LE 0x001 261 + # define TARGET_TIOCM_DTR 0x002 262 + # define TARGET_TIOCM_RTS 0x004 263 + # define TARGET_TIOCM_ST 0x008 264 + # define TARGET_TIOCM_SR 0x010 265 + # define TARGET_TIOCM_CTS 0x020 266 + # define TARGET_TIOCM_CAR 0x040 267 + # define TARGET_TIOCM_RNG 0x080 268 + # define TARGET_TIOCM_DSR 0x100 269 + # define TARGET_TIOCM_CD TIOCM_CAR 270 + # define TARGET_TIOCM_RI TIOCM_RNG 271 + 272 + #define TARGET_TIOCGSOFTCAR _IOR('T', 25, unsigned int) 273 + #define TARGET_TIOCSSOFTCAR _IOW('T', 26, unsigned int) 274 + #define TARGET_TIOCLINUX _IOW('T', 28, char) 275 + #define TARGET_TIOCCONS _IO('T', 29) 276 + #define TARGET_TIOCGSERIAL 0x803C541E /*_IOR('T', 30, struct serial_struct)*/ 277 + #define TARGET_TIOCSSERIAL 0x403C541F /*_IOW('T', 31, struct serial_struct)*/ 278 + #define TARGET_TIOCPKT _IOW('T', 32, int) 279 + # define TARGET_TIOCPKT_DATA 0 280 + # define TARGET_TIOCPKT_FLUSHREAD 1 281 + # define TARGET_TIOCPKT_FLUSHWRITE 2 282 + # define TARGET_TIOCPKT_STOP 4 283 + # define TARGET_TIOCPKT_START 8 284 + # define TARGET_TIOCPKT_NOSTOP 16 285 + # define TARGET_TIOCPKT_DOSTOP 32 286 + # define TARGET_TIOCPKT_IOCTL 64 287 + 288 + 289 + #define TARGET_TIOCNOTTY _IO('T', 34) 290 + #define TARGET_TIOCSETD _IOW('T', 35, int) 291 + #define TARGET_TIOCGETD _IOR('T', 36, int) 292 + #define TARGET_TCSBRKP _IOW('T', 37, int) /* Needed for POSIX tcsendbreak()*/ 293 + #define TARGET_TIOCSBRK _IO('T', 39) /* BSD compatibility */ 294 + #define TARGET_TIOCCBRK _IO('T', 40) /* BSD compatibility */ 295 + #define TARGET_TIOCGSID _IOR('T', 41, pid_t) /* Return the session ID of FD*/ 296 + #define TARGET_TCGETS2 _IOR('T', 42, struct termios2) 297 + #define TARGET_TCSETS2 _IOW('T', 43, struct termios2) 298 + #define TARGET_TCSETSW2 _IOW('T', 44, struct termios2) 299 + #define TARGET_TCSETSF2 _IOW('T', 45, struct termios2) 300 + #define TARGET_TIOCGRS485 _IOR('T', 46, struct serial_rs485) 301 + #define TARGET_TIOCSRS485 _IOWR('T', 47, struct serial_rs485) 302 + #define TARGET_TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 303 + #define TARGET_TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 304 + #define TARGET_TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ 305 + #define TARGET_TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ 306 + #define TARGET_TIOCVHANGUP _IO('T', 0x37) 307 + #define TARGET_TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */ 308 + #define TARGET_TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ 309 + #define TARGET_TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ 310 + #define TARGET_TIOCGPTPEER _IO('T', 0x41) /* Safely open the slave */ 311 + 312 + #define TARGET_TIOCSERCONFIG _IO('T', 83) 313 + #define TARGET_TIOCSERGWILD _IOR('T', 84, int) 314 + #define TARGET_TIOCSERSWILD _IOW('T', 85, int) 315 + #define TARGET_TIOCGLCKTRMIOS 0x5456 316 + #define TARGET_TIOCSLCKTRMIOS 0x5457 317 + #define TARGET_TIOCSERGSTRUCT 0x5458 /* For debugging only */ 318 + #define TARGET_TIOCSERGETLSR _IOR('T', 89, unsigned int) /* Get line status reg. */ 319 + /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ 320 + # define TARGET_TIOCSER_TEMT 0x01 /* Transmitter physically empty */ 321 + #define TARGET_TIOCSERGETMULTI 0x80a8545a /* Get multiport config */ 322 + /* _IOR('T', 90, struct serial_multiport_struct) */ 323 + #define TARGET_TIOCSERSETMULTI 0x40a8545b /* Set multiport config */ 324 + /* _IOW('T', 91, struct serial_multiport_struct) */ 325 + 326 + #define TARGET_TIOCMIWAIT _IO('T', 92) /* wait for a change on serial input line(s) */ 327 + #define TARGET_TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ 328 + #endif /* _XTENSA_TERMBITS_H */

+1 -2

target/xtensa/Makefile.objs

··· 1 - obj-y += xtensa-semi.o 2 1 obj-y += core-dc232b.o 3 2 obj-y += core-dc233c.o 4 3 obj-y += core-de212.o 5 4 obj-y += core-fsf.o 6 5 obj-y += core-sample_controller.o 7 - obj-$(CONFIG_SOFTMMU) += monitor.o 6 + obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o 8 7 obj-y += xtensa-isa.o 9 8 obj-y += translate.o op_helper.o helper.o cpu.o 10 9 obj-y += gdbstub.o

+22 -4

target/xtensa/cpu.c

··· 45 45 46 46 static bool xtensa_cpu_has_work(CPUState *cs) 47 47 { 48 + #ifndef CONFIG_USER_ONLY 48 49 XtensaCPU *cpu = XTENSA_CPU(cs); 49 50 50 51 return !cpu->env.runstall && cpu->env.pending_irq_level; 52 + #else 53 + return true; 54 + #endif 51 55 } 52 56 53 57 /* CPUClass::reset() */ ··· 62 66 env->exception_taken = 0; 63 67 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 64 68 env->sregs[LITBASE] &= ~1; 69 + #ifndef CONFIG_USER_ONLY 65 70 env->sregs[PS] = xtensa_option_enabled(env->config, 66 71 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 72 + env->pending_irq_level = 0; 73 + #else 74 + env->sregs[PS] = 75 + (xtensa_option_enabled(env->config, 76 + XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) | 77 + PS_UM | (3 << PS_RING_SHIFT); 78 + #endif 67 79 env->sregs[VECBASE] = env->config->vecbase; 68 80 env->sregs[IBREAKENABLE] = 0; 69 81 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; ··· 73 85 env->sregs[CONFIGID0] = env->config->configid[0]; 74 86 env->sregs[CONFIGID1] = env->config->configid[1]; 75 87 76 - env->pending_irq_level = 0; 88 + #ifndef CONFIG_USER_ONLY 77 89 reset_mmu(env); 78 90 s->halted = env->runstall; 91 + #endif 79 92 } 80 93 81 94 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) ··· 104 117 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 105 118 { 106 119 CPUState *cs = CPU(dev); 107 - XtensaCPU *cpu = XTENSA_CPU(dev); 108 120 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 109 121 Error *local_err = NULL; 110 122 111 - xtensa_irq_init(&cpu->env); 123 + #ifndef CONFIG_USER_ONLY 124 + xtensa_irq_init(&XTENSA_CPU(dev)->env); 125 + #endif 112 126 113 127 cpu_exec_realizefn(cs, &local_err); 114 128 if (local_err != NULL) { ··· 133 147 cs->env_ptr = env; 134 148 env->config = xcc->config; 135 149 150 + #ifndef CONFIG_USER_ONLY 136 151 env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 137 152 env->system_er = g_malloc(sizeof(*env->system_er)); 138 153 memory_region_init_io(env->system_er, NULL, NULL, env, "er", 139 154 UINT64_C(0x100000000)); 140 155 address_space_init(env->address_space_er, env->system_er, "ER"); 156 + #endif 141 157 } 142 158 143 159 static const VMStateDescription vmstate_xtensa_cpu = { ··· 166 182 cc->gdb_read_register = xtensa_cpu_gdb_read_register; 167 183 cc->gdb_write_register = xtensa_cpu_gdb_write_register; 168 184 cc->gdb_stop_before_watchpoint = true; 169 - #ifndef CONFIG_USER_ONLY 185 + #ifdef CONFIG_USER_ONLY 186 + cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault; 187 + #else 170 188 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; 171 189 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; 172 190 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;

+37 -19

target/xtensa/cpu.h

··· 44 44 #define NB_MMU_MODES 4 45 45 46 46 #define TARGET_PHYS_ADDR_SPACE_BITS 32 47 + #ifdef CONFIG_USER_ONLY 48 + #define TARGET_VIRT_ADDR_SPACE_BITS 30 49 + #else 47 50 #define TARGET_VIRT_ADDR_SPACE_BITS 32 51 + #endif 48 52 #define TARGET_PAGE_BITS 12 49 53 50 54 enum { ··· 176 180 177 181 #define PS_OWB 0xf00 178 182 #define PS_OWB_SHIFT 8 183 + #define PS_OWB_LEN 4 179 184 180 185 #define PS_CALLINC 0x30000 181 186 #define PS_CALLINC_SHIFT 16 ··· 438 443 } fregs[16]; 439 444 float_status fp_status; 440 445 446 + #ifndef CONFIG_USER_ONLY 441 447 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 442 448 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 443 449 unsigned autorefill_idx; ··· 450 456 uint64_t time_base; 451 457 uint64_t ccount_time; 452 458 uint32_t ccount_base; 459 + #endif 453 460 454 461 int exception_taken; 455 462 int yield_needed; ··· 484 491 485 492 #define ENV_OFFSET offsetof(XtensaCPU, env) 486 493 494 + 495 + int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, 496 + int mmu_idx); 487 497 void xtensa_cpu_do_interrupt(CPUState *cpu); 488 498 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 489 499 void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, ··· 531 541 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); 532 542 void xtensa_sync_window_from_phys(CPUXtensaState *env); 533 543 void xtensa_sync_phys_from_window(CPUXtensaState *env); 534 - uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way); 535 - void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 536 - uint32_t *vpn, uint32_t wi, uint32_t *ei); 537 - int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 538 - uint32_t *pwi, uint32_t *pei, uint8_t *pring); 539 - void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 540 - xtensa_tlb_entry *entry, bool dtlb, 541 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 542 - void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 543 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 544 - int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 545 - uint32_t vaddr, int is_write, int mmu_idx, 546 - uint32_t *paddr, uint32_t *page_size, unsigned *access); 547 - void reset_mmu(CPUXtensaState *env); 548 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); 544 + void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 545 + void xtensa_restore_owb(CPUXtensaState *env); 549 546 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 550 - static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 551 - { 552 - return env->system_er; 553 - } 554 547 555 548 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 556 549 unsigned n) ··· 604 597 } 605 598 } 606 599 600 + #ifndef CONFIG_USER_ONLY 601 + uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 602 + bool dtlb, uint32_t way); 603 + void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 604 + uint32_t *vpn, uint32_t wi, uint32_t *ei); 605 + int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 606 + uint32_t *pwi, uint32_t *pei, uint8_t *pring); 607 + void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 608 + xtensa_tlb_entry *entry, bool dtlb, 609 + unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 610 + void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 611 + unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 612 + int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 613 + uint32_t vaddr, int is_write, int mmu_idx, 614 + uint32_t *paddr, uint32_t *page_size, unsigned *access); 615 + void reset_mmu(CPUXtensaState *env); 616 + void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); 617 + 618 + static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 619 + { 620 + return env->system_er; 621 + } 622 + 607 623 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, 608 624 bool dtlb, unsigned wi, unsigned ei) 609 625 { ··· 611 627 env->dtlb[wi] + ei : 612 628 env->itlb[wi] + ei; 613 629 } 630 + #endif 614 631 615 632 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 616 633 { ··· 623 640 #define MMU_MODE1_SUFFIX _ring1 624 641 #define MMU_MODE2_SUFFIX _ring2 625 642 #define MMU_MODE3_SUFFIX _ring3 643 + #define MMU_USER_IDX 3 626 644 627 645 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 628 646 {

+31

target/xtensa/helper.c

··· 173 173 174 174 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 175 175 { 176 + #ifndef CONFIG_USER_ONLY 176 177 XtensaCPU *cpu = XTENSA_CPU(cs); 177 178 uint32_t paddr; 178 179 uint32_t page_size; ··· 187 188 return paddr; 188 189 } 189 190 return ~0; 191 + #else 192 + return addr; 193 + #endif 190 194 } 195 + 196 + #ifndef CONFIG_USER_ONLY 191 197 192 198 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) 193 199 { ··· 298 304 } 299 305 check_interrupts(env); 300 306 } 307 + #else 308 + void xtensa_cpu_do_interrupt(CPUState *cs) 309 + { 310 + } 311 + #endif 301 312 302 313 bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 303 314 { ··· 308 319 } 309 320 return false; 310 321 } 322 + 323 + #ifdef CONFIG_USER_ONLY 324 + 325 + int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, 326 + int mmu_idx) 327 + { 328 + XtensaCPU *cpu = XTENSA_CPU(cs); 329 + CPUXtensaState *env = &cpu->env; 330 + 331 + qemu_log_mask(CPU_LOG_INT, 332 + "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", 333 + __func__, rw, address, size); 334 + env->sregs[EXCVADDR] = address; 335 + env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE; 336 + cs->exception_index = EXC_USER; 337 + return 1; 338 + } 339 + 340 + #else 311 341 312 342 static void reset_tlb_mmu_all_ways(CPUXtensaState *env, 313 343 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) ··· 769 799 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); 770 800 } 771 801 } 802 + #endif

+4

target/xtensa/helper.h

··· 12 12 DEF_HELPER_2(movsp, void, env, i32) 13 13 DEF_HELPER_2(wsr_lbeg, void, env, i32) 14 14 DEF_HELPER_2(wsr_lend, void, env, i32) 15 + #ifndef CONFIG_USER_ONLY 15 16 DEF_HELPER_1(simcall, void, env) 17 + #endif 16 18 DEF_HELPER_1(dump_state, void, env) 17 19 20 + #ifndef CONFIG_USER_ONLY 18 21 DEF_HELPER_3(waiti, void, env, i32, i32) 19 22 DEF_HELPER_1(update_ccount, void, env) 20 23 DEF_HELPER_2(wsr_ccount, void, env, i32) ··· 35 38 DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32) 36 39 DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32) 37 40 DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32) 41 + #endif 38 42 39 43 DEF_HELPER_2(wur_fcr, void, env, i32) 40 44 DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_NO_RWG_SE, f32, f32)

+41 -9

target/xtensa/op_helper.c

··· 36 36 #include "qemu/timer.h" 37 37 #include "fpu/softfloat.h" 38 38 39 + #ifdef CONFIG_USER_ONLY 40 + /* tb_invalidate_phys_range */ 41 + #include "accel/tcg/translate-all.h" 42 + #endif 43 + 44 + #ifndef CONFIG_USER_ONLY 45 + 39 46 void xtensa_cpu_do_unaligned_access(CPUState *cs, 40 47 vaddr addr, MMUAccessType access_type, 41 48 int mmu_idx, uintptr_t retaddr) ··· 101 108 tb_invalidate_phys_addr(&address_space_memory, paddr); 102 109 } 103 110 } 111 + 112 + #else 113 + 114 + static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) 115 + { 116 + mmap_lock(); 117 + tb_invalidate_phys_range(vaddr, vaddr + 1); 118 + mmap_unlock(); 119 + } 120 + 121 + #endif 104 122 105 123 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) 106 124 { ··· 219 237 copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); 220 238 } 221 239 222 - static void rotate_window_abs(CPUXtensaState *env, uint32_t position) 240 + static void xtensa_rotate_window_abs(CPUXtensaState *env, uint32_t position) 223 241 { 224 242 xtensa_sync_phys_from_window(env); 225 243 env->sregs[WINDOW_BASE] = windowbase_bound(position, env); 226 244 xtensa_sync_window_from_phys(env); 227 245 } 228 246 229 - static void rotate_window(CPUXtensaState *env, uint32_t delta) 247 + void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta) 230 248 { 231 - rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); 249 + xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); 232 250 } 233 251 234 252 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) 235 253 { 236 - rotate_window_abs(env, v); 254 + xtensa_rotate_window_abs(env, v); 237 255 } 238 256 239 257 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) ··· 251 269 HELPER(window_check)(env, pc, callinc); 252 270 } 253 271 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm; 254 - rotate_window(env, callinc); 272 + xtensa_rotate_window(env, callinc); 255 273 env->sregs[WINDOW_START] |= 256 274 windowstart_bit(env->sregs[WINDOW_BASE], env); 257 275 } ··· 266 284 267 285 assert(n <= w); 268 286 269 - rotate_window(env, n); 287 + xtensa_rotate_window(env, n); 270 288 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | 271 289 (windowbase << PS_OWB_SHIFT) | PS_EXCM; 272 290 env->sregs[EPC1] = env->pc = pc; ··· 311 329 312 330 ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); 313 331 314 - rotate_window(env, -n); 332 + xtensa_rotate_window(env, -n); 315 333 if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { 316 334 env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); 317 335 } else { ··· 334 352 335 353 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) 336 354 { 337 - rotate_window(env, imm4); 355 + xtensa_rotate_window(env, imm4); 356 + } 357 + 358 + void xtensa_restore_owb(CPUXtensaState *env) 359 + { 360 + xtensa_rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); 338 361 } 339 362 340 363 void HELPER(restore_owb)(CPUXtensaState *env) 341 364 { 342 - rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); 365 + xtensa_restore_owb(env); 343 366 } 344 367 345 368 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) ··· 375 398 376 399 cpu_dump_state(CPU(cpu), stderr, fprintf, 0); 377 400 } 401 + 402 + #ifndef CONFIG_USER_ONLY 378 403 379 404 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) 380 405 { ··· 888 913 } 889 914 env->sregs[DBREAKC + i] = v; 890 915 } 916 + #endif 891 917 892 918 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) 893 919 { ··· 1025 1051 1026 1052 uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr) 1027 1053 { 1054 + #ifndef CONFIG_USER_ONLY 1028 1055 return address_space_ldl(env->address_space_er, addr, 1029 1056 MEMTXATTRS_UNSPECIFIED, NULL); 1057 + #else 1058 + return 0; 1059 + #endif 1030 1060 } 1031 1061 1032 1062 void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr) 1033 1063 { 1064 + #ifndef CONFIG_USER_ONLY 1034 1065 address_space_stl(env->address_space_er, addr, data, 1035 1066 MEMTXATTRS_UNSPECIFIED, NULL); 1067 + #endif 1036 1068 }

+37 -6

target/xtensa/translate.c

··· 345 345 346 346 static bool gen_check_privilege(DisasContext *dc) 347 347 { 348 - if (dc->cring) { 349 - gen_exception_cause(dc, PRIVILEGED_CAUSE); 350 - dc->is_jmp = DISAS_UPDATE; 351 - return false; 348 + #ifndef CONFIG_USER_ONLY 349 + if (!dc->cring) { 350 + return true; 352 351 } 353 - return true; 352 + #endif 353 + gen_exception_cause(dc, PRIVILEGED_CAUSE); 354 + dc->is_jmp = DISAS_UPDATE; 355 + return false; 354 356 } 355 357 356 358 static bool gen_check_cpenable(DisasContext *dc, unsigned cp) ··· 498 500 return true; 499 501 } 500 502 503 + #ifndef CONFIG_USER_ONLY 501 504 static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) 502 505 { 503 506 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { ··· 519 522 tcg_gen_andi_i32(d, d, 0xfffffffc); 520 523 return false; 521 524 } 525 + #endif 522 526 523 527 static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 524 528 { 525 529 static bool (* const rsr_handler[256])(DisasContext *dc, 526 530 TCGv_i32 d, uint32_t sr) = { 531 + #ifndef CONFIG_USER_ONLY 527 532 [CCOUNT] = gen_rsr_ccount, 528 533 [INTSET] = gen_rsr_ccount, 529 534 [PTEVADDR] = gen_rsr_ptevaddr, 535 + #endif 530 536 }; 531 537 532 538 if (rsr_handler[sr]) { ··· 582 588 return false; 583 589 } 584 590 591 + #ifndef CONFIG_USER_ONLY 585 592 static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) 586 593 { 587 594 gen_helper_wsr_windowbase(cpu_env, v); ··· 797 804 } 798 805 return ret; 799 806 } 807 + #else 808 + static void gen_check_interrupts(DisasContext *dc) 809 + { 810 + } 811 + #endif 800 812 801 813 static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) 802 814 { ··· 808 820 [BR] = gen_wsr_br, 809 821 [LITBASE] = gen_wsr_litbase, 810 822 [ACCHI] = gen_wsr_acchi, 823 + #ifndef CONFIG_USER_ONLY 811 824 [WINDOW_BASE] = gen_wsr_windowbase, 812 825 [WINDOW_START] = gen_wsr_windowstart, 813 826 [PTEVADDR] = gen_wsr_ptevaddr, ··· 834 847 [CCOMPARE] = gen_wsr_ccompare, 835 848 [CCOMPARE + 1] = gen_wsr_ccompare, 836 849 [CCOMPARE + 2] = gen_wsr_ccompare, 850 + #endif 837 851 }; 838 852 839 853 if (wsr_handler[sr]) { ··· 878 892 } 879 893 } 880 894 895 + #ifndef CONFIG_USER_ONLY 881 896 static void gen_waiti(DisasContext *dc, uint32_t imm4) 882 897 { 883 898 TCGv_i32 pc = tcg_const_i32(dc->next_pc); ··· 894 909 tcg_temp_free(intlevel); 895 910 gen_jumpi_check_loop_end(dc, 0); 896 911 } 912 + #endif 897 913 898 914 static bool gen_window_check1(DisasContext *dc, unsigned r1) 899 915 { ··· 1596 1612 { 1597 1613 if ((!par[0] || gen_check_privilege(dc)) && 1598 1614 gen_window_check1(dc, arg[0]) && par[1]) { 1615 + #ifndef CONFIG_USER_ONLY 1599 1616 TCGv_i32 addr = tcg_temp_new_i32(); 1600 1617 1601 1618 tcg_gen_movi_i32(cpu_pc, dc->pc); 1602 1619 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); 1603 1620 gen_helper_itlb_hit_test(cpu_env, addr); 1604 1621 tcg_temp_free(addr); 1622 + #endif 1605 1623 } 1606 1624 } 1607 1625 ··· 1610 1628 { 1611 1629 if (gen_check_privilege(dc) && 1612 1630 gen_window_check1(dc, arg[0])) { 1631 + #ifndef CONFIG_USER_ONLY 1613 1632 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1614 1633 1615 1634 gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); 1616 1635 /* This could change memory mapping, so exit tb */ 1617 1636 gen_jumpi_check_loop_end(dc, -1); 1618 1637 tcg_temp_free(dtlb); 1638 + #endif 1619 1639 } 1620 1640 } 1621 1641 ··· 1985 2005 { 1986 2006 if (gen_check_privilege(dc) && 1987 2007 gen_window_check2(dc, arg[0], arg[1])) { 2008 + #ifndef CONFIG_USER_ONLY 1988 2009 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1989 2010 1990 2011 tcg_gen_movi_i32(cpu_pc, dc->pc); 1991 2012 gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); 1992 2013 tcg_temp_free(dtlb); 2014 + #endif 1993 2015 } 1994 2016 } 1995 2017 ··· 2173 2195 { 2174 2196 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, 2175 2197 TCGv_i32 a2) = { 2198 + #ifndef CONFIG_USER_ONLY 2176 2199 gen_helper_rtlb0, 2177 2200 gen_helper_rtlb1, 2201 + #endif 2178 2202 }; 2179 2203 2180 2204 if (gen_check_privilege(dc) && ··· 2283 2307 static void translate_simcall(DisasContext *dc, const uint32_t arg[], 2284 2308 const uint32_t par[]) 2285 2309 { 2310 + #ifndef CONFIG_USER_ONLY 2286 2311 if (semihosting_enabled()) { 2287 2312 if (gen_check_privilege(dc)) { 2288 2313 gen_helper_simcall(cpu_env); 2289 2314 } 2290 - } else { 2315 + } else 2316 + #endif 2317 + { 2291 2318 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); 2292 2319 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 2293 2320 } ··· 2470 2497 const uint32_t par[]) 2471 2498 { 2472 2499 if (gen_check_privilege(dc)) { 2500 + #ifndef CONFIG_USER_ONLY 2473 2501 gen_waiti(dc, arg[0]); 2502 + #endif 2474 2503 } 2475 2504 } 2476 2505 ··· 2479 2508 { 2480 2509 if (gen_check_privilege(dc) && 2481 2510 gen_window_check2(dc, arg[0], arg[1])) { 2511 + #ifndef CONFIG_USER_ONLY 2482 2512 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2483 2513 2484 2514 gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); 2485 2515 /* This could change memory mapping, so exit tb */ 2486 2516 gen_jumpi_check_loop_end(dc, -1); 2487 2517 tcg_temp_free(dtlb); 2518 + #endif 2488 2519 } 2489 2520 } 2490 2521