jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
The GIC_BASE_IRQ macro is a leftover from when we shared code
between the GICv2 and the v7M NVIC. Since the NVIC is now
split off, GIC_BASE_IRQ is always 0, and we can just delete it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180824161819.11085-1-peter.maydell@linaro.org
+14
-20
+14
-17
hw/intc/arm_gic.c
+14
-17
hw/intc/arm_gic.c
···
955
955
res = 0;
956
956
if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
957
957
/* Every byte offset holds 8 group status bits */
958
-
irq = (offset - 0x080) * 8 + GIC_BASE_IRQ;
958
+
irq = (offset - 0x080) * 8;
959
959
if (irq >= s->num_irq) {
960
960
goto bad_reg;
961
961
}
···
974
974
irq = (offset - 0x100) * 8;
975
975
else
976
976
irq = (offset - 0x180) * 8;
977
-
irq += GIC_BASE_IRQ;
978
977
if (irq >= s->num_irq)
979
978
goto bad_reg;
980
979
res = 0;
···
994
993
irq = (offset - 0x200) * 8;
995
994
else
996
995
irq = (offset - 0x280) * 8;
997
-
irq += GIC_BASE_IRQ;
998
996
if (irq >= s->num_irq)
999
997
goto bad_reg;
1000
998
res = 0;
···
1019
1017
goto bad_reg;
1020
1018
}
1021
1019
1022
-
irq += GIC_BASE_IRQ;
1023
1020
if (irq >= s->num_irq)
1024
1021
goto bad_reg;
1025
1022
res = 0;
···
1036
1033
}
1037
1034
} else if (offset < 0x800) {
1038
1035
/* Interrupt Priority. */
1039
-
irq = (offset - 0x400) + GIC_BASE_IRQ;
1036
+
irq = (offset - 0x400);
1040
1037
if (irq >= s->num_irq)
1041
1038
goto bad_reg;
1042
1039
res = gic_dist_get_priority(s, cpu, irq, attrs);
···
1046
1043
/* For uniprocessor GICs these RAZ/WI */
1047
1044
res = 0;
1048
1045
} else {
1049
-
irq = (offset - 0x800) + GIC_BASE_IRQ;
1046
+
irq = (offset - 0x800);
1050
1047
if (irq >= s->num_irq) {
1051
1048
goto bad_reg;
1052
1049
}
···
1060
1057
}
1061
1058
} else if (offset < 0xf00) {
1062
1059
/* Interrupt Configuration. */
1063
-
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
1060
+
irq = (offset - 0xc00) * 4;
1064
1061
if (irq >= s->num_irq)
1065
1062
goto bad_reg;
1066
1063
res = 0;
···
1183
1180
*/
1184
1181
if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
1185
1182
/* Every byte offset holds 8 group status bits */
1186
-
irq = (offset - 0x80) * 8 + GIC_BASE_IRQ;
1183
+
irq = (offset - 0x80) * 8;
1187
1184
if (irq >= s->num_irq) {
1188
1185
goto bad_reg;
1189
1186
}
···
1204
1201
}
1205
1202
} else if (offset < 0x180) {
1206
1203
/* Interrupt Set Enable. */
1207
-
irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
1204
+
irq = (offset - 0x100) * 8;
1208
1205
if (irq >= s->num_irq)
1209
1206
goto bad_reg;
1210
1207
if (irq < GIC_NR_SGIS) {
···
1239
1236
}
1240
1237
} else if (offset < 0x200) {
1241
1238
/* Interrupt Clear Enable. */
1242
-
irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
1239
+
irq = (offset - 0x180) * 8;
1243
1240
if (irq >= s->num_irq)
1244
1241
goto bad_reg;
1245
1242
if (irq < GIC_NR_SGIS) {
···
1264
1261
}
1265
1262
} else if (offset < 0x280) {
1266
1263
/* Interrupt Set Pending. */
1267
-
irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
1264
+
irq = (offset - 0x200) * 8;
1268
1265
if (irq >= s->num_irq)
1269
1266
goto bad_reg;
1270
1267
if (irq < GIC_NR_SGIS) {
···
1283
1280
}
1284
1281
} else if (offset < 0x300) {
1285
1282
/* Interrupt Clear Pending. */
1286
-
irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
1283
+
irq = (offset - 0x280) * 8;
1287
1284
if (irq >= s->num_irq)
1288
1285
goto bad_reg;
1289
1286
if (irq < GIC_NR_SGIS) {
···
1309
1306
goto bad_reg;
1310
1307
}
1311
1308
1312
-
irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
1309
+
irq = (offset - 0x300) * 8;
1313
1310
if (irq >= s->num_irq) {
1314
1311
goto bad_reg;
1315
1312
}
···
1333
1330
goto bad_reg;
1334
1331
}
1335
1332
1336
-
irq = (offset - 0x380) * 8 + GIC_BASE_IRQ;
1333
+
irq = (offset - 0x380) * 8;
1337
1334
if (irq >= s->num_irq) {
1338
1335
goto bad_reg;
1339
1336
}
···
1353
1350
}
1354
1351
} else if (offset < 0x800) {
1355
1352
/* Interrupt Priority. */
1356
-
irq = (offset - 0x400) + GIC_BASE_IRQ;
1353
+
irq = (offset - 0x400);
1357
1354
if (irq >= s->num_irq)
1358
1355
goto bad_reg;
1359
1356
gic_dist_set_priority(s, cpu, irq, value, attrs);
···
1362
1359
* annoying exception of the 11MPCore's GIC.
1363
1360
*/
1364
1361
if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
1365
-
irq = (offset - 0x800) + GIC_BASE_IRQ;
1362
+
irq = (offset - 0x800);
1366
1363
if (irq >= s->num_irq) {
1367
1364
goto bad_reg;
1368
1365
}
···
1375
1372
}
1376
1373
} else if (offset < 0xf00) {
1377
1374
/* Interrupt Configuration. */
1378
-
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
1375
+
irq = (offset - 0xc00) * 4;
1379
1376
if (irq >= s->num_irq)
1380
1377
goto bad_reg;
1381
1378
if (irq < GIC_NR_SGIS)
-1
hw/intc/arm_gic_common.c
-1
hw/intc/arm_gic_common.c
-2
hw/intc/gic_internal.h
-2
hw/intc/gic_internal.h
···
26
26
27
27
#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
28
28
29
-
#define GIC_BASE_IRQ 0
30
-
31
29
#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
32
30
#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))
33
31
#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)