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qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/intc/arm_gic: Document QEMU interface
The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
etc) is now quite complicated with the addition of the
virtualization extensions. Add a comment in the header
file which documents it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180823103818.31189-1-peter.maydell@linaro.org
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include/hw/intc/arm_gic.h
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include/hw/intc/arm_gic.h
···
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* QEMU interface:
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* + QOM property "num-cpu": number of CPUs to support
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* + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
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* + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
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* + QOM property "has-security-extensions": set true if the GIC should
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* implement the security extensions
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* + QOM property "has-virtualization-extensions": set true if the GIC should
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* implement the virtualization extensions
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* + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
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* [0..P-1] SPIs
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* [P..P+31] PPIs for CPU 0
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* [P+32..P+63] PPIs for CPU 1
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* ...
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* + sysbus IRQs: (in order; number will vary depending on number of cores)
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* - IRQ for CPU 0
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* - IRQ for CPU 1
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* ...
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* - FIQ for CPU 0
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* - FIQ for CPU 1
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* ...
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* - VIRQ for CPU 0 (exists even if virt extensions not present)
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* - VIRQ for CPU 1 (exists even if virt extensions not present)
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* ...
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* - VFIQ for CPU 0 (exists even if virt extensions not present)
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* - VFIQ for CPU 1 (exists even if virt extensions not present)
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* ...
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* - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
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* - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
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* + sysbus MMIO regions: (in order; numbers will vary depending on
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* whether virtualization extensions are present and on number of cores)
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* - distributor registers (GICD*)
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* - CPU interface for the accessing core (GICC*)
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* - virtual interface control registers (GICH*) (only if virt extns present)
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* - virtual CPU interface for the accessing core (GICV*) (only if virt)
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* - CPU 0 CPU interface registers
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* - CPU 1 CPU interface registers
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* ...
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* - CPU 0 virtual interface control registers (only if virt extns present)
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* - CPU 1 virtual interface control registers (only if virt extns present)
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* ...
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*/
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#ifndef HW_ARM_GIC_H
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#define HW_ARM_GIC_H
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