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jcs.org/2018/11/12/vfio
target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree
Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
We already have gvec helpers for addition and subtraction, but must
add one for fabd.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-12-peter.maydell@linaro.org
+48
-15
+2
-1
target/arm/helper.h
+2
-1
target/arm/helper.h
···
396
396
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)
397
397
DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)
398
398
399
-
DEF_HELPER_3(neon_abd_f32, i32, i32, i32, ptr)
400
399
DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)
401
400
DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
402
401
DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
···
594
593
DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
595
594
DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
596
595
DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
596
+
597
+
DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
597
598
598
599
DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,
599
600
void, ptr, ptr, ptr, ptr, i32)
+8
target/arm/neon-dp.decode
+8
target/arm/neon-dp.decode
···
45
45
@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
46
46
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
47
47
48
+
# For FP insns the high bit of 'size' is used as part of opcode decode
49
+
@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
50
+
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
51
+
48
52
VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
49
53
VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
50
54
VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
···
169
173
vm=%vm_dp vn=%vn_dp vd=%vd_dp
170
174
171
175
VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
176
+
177
+
VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
178
+
VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
179
+
VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
-7
target/arm/neon_helper.c
-7
target/arm/neon_helper.c
···
1825
1825
}
1826
1826
1827
1827
/* NEON Float helpers. */
1828
-
uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b, void *fpstp)
1829
-
{
1830
-
float_status *fpst = fpstp;
1831
-
float32 f0 = make_float32(a);
1832
-
float32 f1 = make_float32(b);
1833
-
return float32_val(float32_abs(float32_sub(f0, f1, fpst)));
1834
-
}
1835
1828
1836
1829
/* Floating point comparisons produce an integer result.
1837
1830
* Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.
+28
target/arm/translate-neon.inc.c
+28
target/arm/translate-neon.inc.c
···
1021
1021
1022
1022
DO_3SAME_VQDMULH(VQDMULH, qdmulh)
1023
1023
DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
1024
+
1025
+
/*
1026
+
* For all the functions using this macro, size == 1 means fp16,
1027
+
* which is an architecture extension we don't implement yet.
1028
+
*/
1029
+
#define DO_3S_FP_GVEC(INSN,FUNC) \
1030
+
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
1031
+
uint32_t rn_ofs, uint32_t rm_ofs, \
1032
+
uint32_t oprsz, uint32_t maxsz) \
1033
+
{ \
1034
+
TCGv_ptr fpst = get_fpstatus_ptr(1); \
1035
+
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \
1036
+
oprsz, maxsz, 0, FUNC); \
1037
+
tcg_temp_free_ptr(fpst); \
1038
+
} \
1039
+
static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
1040
+
{ \
1041
+
if (a->size != 0) { \
1042
+
/* TODO fp16 support */ \
1043
+
return false; \
1044
+
} \
1045
+
return do_3same(s, a, gen_##INSN##_3s); \
1046
+
}
1047
+
1048
+
1049
+
DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)
1050
+
DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)
1051
+
DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)
+3
-7
target/arm/translate.c
+3
-7
target/arm/translate.c
···
5445
5445
switch (op) {
5446
5446
case NEON_3R_FLOAT_ARITH:
5447
5447
pairwise = (u && size < 2); /* if VPADD (float) */
5448
+
if (!pairwise) {
5449
+
return 1; /* handled by decodetree */
5450
+
}
5448
5451
break;
5449
5452
case NEON_3R_FLOAT_MINMAX:
5450
5453
pairwise = u; /* if VPMIN/VPMAX (float) */
···
5501
5504
{
5502
5505
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5503
5506
switch ((u << 2) | size) {
5504
-
case 0: /* VADD */
5505
5507
case 4: /* VPADD */
5506
5508
gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
5507
-
break;
5508
-
case 2: /* VSUB */
5509
-
gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus);
5510
-
break;
5511
-
case 6: /* VABD */
5512
-
gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus);
5513
5509
break;
5514
5510
default:
5515
5511
abort();
+7
target/arm/vec_helper.c
+7
target/arm/vec_helper.c
···
691
691
return result;
692
692
}
693
693
694
+
static float32 float32_abd(float32 op1, float32 op2, float_status *stat)
695
+
{
696
+
return float32_abs(float32_sub(op1, op2, stat));
697
+
}
698
+
694
699
#define DO_3OP(NAME, FUNC, TYPE) \
695
700
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
696
701
{ \
···
717
722
DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)
718
723
DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)
719
724
DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)
725
+
726
+
DO_3OP(gvec_fabd_s, float32_abd, float32)
720
727
721
728
#ifdef TARGET_AARCH64
722
729