+1 -1

.travis.yml

··· 327 327 - TEST_CMD="" 328 328 before_script: 329 329 - mkdir -p ${BUILD_DIR} && cd ${BUILD_DIR} 330 330 - - ${SRC_DIR}/configure ${CONFIG} --extra-cflags="-g3 -O0 -Wno-error=stringop-truncation -fsanitize=thread -fuse-ld=gold" || { cat config.log && exit 1; } 330 330 + - ${SRC_DIR}/configure ${CONFIG} --extra-cflags="-g3 -O0 -Wno-error=stringop-truncation -fsanitize=thread" --extra-ldflags="-fuse-ld=gold" || { cat config.log && exit 1; } 331 331 332 332 333 333 # Run check-tcg against linux-user

+2 -2

Makefile

··· 498 498 499 499 .PHONY: dtc/all 500 500 dtc/all: .git-submodule-status dtc/libfdt dtc/tests 501 501 - $(call quiet-command,$(MAKE) $(DTC_MAKE_ARGS) CPPFLAGS="$(DTC_CPPFLAGS)" CFLAGS="$(DTC_CFLAGS)" LDFLAGS="$(LDFLAGS)" ARFLAGS="$(ARFLAGS)" CC="$(CC)" AR="$(AR)" LD="$(LD)" $(SUBDIR_MAKEFLAGS) libfdt/libfdt.a,) 501 501 + $(call quiet-command,$(MAKE) $(DTC_MAKE_ARGS) CPPFLAGS="$(DTC_CPPFLAGS)" CFLAGS="$(DTC_CFLAGS)" LDFLAGS="$(QEMU_LDFLAGS)" ARFLAGS="$(ARFLAGS)" CC="$(CC)" AR="$(AR)" LD="$(LD)" $(SUBDIR_MAKEFLAGS) libfdt/libfdt.a,) 502 502 503 503 dtc/%: .git-submodule-status 504 504 @mkdir -p $@ ··· 525 525 BUILD_DIR="$(BUILD_DIR)/slirp" \ 526 526 PKG_CONFIG="$(PKG_CONFIG)" \ 527 527 CC="$(CC)" AR="$(AR)" LD="$(LD)" RANLIB="$(RANLIB)" \ 528 528 - CFLAGS="$(QEMU_CFLAGS) $(CFLAGS)" LDFLAGS="$(LDFLAGS)") 528 528 + CFLAGS="$(QEMU_CFLAGS) $(CFLAGS)" LDFLAGS="$(QEMU_LDFLAGS)") 529 529 530 530 # Compatibility gunk to keep make working across the rename of targets 531 531 # for recursion, to be removed some time after 4.1.

+10 -21

Makefile.objs

··· 2 2 # Common libraries for tools and emulators 3 3 stub-obj-y = stubs/ 4 4 util-obj-y = crypto/ util/ qobject/ qapi/ 5 5 + qom-obj-y = qom/ 6 6 + 7 7 + ####################################################################### 8 8 + # code used by both qemu system emulation and qemu-img 9 9 + 10 10 + ifeq ($(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)),y) 5 11 6 12 chardev-obj-y = chardev/ 7 13 8 8 - ####################################################################### 9 9 - # authz-obj-y is code used by both qemu system emulation and qemu-img 10 10 - 11 14 authz-obj-y = authz/ 12 12 - 13 13 - ####################################################################### 14 14 - # block-obj-y is code used by both qemu system emulation and qemu-img 15 15 16 16 block-obj-y = nbd/ 17 17 block-obj-y += block.o blockjob.o job.o ··· 21 21 22 22 block-obj-m = block/ 23 23 24 24 - ####################################################################### 25 25 - # crypto-obj-y is code used by both qemu system emulation and qemu-img 26 26 - 27 24 crypto-obj-y = crypto/ 28 25 29 29 - ####################################################################### 30 30 - # qom-obj-y is code used by both qemu system emulation and qemu-img 31 31 - 32 32 - qom-obj-y = qom/ 33 33 - 34 34 - ####################################################################### 35 35 - # io-obj-y is code used by both qemu system emulation and qemu-img 26 26 + io-obj-y = io/ 36 27 37 37 - io-obj-y = io/ 28 28 + endif # CONFIG_SOFTMMU or CONFIG_TOOLS 38 29 39 30 ###################################################################### 40 31 # Target independent part of system emulation. The long term path is to ··· 80 71 81 72 common-obj-$(CONFIG_FDT) += device_tree.o 82 73 83 83 - ###################################################################### 84 84 - # qapi 85 85 - 86 74 common-obj-y += qapi/ 87 87 - endif 75 75 + 76 76 + endif # CONFIG_SOFTMMU 88 77 89 78 ####################################################################### 90 79 # Target-independent parts used in system and user emulation

+5

accel/accel.c

··· 63 63 return ret; 64 64 } 65 65 66 66 + AccelState *current_accel(void) 67 67 + { 68 68 + return current_machine->accelerator; 69 69 + } 70 70 + 66 71 void accel_setup_post(MachineState *ms) 67 72 { 68 73 AccelState *accel = ms->accelerator;

+2 -2

accel/kvm/kvm-all.c

··· 164 164 165 165 int kvm_get_max_memslots(void) 166 166 { 167 167 - KVMState *s = KVM_STATE(current_machine->accelerator); 167 167 + KVMState *s = KVM_STATE(current_accel()); 168 168 169 169 return s->nr_slots; 170 170 } ··· 1848 1848 1849 1849 bool kvm_vcpu_id_is_valid(int vcpu_id) 1850 1850 { 1851 1851 - KVMState *s = KVM_STATE(current_machine->accelerator); 1851 1851 + KVMState *s = KVM_STATE(current_accel()); 1852 1852 return vcpu_id >= 0 && vcpu_id < kvm_max_vcpu_id(s); 1853 1853 } 1854 1854

+4 -4

accel/tcg/tcg-all.c

··· 31 31 #include "sysemu/cpus.h" 32 32 #include "qemu/main-loop.h" 33 33 #include "tcg/tcg.h" 34 34 - #include "include/qapi/error.h" 35 35 - #include "include/qemu/error-report.h" 36 36 - #include "include/hw/boards.h" 34 34 + #include "qapi/error.h" 35 35 + #include "qemu/error-report.h" 36 36 + #include "hw/boards.h" 37 37 #include "qapi/qapi-builtin-visit.h" 38 38 39 39 typedef struct TCGState { ··· 124 124 125 125 static int tcg_init(MachineState *ms) 126 126 { 127 127 - TCGState *s = TCG_STATE(current_machine->accelerator); 127 127 + TCGState *s = TCG_STATE(current_accel()); 128 128 129 129 tcg_exec_init(s->tb_size * 1024 * 1024); 130 130 cpu_interrupt_handler = tcg_handle_interrupt;

+1

audio/audio.c

··· 304 304 switch (as->fmt) { 305 305 case AUDIO_FORMAT_S8: 306 306 sign = 1; 307 307 + /* fall through */ 307 308 case AUDIO_FORMAT_U8: 308 309 mul = 1; 309 310 break;

+33 -30

configure

··· 126 126 compile_prog() { 127 127 local_cflags="$1" 128 128 local_ldflags="$2" 129 129 - do_cc $QEMU_CFLAGS $local_cflags -o $TMPE $TMPC $LDFLAGS $local_ldflags 129 129 + do_cc $QEMU_CFLAGS $local_cflags -o $TMPE $TMPC $QEMU_LDFLAGS $local_ldflags 130 130 } 131 131 132 132 # symbolically link $1 to $2. Portable version of "ln -sf". ··· 523 523 --cpu=*) cpu="$optarg" 524 524 ;; 525 525 --extra-cflags=*) QEMU_CFLAGS="$QEMU_CFLAGS $optarg" 526 526 + QEMU_LDFLAGS="$QEMU_LDFLAGS $optarg" 526 527 ;; 527 528 --extra-cxxflags=*) QEMU_CXXFLAGS="$QEMU_CXXFLAGS $optarg" 528 529 ;; 529 529 - --extra-ldflags=*) LDFLAGS="$LDFLAGS $optarg" 530 530 + --extra-ldflags=*) QEMU_LDFLAGS="$QEMU_LDFLAGS $optarg" 530 531 EXTRA_LDFLAGS="$optarg" 531 532 ;; 532 533 --enable-debug-info) debug_info="yes" ··· 599 600 QEMU_INCLUDES="$QEMU_INCLUDES -iquote \$(SRC_PATH)/disas/libvixl" 600 601 if test "$debug_info" = "yes"; then 601 602 CFLAGS="-g $CFLAGS" 602 602 - LDFLAGS="-g $LDFLAGS" 603 603 fi 604 604 605 605 # running configure in the source tree? ··· 845 845 LDFLAGS_SHARED="-bundle -undefined dynamic_lookup" 846 846 if [ "$cpu" = "x86_64" ] ; then 847 847 QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS" 848 848 - LDFLAGS="-arch x86_64 $LDFLAGS" 848 848 + QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS" 849 849 fi 850 850 cocoa="yes" 851 851 audio_drv_list="coreaudio try-sdl" 852 852 audio_possible_drivers="coreaudio sdl" 853 853 - LDFLAGS="-framework CoreFoundation -framework IOKit $LDFLAGS" 853 853 + QEMU_LDFLAGS="-framework CoreFoundation -framework IOKit $QEMU_LDFLAGS" 854 854 libs_softmmu="-F/System/Library/Frameworks -framework Cocoa -framework IOKit $libs_softmmu" 855 855 # Disable attempts to use ObjectiveC features in os/object.h since they 856 856 # won't work when we're compiling with gcc as a C compiler. ··· 1025 1025 ;; 1026 1026 --static) 1027 1027 static="yes" 1028 1028 - LDFLAGS="-static $LDFLAGS" 1028 1028 + QEMU_LDFLAGS="-static $QEMU_LDFLAGS" 1029 1029 QEMU_PKG_CONFIG_FLAGS="--static $QEMU_PKG_CONFIG_FLAGS" 1030 1030 ;; 1031 1031 --mandir=*) mandir="$optarg" ··· 1551 1551 case "$cpu" in 1552 1552 ppc) 1553 1553 CPU_CFLAGS="-m32" 1554 1554 - LDFLAGS="-m32 $LDFLAGS" 1554 1554 + QEMU_LDFLAGS="-m32 $QEMU_LDFLAGS" 1555 1555 ;; 1556 1556 ppc64) 1557 1557 CPU_CFLAGS="-m64" 1558 1558 - LDFLAGS="-m64 $LDFLAGS" 1558 1558 + QEMU_LDFLAGS="-m64 $QEMU_LDFLAGS" 1559 1559 ;; 1560 1560 sparc) 1561 1561 CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" 1562 1562 - LDFLAGS="-m32 -mv8plus $LDFLAGS" 1562 1562 + QEMU_LDFLAGS="-m32 -mv8plus $QEMU_LDFLAGS" 1563 1563 ;; 1564 1564 sparc64) 1565 1565 CPU_CFLAGS="-m64 -mcpu=ultrasparc" 1566 1566 - LDFLAGS="-m64 $LDFLAGS" 1566 1566 + QEMU_LDFLAGS="-m64 $QEMU_LDFLAGS" 1567 1567 ;; 1568 1568 s390) 1569 1569 CPU_CFLAGS="-m31" 1570 1570 - LDFLAGS="-m31 $LDFLAGS" 1570 1570 + QEMU_LDFLAGS="-m31 $QEMU_LDFLAGS" 1571 1571 ;; 1572 1572 s390x) 1573 1573 CPU_CFLAGS="-m64" 1574 1574 - LDFLAGS="-m64 $LDFLAGS" 1574 1574 + QEMU_LDFLAGS="-m64 $QEMU_LDFLAGS" 1575 1575 ;; 1576 1576 i386) 1577 1577 CPU_CFLAGS="-m32" 1578 1578 - LDFLAGS="-m32 $LDFLAGS" 1578 1578 + QEMU_LDFLAGS="-m32 $QEMU_LDFLAGS" 1579 1579 ;; 1580 1580 x86_64) 1581 1581 # ??? Only extremely old AMD cpus do not have cmpxchg16b. 1582 1582 # If we truly care, we should simply detect this case at 1583 1583 # runtime and generate the fallback to serial emulation. 1584 1584 CPU_CFLAGS="-m64 -mcx16" 1585 1585 - LDFLAGS="-m64 $LDFLAGS" 1585 1585 + QEMU_LDFLAGS="-m64 $QEMU_LDFLAGS" 1586 1586 ;; 1587 1587 x32) 1588 1588 CPU_CFLAGS="-mx32" 1589 1589 - LDFLAGS="-mx32 $LDFLAGS" 1589 1589 + QEMU_LDFLAGS="-mx32 $QEMU_LDFLAGS" 1590 1590 ;; 1591 1591 # No special flags required for other host CPUs 1592 1592 esac ··· 1967 1967 if do_cc $QEMU_CFLAGS -Werror $flag -c -o $TMPO $TMPC && 1968 1968 compile_prog "-Werror $flag" ""; then 1969 1969 QEMU_CFLAGS="$QEMU_CFLAGS $flag" 1970 1970 + QEMU_LDFLAGS="$QEMU_LDFLAGS $flag" 1970 1971 sp_on=1 1971 1972 break 1972 1973 fi ··· 2051 2052 2052 2053 if compile_prog "-fPIE -DPIE" "-pie"; then 2053 2054 QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS" 2054 2054 - LDFLAGS="-pie $LDFLAGS" 2055 2055 + QEMU_LDFLAGS="-pie $QEMU_LDFLAGS" 2055 2056 pie="yes" 2056 2057 if compile_prog "" "-Wl,-z,relro -Wl,-z,now" ; then 2057 2057 - LDFLAGS="-Wl,-z,relro -Wl,-z,now $LDFLAGS" 2058 2058 + QEMU_LDFLAGS="-Wl,-z,relro -Wl,-z,now $QEMU_LDFLAGS" 2058 2059 fi 2059 2060 else 2060 2061 if test "$pie" = "yes"; then ··· 4095 4096 "targets which need it (by specifying a cut down --target-list)." 4096 4097 fi 4097 4098 fdt=yes 4099 4099 + elif test "$fdt" != "yes" ; then 4100 4100 + fdt=no 4098 4101 fi 4099 4102 4100 4103 if test "$fdt" != "no" ; then ··· 5854 5857 hvf='no' 5855 5858 else 5856 5859 hvf='yes' 5857 5857 - LDFLAGS="-framework Hypervisor $LDFLAGS" 5860 5860 + QEMU_LDFLAGS="-framework Hypervisor $QEMU_LDFLAGS" 5858 5861 fi 5859 5862 fi 5860 5863 ··· 6088 6091 write_c_skeleton 6089 6092 6090 6093 if test "$gcov" = "yes" ; then 6091 6091 - CFLAGS="-fprofile-arcs -ftest-coverage -g $CFLAGS" 6092 6092 - LDFLAGS="-fprofile-arcs -ftest-coverage $LDFLAGS" 6094 6094 + QEMU_CFLAGS="-fprofile-arcs -ftest-coverage -g $QEMU_CFLAGS" 6095 6095 + QEMU_LDFLAGS="-fprofile-arcs -ftest-coverage $QEMU_LDFLAGS" 6093 6096 elif test "$fortify_source" = "yes" ; then 6094 6097 CFLAGS="-O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $CFLAGS" 6095 6098 elif test "$debug" = "no"; then ··· 6097 6100 fi 6098 6101 6099 6102 if test "$have_asan" = "yes"; then 6100 6100 - CFLAGS="-fsanitize=address $CFLAGS" 6103 6103 + QEMU_CFLAGS="-fsanitize=address $QEMU_CFLAGS" 6104 6104 + QEMU_LDFLAGS="-fsanitize=address $QEMU_LDFLAGS" 6101 6105 if test "$have_asan_iface_h" = "no" ; then 6102 6106 echo "ASAN build enabled, but ASAN header missing." \ 6103 6107 "Without code annotation, the report may be inferior." ··· 6107 6111 fi 6108 6112 fi 6109 6113 if test "$have_ubsan" = "yes"; then 6110 6110 - CFLAGS="-fsanitize=undefined $CFLAGS" 6114 6114 + QEMU_CFLAGS="-fsanitize=undefined $QEMU_CFLAGS" 6115 6115 + QEMU_LDFLAGS="-fsanitize=undefined $QEMU_LDFLAGS" 6111 6116 fi 6112 6117 6113 6118 ########################################## ··· 6142 6147 6143 6148 if test "$solaris" = "no" ; then 6144 6149 if $ld --version 2>/dev/null | grep "GNU ld" >/dev/null 2>/dev/null ; then 6145 6145 - LDFLAGS="-Wl,--warn-common $LDFLAGS" 6150 6150 + QEMU_LDFLAGS="-Wl,--warn-common $QEMU_LDFLAGS" 6146 6151 fi 6147 6152 fi 6148 6153 ··· 6157 6162 if test "$mingw32" = "yes" ; then 6158 6163 for flag in --dynamicbase --no-seh --nxcompat; do 6159 6164 if ld_has $flag ; then 6160 6160 - LDFLAGS="-Wl,$flag $LDFLAGS" 6165 6165 + QEMU_LDFLAGS="-Wl,$flag $QEMU_LDFLAGS" 6161 6166 fi 6162 6167 done 6163 6168 fi ··· 6392 6397 6393 6398 update_cxxflags 6394 6399 6395 6395 - if do_cxx $QEMU_CXXFLAGS -o $TMPE $TMPCXX $TMPO $LDFLAGS; then 6400 6400 + if do_cxx $QEMU_CXXFLAGS -o $TMPE $TMPCXX $TMPO $QEMU_LDFLAGS; then 6396 6401 # C++ compiler $cxx works ok with C compiler $cc 6397 6402 : 6398 6403 else ··· 6444 6449 echo "ARFLAGS $ARFLAGS" 6445 6450 echo "CFLAGS $CFLAGS" 6446 6451 echo "QEMU_CFLAGS $QEMU_CFLAGS" 6447 6447 - echo "LDFLAGS $LDFLAGS" 6448 6452 echo "QEMU_LDFLAGS $QEMU_LDFLAGS" 6449 6453 echo "make $make" 6450 6454 echo "install $install" ··· 7502 7506 echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak 7503 7507 echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak 7504 7508 fi 7505 7505 - echo "LDFLAGS=$LDFLAGS" >> $config_host_mak 7509 7509 + echo "QEMU_LDFLAGS=$QEMU_LDFLAGS" >> $config_host_mak 7506 7510 echo "LDFLAGS_NOPIE=$LDFLAGS_NOPIE" >> $config_host_mak 7507 7507 - echo "QEMU_LDFLAGS=$QEMU_LDFLAGS" >> $config_host_mak 7508 7511 echo "LD_REL_FLAGS=$LD_REL_FLAGS" >> $config_host_mak 7509 7512 echo "LD_I386_EMULATION=$ld_i386_emulation" >> $config_host_mak 7510 7513 echo "LIBS+=$LIBS" >> $config_host_mak ··· 7830 7833 fi 7831 7834 7832 7835 7833 7833 - # generate QEMU_CFLAGS/LDFLAGS for targets 7836 7836 + # generate QEMU_CFLAGS/QEMU_LDFLAGS for targets 7834 7837 7835 7838 cflags="" 7836 7839 ldflags="" ··· 7951 7954 fi 7952 7955 fi 7953 7956 7954 7954 - echo "LDFLAGS+=$ldflags" >> $config_target_mak 7957 7957 + echo "QEMU_LDFLAGS+=$ldflags" >> $config_target_mak 7955 7958 echo "QEMU_CFLAGS+=$cflags" >> $config_target_mak 7956 7959 7957 7960 done # for target in $targets

+11 -7

docs/specs/pvpanic.txt

··· 16 16 recognized by the device are set. Software should ignore bits it doesn't 17 17 recognize. On write, the bits not recognized by the device are ignored. 18 18 Software should set only bits both itself and the device recognize. 19 19 - Currently, only bit 0 is recognized, setting it indicates a guest panic 20 20 - has happened. 19 19 + 20 20 + Bit Definition 21 21 + -------------- 22 22 + bit 0: a guest panic has happened and should be processed by the host 23 23 + bit 1: a guest panic has happened and will be handled by the guest; 24 24 + the host should record it or report it, but should not affect 25 25 + the execution of the guest. 21 26 22 27 ACPI Interface 23 28 -------------- ··· 26 31 27 32 RDPT: To determine whether guest panic notification is supported. 28 33 Arguments: None 29 29 - Return: Returns a byte, bit 0 set to indicate guest panic 30 30 - notification is supported. Other bits are reserved and 31 31 - should be ignored. 34 34 + Return: Returns a byte, with the same semantics as the I/O port 35 35 + interface. 32 36 33 37 WRPT: To send a guest panic event 34 34 - Arguments: Arg0 is a byte, with bit 0 set to indicate guest panic has 35 35 - happened. Other bits are reserved and should be cleared. 38 38 + Arguments: Arg0 is a byte to be written, with the same semantics as 39 39 + the I/O interface. 36 40 Return: None 37 41 38 42 The ACPI device will automatically refer to the right port in case it

+1 -1

hw/9pfs/virtio-9p-device.c

··· 246 246 DeviceClass *dc = DEVICE_CLASS(klass); 247 247 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 248 248 249 249 - dc->props = virtio_9p_properties; 249 249 + device_class_set_props(dc, virtio_9p_properties); 250 250 dc->vmsd = &vmstate_virtio_9p; 251 251 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 252 252 vdc->realize = virtio_9p_device_realize;

+1 -1

hw/acpi/generic_event_device.c

··· 282 282 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(class); 283 283 284 284 dc->desc = "ACPI Generic Event Device"; 285 285 - dc->props = acpi_ged_properties; 285 285 + device_class_set_props(dc, acpi_ged_properties); 286 286 dc->vmsd = &vmstate_acpi_ged; 287 287 288 288 hc->plug = acpi_ged_device_plug_cb;

+1 -1

hw/acpi/piix4.c

··· 653 653 dc->reset = piix4_pm_reset; 654 654 dc->desc = "PM"; 655 655 dc->vmsd = &vmstate_acpi; 656 656 - dc->props = piix4_pm_properties; 656 656 + device_class_set_props(dc, piix4_pm_properties); 657 657 /* 658 658 * Reason: part of PIIX4 southbridge, needs to be wired up, 659 659 * e.g. by mips_malta_init()

+1 -1

hw/acpi/vmgenid.c

··· 226 226 227 227 dc->vmsd = &vmstate_vmgenid; 228 228 dc->realize = vmgenid_realize; 229 229 - dc->props = vmgenid_device_properties; 229 229 + device_class_set_props(dc, vmgenid_device_properties); 230 230 dc->hotpluggable = false; 231 231 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 232 232 }

+1 -1

hw/arm/armsse.c

··· 1283 1283 1284 1284 dc->realize = armsse_realize; 1285 1285 dc->vmsd = &armsse_vmstate; 1286 1286 - dc->props = info->props; 1286 1286 + device_class_set_props(dc, info->props); 1287 1287 dc->reset = armsse_reset; 1288 1288 iic->check = armsse_idau_check; 1289 1289 asc->info = info;

+2 -2

hw/arm/armv7m.c

··· 288 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 289 290 290 dc->realize = armv7m_realize; 291 291 - dc->props = armv7m_properties; 291 291 + device_class_set_props(dc, armv7m_properties); 292 292 } 293 293 294 294 static const TypeInfo armv7m_info = { ··· 367 367 DeviceClass *dc = DEVICE_CLASS(klass); 368 368 369 369 dc->realize = bitband_realize; 370 370 - dc->props = bitband_properties; 370 370 + device_class_set_props(dc, bitband_properties); 371 371 } 372 372 373 373 static const TypeInfo bitband_info = {

+1 -1

hw/arm/aspeed_soc.c

··· 449 449 dc->realize = aspeed_soc_realize; 450 450 /* Reason: Uses serial_hds and nd_table in realize() directly */ 451 451 dc->user_creatable = false; 452 452 - dc->props = aspeed_soc_properties; 452 452 + device_class_set_props(dc, aspeed_soc_properties); 453 453 } 454 454 455 455 static const TypeInfo aspeed_soc_type_info = {

+1 -1

hw/arm/bcm2836.c

··· 180 180 181 181 bc->info = data; 182 182 dc->realize = bcm2836_realize; 183 183 - dc->props = bcm2836_props; 183 183 + device_class_set_props(dc, bcm2836_props); 184 184 /* Reason: Must be wired up in code (see raspi_init() function) */ 185 185 dc->user_creatable = false; 186 186 }

+1 -1

hw/arm/integratorcp.c

··· 673 673 { 674 674 DeviceClass *dc = DEVICE_CLASS(klass); 675 675 676 676 - dc->props = core_properties; 676 676 + device_class_set_props(dc, core_properties); 677 677 dc->realize = integratorcm_realize; 678 678 dc->vmsd = &vmstate_integratorcm; 679 679 }

+1 -1

hw/arm/msf2-soc.c

··· 229 229 DeviceClass *dc = DEVICE_CLASS(klass); 230 230 231 231 dc->realize = m2sxxx_soc_realize; 232 232 - dc->props = m2sxxx_soc_properties; 232 232 + device_class_set_props(dc, m2sxxx_soc_properties); 233 233 } 234 234 235 235 static const TypeInfo m2sxxx_soc_info = {

+1 -1

hw/arm/musicpal.c

··· 435 435 DeviceClass *dc = DEVICE_CLASS(klass); 436 436 437 437 dc->vmsd = &mv88w8618_eth_vmsd; 438 438 - dc->props = mv88w8618_eth_properties; 438 438 + device_class_set_props(dc, mv88w8618_eth_properties); 439 439 dc->realize = mv88w8618_eth_realize; 440 440 } 441 441

+1 -1

hw/arm/nrf51_soc.c

··· 224 224 DeviceClass *dc = DEVICE_CLASS(klass); 225 225 226 226 dc->realize = nrf51_soc_realize; 227 227 - dc->props = nrf51_soc_properties; 227 227 + device_class_set_props(dc, nrf51_soc_properties); 228 228 } 229 229 230 230 static const TypeInfo nrf51_soc_info = {

+2 -2

hw/arm/pxa2xx.c

··· 1531 1531 1532 1532 dc->desc = "PXA2xx I2C Bus Controller"; 1533 1533 dc->vmsd = &vmstate_pxa2xx_i2c; 1534 1534 - dc->props = pxa2xx_i2c_properties; 1534 1534 + device_class_set_props(dc, pxa2xx_i2c_properties); 1535 1535 } 1536 1536 1537 1537 static const TypeInfo pxa2xx_i2c_info = { ··· 2015 2015 2016 2016 dc->realize = pxa2xx_fir_realize; 2017 2017 dc->vmsd = &pxa2xx_fir_vmsd; 2018 2018 - dc->props = pxa2xx_fir_properties; 2018 2018 + device_class_set_props(dc, pxa2xx_fir_properties); 2019 2019 dc->reset = pxa2xx_fir_reset; 2020 2020 } 2021 2021

+1 -1

hw/arm/pxa2xx_gpio.c

··· 347 347 DeviceClass *dc = DEVICE_CLASS(klass); 348 348 349 349 dc->desc = "PXA2xx GPIO controller"; 350 350 - dc->props = pxa2xx_gpio_properties; 350 350 + device_class_set_props(dc, pxa2xx_gpio_properties); 351 351 dc->vmsd = &vmstate_pxa2xx_gpio_regs; 352 352 dc->realize = pxa2xx_gpio_realize; 353 353 }

+1 -1

hw/arm/smmu-common.c

··· 461 461 DeviceClass *dc = DEVICE_CLASS(klass); 462 462 SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass); 463 463 464 464 - dc->props = smmu_dev_properties; 464 464 + device_class_set_props(dc, smmu_dev_properties); 465 465 device_class_set_parent_realize(dc, smmu_base_realize, 466 466 &sbc->parent_realize); 467 467 dc->reset = smmu_base_reset;

+1 -1

hw/arm/spitz.c

··· 1083 1083 DeviceClass *dc = DEVICE_CLASS(klass); 1084 1084 1085 1085 dc->vmsd = &vmstate_sl_nand_info; 1086 1086 - dc->props = sl_nand_properties; 1086 1086 + device_class_set_props(dc, sl_nand_properties); 1087 1087 dc->realize = sl_nand_realize; 1088 1088 /* Reason: init() method uses drive_get() */ 1089 1089 dc->user_creatable = false;

+1 -1

hw/arm/stm32f205_soc.c

··· 207 207 DeviceClass *dc = DEVICE_CLASS(klass); 208 208 209 209 dc->realize = stm32f205_soc_realize; 210 210 - dc->props = stm32f205_soc_properties; 210 210 + device_class_set_props(dc, stm32f205_soc_properties); 211 211 } 212 212 213 213 static const TypeInfo stm32f205_soc_info = {

+1 -1

hw/arm/stm32f405_soc.c

··· 282 282 DeviceClass *dc = DEVICE_CLASS(klass); 283 283 284 284 dc->realize = stm32f405_soc_realize; 285 285 - dc->props = stm32f405_soc_properties; 285 285 + device_class_set_props(dc, stm32f405_soc_properties); 286 286 /* No vmstate or reset required: device has no internal state */ 287 287 } 288 288

+1 -1

hw/arm/strongarm.c

··· 1327 1327 dc->desc = "StrongARM UART controller"; 1328 1328 dc->reset = strongarm_uart_reset; 1329 1329 dc->vmsd = &vmstate_strongarm_uart_regs; 1330 1330 - dc->props = strongarm_uart_properties; 1330 1330 + device_class_set_props(dc, strongarm_uart_properties); 1331 1331 dc->realize = strongarm_uart_realize; 1332 1332 } 1333 1333

+1 -1

hw/arm/xlnx-versal.c

··· 305 305 DeviceClass *dc = DEVICE_CLASS(klass); 306 306 307 307 dc->realize = versal_realize; 308 308 - dc->props = versal_properties; 308 308 + device_class_set_props(dc, versal_properties); 309 309 /* No VMSD since we haven't got any top-level SoC state to save. */ 310 310 } 311 311

+1 -1

hw/arm/xlnx-zynqmp.c

··· 657 657 { 658 658 DeviceClass *dc = DEVICE_CLASS(oc); 659 659 660 660 - dc->props = xlnx_zynqmp_props; 660 660 + device_class_set_props(dc, xlnx_zynqmp_props); 661 661 dc->realize = xlnx_zynqmp_realize; 662 662 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 663 663 dc->user_creatable = false;

+1 -1

hw/audio/ac97.c

··· 1420 1420 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1421 1421 dc->desc = "Intel 82801AA AC97 Audio"; 1422 1422 dc->vmsd = &vmstate_ac97; 1423 1423 - dc->props = ac97_properties; 1423 1423 + device_class_set_props(dc, ac97_properties); 1424 1424 dc->reset = ac97_on_reset; 1425 1425 } 1426 1426

+1 -1

hw/audio/adlib.c

··· 312 312 dc->realize = adlib_realizefn; 313 313 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 314 314 dc->desc = ADLIB_DESC; 315 315 - dc->props = adlib_properties; 315 315 + device_class_set_props(dc, adlib_properties); 316 316 } 317 317 318 318 static const TypeInfo adlib_info = {

+1 -1

hw/audio/cs4231.c

··· 168 168 169 169 dc->reset = cs_reset; 170 170 dc->vmsd = &vmstate_cs4231; 171 171 - dc->props = cs4231_properties; 171 171 + device_class_set_props(dc, cs4231_properties); 172 172 } 173 173 174 174 static const TypeInfo cs4231_info = {

+1 -1

hw/audio/cs4231a.c

··· 706 706 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 707 707 dc->desc = "Crystal Semiconductor CS4231A"; 708 708 dc->vmsd = &vmstate_cs4231a; 709 709 - dc->props = cs4231a_properties; 709 709 + device_class_set_props(dc, cs4231a_properties); 710 710 } 711 711 712 712 static const TypeInfo cs4231a_info = {

+1 -1

hw/audio/es1370.c

··· 908 908 dc->desc = "ENSONIQ AudioPCI ES1370"; 909 909 dc->vmsd = &vmstate_es1370; 910 910 dc->reset = es1370_on_reset; 911 911 - dc->props = es1370_properties; 911 911 + device_class_set_props(dc, es1370_properties); 912 912 } 913 913 914 914 static const TypeInfo es1370_info = {

+1 -1

hw/audio/gus.c

··· 315 315 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 316 316 dc->desc = "Gravis Ultrasound GF1"; 317 317 dc->vmsd = &vmstate_gus; 318 318 - dc->props = gus_properties; 318 318 + device_class_set_props(dc, gus_properties); 319 319 } 320 320 321 321 static const TypeInfo gus_info = {

+1 -1

hw/audio/hda-codec.c

··· 892 892 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 893 893 dc->reset = hda_audio_reset; 894 894 dc->vmsd = &vmstate_hda_audio; 895 895 - dc->props = hda_audio_properties; 895 895 + device_class_set_props(dc, hda_audio_properties); 896 896 } 897 897 898 898 static const TypeInfo hda_audio_info = {

+2 -2

hw/audio/intel-hda.c

··· 1233 1233 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1234 1234 dc->reset = intel_hda_reset; 1235 1235 dc->vmsd = &vmstate_intel_hda; 1236 1236 - dc->props = intel_hda_properties; 1236 1236 + device_class_set_props(dc, intel_hda_properties); 1237 1237 } 1238 1238 1239 1239 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) ··· 1289 1289 k->unrealize = hda_codec_dev_unrealize; 1290 1290 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1291 1291 k->bus_type = TYPE_HDA_BUS; 1292 1292 - k->props = hda_props; 1292 1292 + device_class_set_props(k, hda_props); 1293 1293 } 1294 1294 1295 1295 static const TypeInfo hda_codec_device_type_info = {

+1 -1

hw/audio/milkymist-ac97.c

··· 342 342 dc->realize = milkymist_ac97_realize; 343 343 dc->reset = milkymist_ac97_reset; 344 344 dc->vmsd = &vmstate_milkymist_ac97; 345 345 - dc->props = milkymist_ac97_properties; 345 345 + device_class_set_props(dc, milkymist_ac97_properties); 346 346 } 347 347 348 348 static const TypeInfo milkymist_ac97_info = {

+1 -1

hw/audio/pcspk.c

··· 222 222 dc->realize = pcspk_realizefn; 223 223 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 224 224 dc->vmsd = &vmstate_spk; 225 225 - dc->props = pcspk_properties; 225 225 + device_class_set_props(dc, pcspk_properties); 226 226 /* Reason: realize sets global pcspk_state */ 227 227 /* Reason: pit object link */ 228 228 dc->user_creatable = false;

+1 -1

hw/audio/pl041.c

··· 640 640 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 641 641 dc->reset = pl041_device_reset; 642 642 dc->vmsd = &vmstate_pl041; 643 643 - dc->props = pl041_device_properties; 643 643 + device_class_set_props(dc, pl041_device_properties); 644 644 } 645 645 646 646 static const TypeInfo pl041_device_info = {

+1 -1

hw/audio/sb16.c

··· 1439 1439 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1440 1440 dc->desc = "Creative Sound Blaster 16"; 1441 1441 dc->vmsd = &vmstate_sb16; 1442 1442 - dc->props = sb16_properties; 1442 1442 + device_class_set_props(dc, sb16_properties); 1443 1443 } 1444 1444 1445 1445 static const TypeInfo sb16_info = {

+1 -1

hw/audio/wm8750.c

··· 717 717 sc->recv = wm8750_rx; 718 718 sc->send = wm8750_tx; 719 719 dc->vmsd = &vmstate_wm8750; 720 720 - dc->props = wm8750_properties; 720 720 + device_class_set_props(dc, wm8750_properties); 721 721 } 722 722 723 723 static const TypeInfo wm8750_info = {

+4 -4

hw/block/fdc.c

··· 606 606 k->realize = floppy_drive_realize; 607 607 set_bit(DEVICE_CATEGORY_STORAGE, k->categories); 608 608 k->bus_type = TYPE_FLOPPY_BUS; 609 609 - k->props = floppy_drive_properties; 609 609 + device_class_set_props(k, floppy_drive_properties); 610 610 k->desc = "virtual floppy drive"; 611 611 } 612 612 ··· 2827 2827 dc->fw_name = "fdc"; 2828 2828 dc->reset = fdctrl_external_reset_isa; 2829 2829 dc->vmsd = &vmstate_isa_fdc; 2830 2830 - dc->props = isa_fdc_properties; 2830 2830 + device_class_set_props(dc, isa_fdc_properties); 2831 2831 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2832 2832 } 2833 2833 ··· 2880 2880 { 2881 2881 DeviceClass *dc = DEVICE_CLASS(klass); 2882 2882 2883 2883 - dc->props = sysbus_fdc_properties; 2883 2883 + device_class_set_props(dc, sysbus_fdc_properties); 2884 2884 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2885 2885 } 2886 2886 ··· 2906 2906 { 2907 2907 DeviceClass *dc = DEVICE_CLASS(klass); 2908 2908 2909 2909 - dc->props = sun4m_fdc_properties; 2909 2909 + device_class_set_props(dc, sun4m_fdc_properties); 2910 2910 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2911 2911 } 2912 2912

+1 -1

hw/block/m25p80.c

··· 1391 1391 k->set_cs = m25p80_cs; 1392 1392 k->cs_polarity = SSI_CS_LOW; 1393 1393 dc->vmsd = &vmstate_m25p80; 1394 1394 - dc->props = m25p80_properties; 1394 1394 + device_class_set_props(dc, m25p80_properties); 1395 1395 dc->reset = m25p80_reset; 1396 1396 mc->pi = data; 1397 1397 }

+1 -1

hw/block/nand.c

··· 448 448 dc->realize = nand_realize; 449 449 dc->reset = nand_reset; 450 450 dc->vmsd = &vmstate_nand; 451 451 - dc->props = nand_properties; 451 451 + device_class_set_props(dc, nand_properties); 452 452 } 453 453 454 454 static const TypeInfo nand_info = {

+1 -1

hw/block/nvme.c

··· 1475 1475 1476 1476 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1477 1477 dc->desc = "Non-Volatile Memory Express"; 1478 1478 - dc->props = nvme_props; 1478 1478 + device_class_set_props(dc, nvme_props); 1479 1479 dc->vmsd = &nvme_vmstate; 1480 1480 } 1481 1481

+1 -1

hw/block/onenand.c

··· 845 845 846 846 dc->realize = onenand_realize; 847 847 dc->reset = onenand_system_reset; 848 848 - dc->props = onenand_properties; 848 848 + device_class_set_props(dc, onenand_properties); 849 849 } 850 850 851 851 static const TypeInfo onenand_info = {

+1 -1

hw/block/pflash_cfi01.c

··· 930 930 931 931 dc->reset = pflash_cfi01_system_reset; 932 932 dc->realize = pflash_cfi01_realize; 933 933 - dc->props = pflash_cfi01_properties; 933 933 + device_class_set_props(dc, pflash_cfi01_properties); 934 934 dc->vmsd = &vmstate_pflash; 935 935 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 936 936 }

+1 -1

hw/block/pflash_cfi02.c

··· 963 963 964 964 dc->realize = pflash_cfi02_realize; 965 965 dc->unrealize = pflash_cfi02_unrealize; 966 966 - dc->props = pflash_cfi02_properties; 966 966 + device_class_set_props(dc, pflash_cfi02_properties); 967 967 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 968 968 } 969 969

+1 -1

hw/block/swim.c

··· 239 239 k->realize = swim_drive_realize; 240 240 set_bit(DEVICE_CATEGORY_STORAGE, k->categories); 241 241 k->bus_type = TYPE_SWIM_BUS; 242 242 - k->props = swim_drive_properties; 242 242 + device_class_set_props(k, swim_drive_properties); 243 243 k->desc = "virtual SWIM drive"; 244 244 } 245 245

+1 -1

hw/block/vhost-user-blk.c

··· 511 511 DeviceClass *dc = DEVICE_CLASS(klass); 512 512 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 513 513 514 514 - dc->props = vhost_user_blk_properties; 514 514 + device_class_set_props(dc, vhost_user_blk_properties); 515 515 dc->vmsd = &vmstate_vhost_user_blk; 516 516 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 517 517 vdc->realize = vhost_user_blk_device_realize;

+1 -1

hw/block/virtio-blk.c

··· 1294 1294 DeviceClass *dc = DEVICE_CLASS(klass); 1295 1295 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 1296 1296 1297 1297 - dc->props = virtio_blk_properties; 1297 1297 + device_class_set_props(dc, virtio_blk_properties); 1298 1298 dc->vmsd = &vmstate_virtio_blk; 1299 1299 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1300 1300 vdc->realize = virtio_blk_device_realize;

+1 -1

hw/block/xen-block.c

··· 554 554 xendev_class->frontend_changed = xen_block_frontend_changed; 555 555 xendev_class->unrealize = xen_block_unrealize; 556 556 557 557 - dev_class->props = xen_block_props; 557 557 + device_class_set_props(dev_class, xen_block_props); 558 558 } 559 559 560 560 static const TypeInfo xen_block_type_info = {

+1 -1

hw/char/bcm2835_aux.c

··· 299 299 dc->realize = bcm2835_aux_realize; 300 300 dc->vmsd = &vmstate_bcm2835_aux; 301 301 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 302 302 - dc->props = bcm2835_aux_props; 302 302 + device_class_set_props(dc, bcm2835_aux_props); 303 303 } 304 304 305 305 static const TypeInfo bcm2835_aux_info = {

+1 -1

hw/char/cadence_uart.c

··· 550 550 dc->realize = cadence_uart_realize; 551 551 dc->vmsd = &vmstate_cadence_uart; 552 552 dc->reset = cadence_uart_reset; 553 553 - dc->props = cadence_uart_properties; 553 553 + device_class_set_props(dc, cadence_uart_properties); 554 554 } 555 555 556 556 static const TypeInfo cadence_uart_info = {

+1 -1

hw/char/cmsdk-apb-uart.c

··· 389 389 dc->realize = cmsdk_apb_uart_realize; 390 390 dc->vmsd = &cmsdk_apb_uart_vmstate; 391 391 dc->reset = cmsdk_apb_uart_reset; 392 392 - dc->props = cmsdk_apb_uart_properties; 392 392 + device_class_set_props(dc, cmsdk_apb_uart_properties); 393 393 } 394 394 395 395 static const TypeInfo cmsdk_apb_uart_info = {

+1 -1

hw/char/debugcon.c

··· 125 125 DeviceClass *dc = DEVICE_CLASS(klass); 126 126 127 127 dc->realize = debugcon_isa_realizefn; 128 128 - dc->props = debugcon_isa_properties; 128 128 + device_class_set_props(dc, debugcon_isa_properties); 129 129 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 130 130 } 131 131

+1 -1

hw/char/digic-uart.c

··· 183 183 dc->realize = digic_uart_realize; 184 184 dc->reset = digic_uart_reset; 185 185 dc->vmsd = &vmstate_digic_uart; 186 186 - dc->props = digic_uart_properties; 186 186 + device_class_set_props(dc, digic_uart_properties); 187 187 } 188 188 189 189 static const TypeInfo digic_uart_info = {

+1 -1

hw/char/escc.c

··· 865 865 dc->reset = escc_reset; 866 866 dc->realize = escc_realize; 867 867 dc->vmsd = &vmstate_escc; 868 868 - dc->props = escc_properties; 868 868 + device_class_set_props(dc, escc_properties); 869 869 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 870 870 } 871 871

+1 -1

hw/char/etraxfs_ser.c

··· 244 244 DeviceClass *dc = DEVICE_CLASS(klass); 245 245 246 246 dc->reset = etraxfs_ser_reset; 247 247 - dc->props = etraxfs_ser_properties; 247 247 + device_class_set_props(dc, etraxfs_ser_properties); 248 248 dc->realize = etraxfs_ser_realize; 249 249 } 250 250

+1 -1

hw/char/exynos4210_uart.c

··· 710 710 711 711 dc->realize = exynos4210_uart_realize; 712 712 dc->reset = exynos4210_uart_reset; 713 713 - dc->props = exynos4210_uart_properties; 713 713 + device_class_set_props(dc, exynos4210_uart_properties); 714 714 dc->vmsd = &vmstate_exynos4210_uart; 715 715 } 716 716

+1 -1

hw/char/grlib_apbuart.c

··· 285 285 286 286 dc->realize = grlib_apbuart_realize; 287 287 dc->reset = grlib_apbuart_reset; 288 288 - dc->props = grlib_apbuart_properties; 288 288 + device_class_set_props(dc, grlib_apbuart_properties); 289 289 } 290 290 291 291 static const TypeInfo grlib_apbuart_info = {

+1 -1

hw/char/imx_serial.c

··· 372 372 dc->reset = imx_serial_reset_at_boot; 373 373 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 374 374 dc->desc = "i.MX series UART"; 375 375 - dc->props = imx_serial_properties; 375 375 + device_class_set_props(dc, imx_serial_properties); 376 376 } 377 377 378 378 static const TypeInfo imx_serial_info = {

+1 -1

hw/char/ipoctal232.c

··· 588 588 589 589 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 590 590 dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack"; 591 591 - dc->props = ipoctal_properties; 591 591 + device_class_set_props(dc, ipoctal_properties); 592 592 dc->vmsd = &vmstate_ipoctal; 593 593 } 594 594

+1 -1

hw/char/lm32_juart.c

··· 146 146 147 147 dc->reset = juart_reset; 148 148 dc->vmsd = &vmstate_lm32_juart; 149 149 - dc->props = lm32_juart_properties; 149 149 + device_class_set_props(dc, lm32_juart_properties); 150 150 dc->realize = lm32_juart_realize; 151 151 } 152 152

+1 -1

hw/char/lm32_uart.c

··· 293 293 294 294 dc->reset = uart_reset; 295 295 dc->vmsd = &vmstate_lm32_uart; 296 296 - dc->props = lm32_uart_properties; 296 296 + device_class_set_props(dc, lm32_uart_properties); 297 297 dc->realize = lm32_uart_realize; 298 298 } 299 299

+1 -1

hw/char/mcf_uart.c

··· 320 320 321 321 dc->realize = mcf_uart_realize; 322 322 dc->reset = mcf_uart_reset; 323 323 - dc->props = mcf_uart_properties; 323 323 + device_class_set_props(dc, mcf_uart_properties); 324 324 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 325 325 } 326 326

+1 -1

hw/char/milkymist-uart.c

··· 239 239 dc->realize = milkymist_uart_realize; 240 240 dc->reset = milkymist_uart_reset; 241 241 dc->vmsd = &vmstate_milkymist_uart; 242 242 - dc->props = milkymist_uart_properties; 242 242 + device_class_set_props(dc, milkymist_uart_properties); 243 243 } 244 244 245 245 static const TypeInfo milkymist_uart_info = {

+1 -1

hw/char/nrf51_uart.c

··· 314 314 315 315 dc->reset = nrf51_uart_reset; 316 316 dc->realize = nrf51_uart_realize; 317 317 - dc->props = nrf51_uart_properties; 317 317 + device_class_set_props(dc, nrf51_uart_properties); 318 318 dc->vmsd = &nrf51_uart_vmstate; 319 319 } 320 320

+1 -1

hw/char/parallel.c

··· 627 627 628 628 dc->realize = parallel_isa_realizefn; 629 629 dc->vmsd = &vmstate_parallel_isa; 630 630 - dc->props = parallel_isa_properties; 630 630 + device_class_set_props(dc, parallel_isa_properties); 631 631 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 632 632 } 633 633

+1 -1

hw/char/pl011.c

··· 356 356 357 357 dc->realize = pl011_realize; 358 358 dc->vmsd = &vmstate_pl011; 359 359 - dc->props = pl011_properties; 359 359 + device_class_set_props(dc, pl011_properties); 360 360 } 361 361 362 362 static const TypeInfo pl011_arm_info = {

+1 -1

hw/char/sclpconsole-lm.c

··· 342 342 DeviceClass *dc = DEVICE_CLASS(klass); 343 343 SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); 344 344 345 345 - dc->props = console_properties; 345 345 + device_class_set_props(dc, console_properties); 346 346 dc->reset = console_reset; 347 347 dc->vmsd = &vmstate_sclplmconsole; 348 348 ec->init = console_init;

+1 -1

hw/char/sclpconsole.c

··· 258 258 DeviceClass *dc = DEVICE_CLASS(klass); 259 259 SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); 260 260 261 261 - dc->props = console_properties; 261 261 + device_class_set_props(dc, console_properties); 262 262 dc->reset = console_reset; 263 263 dc->vmsd = &vmstate_sclpconsole; 264 264 ec->init = console_init;

+1 -1

hw/char/serial-isa.c

··· 106 106 107 107 dc->realize = serial_isa_realizefn; 108 108 dc->vmsd = &vmstate_isa_serial; 109 109 - dc->props = serial_isa_properties; 109 109 + device_class_set_props(dc, serial_isa_properties); 110 110 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 111 111 } 112 112

+2 -2

hw/char/serial-pci-multi.c

··· 161 161 pc->revision = 1; 162 162 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 163 163 dc->vmsd = &vmstate_pci_multi_serial; 164 164 - dc->props = multi_2x_serial_pci_properties; 164 164 + device_class_set_props(dc, multi_2x_serial_pci_properties); 165 165 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 166 166 } 167 167 ··· 176 176 pc->revision = 1; 177 177 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 178 178 dc->vmsd = &vmstate_pci_multi_serial; 179 179 - dc->props = multi_4x_serial_pci_properties; 179 179 + device_class_set_props(dc, multi_4x_serial_pci_properties); 180 180 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 181 181 } 182 182

+1 -1

hw/char/serial-pci.c

··· 100 100 pc->revision = 1; 101 101 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; 102 102 dc->vmsd = &vmstate_pci_serial; 103 103 - dc->props = serial_pci_properties; 103 103 + device_class_set_props(dc, serial_pci_properties); 104 104 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 105 105 } 106 106

+2 -2

hw/char/serial.c

··· 1044 1044 dc->realize = serial_realize; 1045 1045 dc->unrealize = serial_unrealize; 1046 1046 dc->vmsd = &vmstate_serial; 1047 1047 - dc->props = serial_properties; 1047 1047 + device_class_set_props(dc, serial_properties); 1048 1048 } 1049 1049 1050 1050 static const TypeInfo serial_info = { ··· 1159 1159 { 1160 1160 DeviceClass *dc = DEVICE_CLASS(oc); 1161 1161 1162 1162 - dc->props = serial_mm_properties; 1162 1162 + device_class_set_props(dc, serial_mm_properties); 1163 1163 dc->realize = serial_mm_realize; 1164 1164 } 1165 1165

+1 -1

hw/char/spapr_vty.c

··· 193 193 k->dt_type = "serial"; 194 194 k->dt_compatible = "hvterm1"; 195 195 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 196 196 - dc->props = spapr_vty_properties; 196 196 + device_class_set_props(dc, spapr_vty_properties); 197 197 dc->vmsd = &vmstate_spapr_vty; 198 198 } 199 199

+1 -1

hw/char/stm32f2xx_usart.c

··· 222 222 DeviceClass *dc = DEVICE_CLASS(klass); 223 223 224 224 dc->reset = stm32f2xx_usart_reset; 225 225 - dc->props = stm32f2xx_usart_properties; 225 225 + device_class_set_props(dc, stm32f2xx_usart_properties); 226 226 dc->realize = stm32f2xx_usart_realize; 227 227 } 228 228

+1 -1

hw/char/terminal3270.c

··· 288 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 289 EmulatedCcw3270Class *ck = EMULATED_CCW_3270_CLASS(klass); 290 290 291 291 - dc->props = terminal_properties; 291 291 + device_class_set_props(dc, terminal_properties); 292 292 dc->vmsd = &terminal3270_vmstate; 293 293 ck->init = terminal_init; 294 294 ck->read_payload_3270 = read_payload_3270;

+1 -1

hw/char/virtio-console.c

··· 287 287 k->set_guest_connected = set_guest_connected; 288 288 k->enable_backend = virtconsole_enable_backend; 289 289 k->guest_writable = guest_writable; 290 290 - dc->props = virtserialport_properties; 290 290 + device_class_set_props(dc, virtserialport_properties); 291 291 } 292 292 293 293 static const TypeInfo virtserialport_info = {

+2 -2

hw/char/virtio-serial-bus.c

··· 1110 1110 k->bus_type = TYPE_VIRTIO_SERIAL_BUS; 1111 1111 k->realize = virtser_port_device_realize; 1112 1112 k->unrealize = virtser_port_device_unrealize; 1113 1113 - k->props = virtser_props; 1113 1113 + device_class_set_props(k, virtser_props); 1114 1114 } 1115 1115 1116 1116 static const TypeInfo virtio_serial_port_type_info = { ··· 1179 1179 1180 1180 QLIST_INIT(&vserdevices.devices); 1181 1181 1182 1182 - dc->props = virtio_serial_properties; 1182 1182 + device_class_set_props(dc, virtio_serial_properties); 1183 1183 dc->vmsd = &vmstate_virtio_console; 1184 1184 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 1185 1185 vdc->realize = virtio_serial_device_realize;

+1 -1

hw/char/xilinx_uartlite.c

··· 236 236 237 237 dc->reset = xilinx_uartlite_reset; 238 238 dc->realize = xilinx_uartlite_realize; 239 239 - dc->props = xilinx_uartlite_properties; 239 239 + device_class_set_props(dc, xilinx_uartlite_properties); 240 240 } 241 241 242 242 static const TypeInfo xilinx_uartlite_info = {

+16 -15

hw/core/Makefile.objs

··· 1 1 # core qdev-related obj files, also used by *-user: 2 2 common-obj-y += qdev.o qdev-properties.o 3 3 - common-obj-y += bus.o reset.o 4 4 - common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o 5 5 - common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o 3 3 + common-obj-y += bus.o 4 4 + common-obj-y += cpu.o 5 5 + common-obj-y += hotplug.o 6 6 + common-obj-y += vmstate-if.o 6 7 # irq.o needed for qdev GPIO handling: 7 8 common-obj-y += irq.o 8 8 - common-obj-y += hotplug.o 9 9 + 10 10 + common-obj-$(CONFIG_SOFTMMU) += reset.o 11 11 + common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o 12 12 + common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o 9 13 common-obj-$(CONFIG_SOFTMMU) += nmi.o 10 14 common-obj-$(CONFIG_SOFTMMU) += vm-change-state-handler.o 11 11 - common-obj-y += cpu.o 12 12 - common-obj-y += vmstate-if.o 15 15 + common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o 16 16 + common-obj-$(CONFIG_SOFTMMU) += sysbus.o 17 17 + common-obj-$(CONFIG_SOFTMMU) += machine.o 18 18 + common-obj-$(CONFIG_SOFTMMU) += null-machine.o 19 19 + common-obj-$(CONFIG_SOFTMMU) += loader.o 20 20 + common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o 21 21 + obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o 22 22 + obj-$(CONFIG_SOFTMMU) += numa.o 13 23 14 24 common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o 15 25 common-obj-$(CONFIG_XILINX_AXI) += stream.o 16 26 common-obj-$(CONFIG_PTIMER) += ptimer.o 17 17 - common-obj-$(CONFIG_SOFTMMU) += sysbus.o 18 18 - common-obj-$(CONFIG_SOFTMMU) += machine.o 19 19 - common-obj-$(CONFIG_SOFTMMU) += loader.o 20 27 common-obj-$(CONFIG_FITLOADER) += loader-fit.o 21 21 - common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o 22 28 common-obj-$(CONFIG_REGISTER) += register.o 23 29 common-obj-$(CONFIG_OR_IRQ) += or-irq.o 24 30 common-obj-$(CONFIG_SPLIT_IRQ) += split-irq.o 25 31 common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o 26 32 common-obj-$(CONFIG_GENERIC_LOADER) += generic-loader.o 27 27 - common-obj-$(CONFIG_SOFTMMU) += null-machine.o 28 28 - 29 29 - obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o 30 30 - obj-$(CONFIG_SOFTMMU) += numa.o 31 31 - common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o

+9 -1

hw/core/cpu.c

··· 239 239 } 240 240 } 241 241 242 242 + void cpu_class_set_parent_reset(CPUClass *cc, 243 243 + void (*child_reset)(CPUState *cpu), 244 244 + void (**parent_reset)(CPUState *cpu)) 245 245 + { 246 246 + *parent_reset = cc->reset; 247 247 + cc->reset = child_reset; 248 248 + } 249 249 + 242 250 void cpu_reset(CPUState *cpu) 243 251 { 244 252 CPUClass *klass = CPU_GET_CLASS(cpu); ··· 432 440 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 433 441 dc->realize = cpu_common_realizefn; 434 442 dc->unrealize = cpu_common_unrealizefn; 435 435 - dc->props = cpu_common_props; 443 443 + device_class_set_props(dc, cpu_common_props); 436 444 /* 437 445 * Reason: CPUs still need special care by board code: wiring up 438 446 * IRQs, adding reset handlers, halting non-first CPUs, ...

+1 -1

hw/core/generic-loader.c

··· 201 201 */ 202 202 dc->realize = generic_loader_realize; 203 203 dc->unrealize = generic_loader_unrealize; 204 204 - dc->props = generic_loader_props; 204 204 + device_class_set_props(dc, generic_loader_props); 205 205 dc->desc = "Generic Loader"; 206 206 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 207 207 }

+1 -1

hw/core/or-irq.c

··· 125 125 DeviceClass *dc = DEVICE_CLASS(klass); 126 126 127 127 dc->reset = or_irq_reset; 128 128 - dc->props = or_irq_properties; 128 128 + device_class_set_props(dc, or_irq_properties); 129 129 dc->realize = or_irq_realize; 130 130 dc->vmsd = &vmstate_or_irq; 131 131

+1 -1

hw/core/platform-bus.c

··· 211 211 DeviceClass *dc = DEVICE_CLASS(klass); 212 212 213 213 dc->realize = platform_bus_realize; 214 214 - dc->props = platform_bus_properties; 214 214 + device_class_set_props(dc, platform_bus_properties); 215 215 } 216 216 217 217 static const TypeInfo platform_bus_info = {

+18 -22

hw/core/qdev-properties.c

··· 73 73 visit_type_enum(v, prop->name, ptr, prop->info->enum_table, errp); 74 74 } 75 75 76 76 - static void set_default_value_enum(Object *obj, const Property *prop) 76 76 + static void set_default_value_enum(ObjectProperty *op, const Property *prop) 77 77 { 78 78 - object_property_set_str(obj, 79 79 - qapi_enum_lookup(prop->info->enum_table, 80 80 - prop->defval.i), 81 81 - prop->name, &error_abort); 78 78 + object_property_set_default_str(op, 79 79 + qapi_enum_lookup(prop->info->enum_table, prop->defval.i)); 82 80 } 83 81 84 82 /* Bit */ ··· 132 130 bit_prop_set(dev, prop, value); 133 131 } 134 132 135 135 - static void set_default_value_bool(Object *obj, const Property *prop) 133 133 + static void set_default_value_bool(ObjectProperty *op, const Property *prop) 136 134 { 137 137 - object_property_set_bool(obj, prop->defval.u, prop->name, &error_abort); 135 135 + object_property_set_default_bool(op, prop->defval.u); 138 136 } 139 137 140 138 const PropertyInfo qdev_prop_bit = { ··· 265 263 visit_type_uint8(v, name, ptr, errp); 266 264 } 267 265 268 268 - static void set_default_value_int(Object *obj, const Property *prop) 266 266 + static void set_default_value_int(ObjectProperty *op, const Property *prop) 269 267 { 270 270 - object_property_set_int(obj, prop->defval.i, prop->name, &error_abort); 268 268 + object_property_set_default_int(op, prop->defval.i); 271 269 } 272 270 273 273 - static void set_default_value_uint(Object *obj, const Property *prop) 271 271 + static void set_default_value_uint(ObjectProperty *op, const Property *prop) 274 272 { 275 275 - object_property_set_uint(obj, prop->defval.u, prop->name, &error_abort); 273 273 + object_property_set_default_uint(op, prop->defval.u); 276 274 } 277 275 278 276 const PropertyInfo qdev_prop_uint8 = { ··· 925 923 g_free(str); 926 924 } 927 925 928 928 - static void set_default_uuid_auto(Object *obj, const Property *prop) 926 926 + static void set_default_uuid_auto(ObjectProperty *op, const Property *prop) 929 927 { 930 930 - object_property_set_str(obj, UUID_VALUE_AUTO, prop->name, &error_abort); 928 928 + object_property_set_default_str(op, UUID_VALUE_AUTO); 931 929 } 932 930 933 931 const PropertyInfo qdev_prop_uuid = { ··· 1071 1069 /* device properties */ 1072 1070 class = object_get_class(OBJECT(dev)); 1073 1071 do { 1074 1074 - prop = qdev_prop_walk(DEVICE_CLASS(class)->props, name); 1072 1072 + prop = qdev_prop_walk(DEVICE_CLASS(class)->props_, name); 1075 1073 if (prop) { 1076 1074 return prop; 1077 1075 } ··· 1243 1241 1244 1242 /* --- object link property --- */ 1245 1243 1246 1246 - static void create_link_property(Object *obj, Property *prop, Error **errp) 1244 1244 + static void create_link_property(ObjectClass *oc, Property *prop, Error **errp) 1247 1245 { 1248 1248 - Object **child = qdev_get_prop_ptr(DEVICE(obj), prop); 1249 1249 - 1250 1250 - object_property_add_link(obj, prop->name, prop->link_type, 1251 1251 - child, 1252 1252 - qdev_prop_allow_set_link_before_realize, 1253 1253 - OBJ_PROP_LINK_STRONG, 1254 1254 - errp); 1246 1246 + object_class_property_add_link(oc, prop->name, prop->link_type, 1247 1247 + prop->offset, 1248 1248 + qdev_prop_allow_set_link_before_realize, 1249 1249 + OBJ_PROP_LINK_STRONG, 1250 1250 + errp); 1255 1251 } 1256 1252 1257 1253 const PropertyInfo qdev_prop_link = {

+66 -93

hw/core/qdev.c

··· 678 678 } 679 679 680 680 /** 681 681 - * qdev_property_add_legacy: 681 681 + * qdev_class_add_legacy_property: 682 682 * @dev: Device to add the property to. 683 683 * @prop: The qdev property definition. 684 684 - * @errp: location to store error information. 685 684 * 686 685 * Add a legacy QOM property to @dev for qdev property @prop. 687 687 - * On error, store error in @errp. 688 686 * 689 687 * Legacy properties are string versions of QOM properties. The format of 690 688 * the string depends on the property type. Legacy properties are only ··· 693 691 * Do not use this in new code! QOM Properties added through this interface 694 692 * will be given names in the "legacy" namespace. 695 693 */ 696 696 - static void qdev_property_add_legacy(DeviceState *dev, Property *prop, 697 697 - Error **errp) 694 694 + static void qdev_class_add_legacy_property(DeviceClass *dc, Property *prop) 698 695 { 699 699 - gchar *name; 696 696 + g_autofree char *name = NULL; 700 697 701 698 /* Register pointer properties as legacy properties */ 702 699 if (!prop->info->print && prop->info->get) { 703 700 return; 704 701 } 705 702 706 706 - if (prop->info->create) { 707 707 - return; 708 708 - } 709 709 - 710 703 name = g_strdup_printf("legacy-%s", prop->name); 711 711 - object_property_add(OBJECT(dev), name, "str", 712 712 - prop->info->print ? qdev_get_legacy_property : prop->info->get, 713 713 - NULL, 714 714 - NULL, 715 715 - prop, errp); 716 716 - 717 717 - g_free(name); 704 704 + object_class_property_add(OBJECT_CLASS(dc), name, "str", 705 705 + prop->info->print ? qdev_get_legacy_property : prop->info->get, 706 706 + NULL, NULL, prop, &error_abort); 718 707 } 719 708 720 720 - /** 721 721 - * qdev_property_add_static: 722 722 - * @dev: Device to add the property to. 723 723 - * @prop: The qdev property definition. 724 724 - * @errp: location to store error information. 725 725 - * 726 726 - * Add a static QOM property to @dev for qdev property @prop. 727 727 - * On error, store error in @errp. Static properties access data in a struct. 728 728 - * The type of the QOM property is derived from prop->info. 729 729 - */ 730 730 - void qdev_property_add_static(DeviceState *dev, Property *prop, 731 731 - Error **errp) 709 709 + void qdev_property_add_static(DeviceState *dev, Property *prop) 732 710 { 733 733 - Error *local_err = NULL; 734 711 Object *obj = OBJECT(dev); 712 712 + ObjectProperty *op; 735 713 736 736 - if (prop->info->create) { 737 737 - prop->info->create(obj, prop, &local_err); 738 738 - } else { 739 739 - object_property_add(obj, prop->name, prop->info->name, 740 740 - prop->info->get, prop->info->set, 741 741 - prop->info->release, 742 742 - prop, &local_err); 743 743 - } 714 714 + assert(!prop->info->create); 744 715 745 745 - if (local_err) { 746 746 - error_propagate(errp, local_err); 747 747 - return; 748 748 - } 716 716 + op = object_property_add(obj, prop->name, prop->info->name, 717 717 + prop->info->get, prop->info->set, 718 718 + prop->info->release, 719 719 + prop, &error_abort); 749 720 750 721 object_property_set_description(obj, prop->name, 751 722 prop->info->description, 752 723 &error_abort); 753 724 754 725 if (prop->set_default) { 755 755 - prop->info->set_default_value(obj, prop); 726 726 + prop->info->set_default_value(op, prop); 727 727 + if (op->init) { 728 728 + op->init(obj, op); 729 729 + } 756 730 } 757 731 } 758 732 733 733 + static void qdev_class_add_property(DeviceClass *klass, Property *prop) 734 734 + { 735 735 + ObjectClass *oc = OBJECT_CLASS(klass); 736 736 + 737 737 + if (prop->info->create) { 738 738 + prop->info->create(oc, prop, &error_abort); 739 739 + } else { 740 740 + ObjectProperty *op; 741 741 + 742 742 + op = object_class_property_add(oc, 743 743 + prop->name, prop->info->name, 744 744 + prop->info->get, prop->info->set, 745 745 + prop->info->release, 746 746 + prop, &error_abort); 747 747 + if (prop->set_default) { 748 748 + prop->info->set_default_value(op, prop); 749 749 + } 750 750 + } 751 751 + object_class_property_set_description(oc, prop->name, 752 752 + prop->info->description, 753 753 + &error_abort); 754 754 + } 755 755 + 759 756 /* @qdev_alias_all_properties - Add alias properties to the source object for 760 757 * all qdev properties on the target DeviceState. 761 758 */ ··· 768 765 do { 769 766 DeviceClass *dc = DEVICE_CLASS(class); 770 767 771 771 - for (prop = dc->props; prop && prop->name; prop++) { 768 768 + for (prop = dc->props_; prop && prop->name; prop++) { 772 769 object_property_add_alias(source, prop->name, 773 770 OBJECT(target), prop->name, 774 771 &error_abort); 775 772 } 776 773 class = object_class_get_parent(class); 777 774 } while (class != object_class_by_name(TYPE_DEVICE)); 778 778 - } 779 779 - 780 780 - static int qdev_add_hotpluggable_device(Object *obj, void *opaque) 781 781 - { 782 782 - GSList **list = opaque; 783 783 - DeviceState *dev = (DeviceState *)object_dynamic_cast(OBJECT(obj), 784 784 - TYPE_DEVICE); 785 785 - 786 786 - if (dev == NULL) { 787 787 - return 0; 788 788 - } 789 789 - 790 790 - if (dev->realized && object_property_get_bool(obj, "hotpluggable", NULL)) { 791 791 - *list = g_slist_append(*list, dev); 792 792 - } 793 793 - 794 794 - return 0; 795 795 - } 796 796 - 797 797 - GSList *qdev_build_hotpluggable_device_list(Object *peripheral) 798 798 - { 799 799 - GSList *list = NULL; 800 800 - 801 801 - object_child_foreach(peripheral, qdev_add_hotpluggable_device, &list); 802 802 - 803 803 - return list; 804 775 } 805 776 806 777 static bool device_get_realized(Object *obj, Error **errp) ··· 975 946 static void device_initfn(Object *obj) 976 947 { 977 948 DeviceState *dev = DEVICE(obj); 978 978 - ObjectClass *class; 979 979 - Property *prop; 980 949 981 950 if (qdev_hotplug) { 982 951 dev->hotplugged = 1; ··· 987 956 dev->realized = false; 988 957 dev->allow_unplug_during_migration = false; 989 958 990 990 - object_property_add_bool(obj, "realized", 991 991 - device_get_realized, device_set_realized, NULL); 992 992 - object_property_add_bool(obj, "hotpluggable", 993 993 - device_get_hotpluggable, NULL, NULL); 994 994 - object_property_add_bool(obj, "hotplugged", 995 995 - device_get_hotplugged, NULL, 996 996 - &error_abort); 997 997 - 998 998 - class = object_get_class(OBJECT(dev)); 999 999 - do { 1000 1000 - for (prop = DEVICE_CLASS(class)->props; prop && prop->name; prop++) { 1001 1001 - qdev_property_add_legacy(dev, prop, &error_abort); 1002 1002 - qdev_property_add_static(dev, prop, &error_abort); 1003 1003 - } 1004 1004 - class = object_class_get_parent(class); 1005 1005 - } while (class != object_class_by_name(TYPE_DEVICE)); 1006 1006 - 1007 1007 - object_property_add_link(OBJECT(dev), "parent_bus", TYPE_BUS, 1008 1008 - (Object **)&dev->parent_bus, NULL, 0, 1009 1009 - &error_abort); 1010 959 QLIST_INIT(&dev->gpios); 1011 960 } 1012 961 ··· 1056 1005 /* We explicitly look up properties in the superclasses, 1057 1006 * so do not propagate them to the subclasses. 1058 1007 */ 1059 1059 - klass->props = NULL; 1008 1008 + klass->props_ = NULL; 1060 1009 } 1061 1010 1062 1011 static void device_unparent(Object *obj) ··· 1102 1051 dc->hotpluggable = true; 1103 1052 dc->user_creatable = true; 1104 1053 vc->get_id = device_vmstate_if_get_id; 1054 1054 + 1055 1055 + object_class_property_add_bool(class, "realized", 1056 1056 + device_get_realized, device_set_realized, 1057 1057 + &error_abort); 1058 1058 + object_class_property_add_bool(class, "hotpluggable", 1059 1059 + device_get_hotpluggable, NULL, 1060 1060 + &error_abort); 1061 1061 + object_class_property_add_bool(class, "hotplugged", 1062 1062 + device_get_hotplugged, NULL, 1063 1063 + &error_abort); 1064 1064 + object_class_property_add_link(class, "parent_bus", TYPE_BUS, 1065 1065 + offsetof(DeviceState, parent_bus), NULL, 0, 1066 1066 + &error_abort); 1067 1067 + } 1068 1068 + 1069 1069 + void device_class_set_props(DeviceClass *dc, Property *props) 1070 1070 + { 1071 1071 + Property *prop; 1072 1072 + 1073 1073 + dc->props_ = props; 1074 1074 + for (prop = props; prop && prop->name; prop++) { 1075 1075 + qdev_class_add_legacy_property(dc, prop); 1076 1076 + qdev_class_add_property(dc, prop); 1077 1077 + } 1105 1078 } 1106 1079 1107 1080 void device_class_set_parent_reset(DeviceClass *dc,

+1 -1

hw/core/split-irq.c

··· 69 69 DeviceClass *dc = DEVICE_CLASS(klass); 70 70 71 71 /* No state to reset or migrate */ 72 72 - dc->props = split_irq_properties; 72 72 + device_class_set_props(dc, split_irq_properties); 73 73 dc->realize = split_irq_realize; 74 74 75 75 /* Reason: Needs to be wired up to work */

+1 -1

hw/cpu/a15mpcore.c

··· 164 164 DeviceClass *dc = DEVICE_CLASS(klass); 165 165 166 166 dc->realize = a15mp_priv_realize; 167 167 - dc->props = a15mp_priv_properties; 167 167 + device_class_set_props(dc, a15mp_priv_properties); 168 168 /* We currently have no savable state */ 169 169 } 170 170

+1 -1

hw/cpu/a9mpcore.c

··· 175 175 DeviceClass *dc = DEVICE_CLASS(klass); 176 176 177 177 dc->realize = a9mp_priv_realize; 178 178 - dc->props = a9mp_priv_properties; 178 178 + device_class_set_props(dc, a9mp_priv_properties); 179 179 } 180 180 181 181 static const TypeInfo a9mp_priv_info = {

+1 -1

hw/cpu/arm11mpcore.c

··· 156 156 DeviceClass *dc = DEVICE_CLASS(klass); 157 157 158 158 dc->realize = mpcore_priv_realize; 159 159 - dc->props = mpcore_priv_properties; 159 159 + device_class_set_props(dc, mpcore_priv_properties); 160 160 } 161 161 162 162 static const TypeInfo mpcore_priv_info = {

+1 -1

hw/cpu/cluster.c

··· 78 78 { 79 79 DeviceClass *dc = DEVICE_CLASS(klass); 80 80 81 81 - dc->props = cpu_cluster_properties; 81 81 + device_class_set_props(dc, cpu_cluster_properties); 82 82 dc->realize = cpu_cluster_realize; 83 83 84 84 /* This is not directly for users, CPU children must be attached by code */

+1 -1

hw/cpu/realview_mpcore.c

··· 125 125 DeviceClass *dc = DEVICE_CLASS(klass); 126 126 127 127 dc->realize = realview_mpcore_realize; 128 128 - dc->props = mpcore_rirq_properties; 128 128 + device_class_set_props(dc, mpcore_rirq_properties); 129 129 } 130 130 131 131 static const TypeInfo mpcore_rirq_info = {

+1 -1

hw/display/ati.c

··· 980 980 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 981 981 982 982 dc->reset = ati_vga_reset; 983 983 - dc->props = ati_vga_properties; 983 983 + device_class_set_props(dc, ati_vga_properties); 984 984 dc->hotpluggable = false; 985 985 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 986 986

+1 -1

hw/display/bcm2835_fb.c

··· 451 451 { 452 452 DeviceClass *dc = DEVICE_CLASS(klass); 453 453 454 454 - dc->props = bcm2835_fb_props; 454 454 + device_class_set_props(dc, bcm2835_fb_props); 455 455 dc->realize = bcm2835_fb_realize; 456 456 dc->reset = bcm2835_fb_reset; 457 457 dc->vmsd = &vmstate_bcm2835_fb;

+1 -1

hw/display/bochs-display.c

··· 364 364 k->romfile = "vgabios-bochs-display.bin"; 365 365 k->exit = bochs_display_exit; 366 366 dc->vmsd = &vmstate_bochs_display; 367 367 - dc->props = bochs_display_properties; 367 367 + device_class_set_props(dc, bochs_display_properties); 368 368 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 369 369 } 370 370

+1 -1

hw/display/cg3.c

··· 382 382 dc->realize = cg3_realizefn; 383 383 dc->reset = cg3_reset; 384 384 dc->vmsd = &vmstate_cg3; 385 385 - dc->props = cg3_properties; 385 385 + device_class_set_props(dc, cg3_properties); 386 386 } 387 387 388 388 static const TypeInfo cg3_info = {

+1 -1

hw/display/cirrus_vga.c

··· 3031 3031 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 3032 3032 dc->desc = "Cirrus CLGD 54xx VGA"; 3033 3033 dc->vmsd = &vmstate_pci_cirrus_vga; 3034 3034 - dc->props = pci_vga_cirrus_properties; 3034 3034 + device_class_set_props(dc, pci_vga_cirrus_properties); 3035 3035 dc->hotpluggable = false; 3036 3036 } 3037 3037

+1 -1

hw/display/cirrus_vga_isa.c

··· 80 80 81 81 dc->vmsd = &vmstate_cirrus_vga; 82 82 dc->realize = isa_cirrus_vga_realizefn; 83 83 - dc->props = isa_cirrus_vga_properties; 83 83 + device_class_set_props(dc, isa_cirrus_vga_properties); 84 84 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 85 85 } 86 86

+1 -1

hw/display/g364fb.c

··· 526 526 dc->desc = "G364 framebuffer"; 527 527 dc->reset = g364fb_sysbus_reset; 528 528 dc->vmsd = &vmstate_g364fb; 529 529 - dc->props = g364fb_sysbus_properties; 529 529 + device_class_set_props(dc, g364fb_sysbus_properties); 530 530 } 531 531 532 532 static const TypeInfo g364fb_sysbus_info = {

+1 -1

hw/display/i2c-ddc.c

··· 107 107 108 108 dc->reset = i2c_ddc_reset; 109 109 dc->vmsd = &vmstate_i2c_ddc; 110 110 - dc->props = i2c_ddc_properties; 110 110 + device_class_set_props(dc, i2c_ddc_properties); 111 111 isc->event = i2c_ddc_event; 112 112 isc->recv = i2c_ddc_rx; 113 113 isc->send = i2c_ddc_tx;

+2 -2

hw/display/macfb.c

··· 437 437 dc->desc = "SysBus Macintosh framebuffer"; 438 438 dc->reset = macfb_sysbus_reset; 439 439 dc->vmsd = &vmstate_macfb; 440 440 - dc->props = macfb_sysbus_properties; 440 440 + device_class_set_props(dc, macfb_sysbus_properties); 441 441 } 442 442 443 443 static void macfb_nubus_class_init(ObjectClass *klass, void *data) ··· 450 450 dc->desc = "Nubus Macintosh framebuffer"; 451 451 dc->reset = macfb_nubus_reset; 452 452 dc->vmsd = &vmstate_macfb; 453 453 - dc->props = macfb_nubus_properties; 453 453 + device_class_set_props(dc, macfb_nubus_properties); 454 454 } 455 455 456 456 static TypeInfo macfb_sysbus_info = {

+1 -1

hw/display/milkymist-vgafb.c

··· 341 341 342 342 dc->reset = milkymist_vgafb_reset; 343 343 dc->vmsd = &vmstate_milkymist_vgafb; 344 344 - dc->props = milkymist_vgafb_properties; 344 344 + device_class_set_props(dc, milkymist_vgafb_properties); 345 345 dc->realize = milkymist_vgafb_realize; 346 346 } 347 347

+1 -1

hw/display/qxl.c

··· 2478 2478 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2479 2479 dc->reset = qxl_reset_handler; 2480 2480 dc->vmsd = &qxl_vmstate; 2481 2481 - dc->props = qxl_properties; 2481 2481 + device_class_set_props(dc, qxl_properties); 2482 2482 } 2483 2483 2484 2484 static const TypeInfo qxl_pci_type_info = {

+1 -1

hw/display/ramfb-standalone.c

··· 52 52 53 53 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 54 54 dc->realize = ramfb_realizefn; 55 55 - dc->props = ramfb_properties; 55 55 + device_class_set_props(dc, ramfb_properties); 56 56 dc->desc = "ram framebuffer standalone device"; 57 57 dc->user_creatable = true; 58 58 }

+2 -2

hw/display/sm501.c

··· 1995 1995 dc->realize = sm501_realize_sysbus; 1996 1996 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1997 1997 dc->desc = "SM501 Multimedia Companion"; 1998 1998 - dc->props = sm501_sysbus_properties; 1998 1998 + device_class_set_props(dc, sm501_sysbus_properties); 1999 1999 dc->reset = sm501_reset_sysbus; 2000 2000 dc->vmsd = &vmstate_sm501_sysbus; 2001 2001 } ··· 2085 2085 k->class_id = PCI_CLASS_DISPLAY_OTHER; 2086 2086 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 2087 2087 dc->desc = "SM501 Display Controller"; 2088 2088 - dc->props = sm501_pci_properties; 2088 2088 + device_class_set_props(dc, sm501_pci_properties); 2089 2089 dc->reset = sm501_reset_pci; 2090 2090 dc->hotpluggable = false; 2091 2091 dc->vmsd = &vmstate_sm501_pci;

+3 -1

hw/display/tcx.c

··· 410 410 case 2: 411 411 val = s->b[s->dac_index] << 24; 412 412 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 413 413 + /* fall through */ 413 414 default: 414 415 s->dac_state = 0; 415 416 break; ··· 451 452 s->b[index] = val >> 24; 452 453 update_palette_entries(s, index, index + 1); 453 454 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 455 455 + /* fall through */ 454 456 default: 455 457 s->dac_state = 0; 456 458 break; ··· 891 893 dc->realize = tcx_realizefn; 892 894 dc->reset = tcx_reset; 893 895 dc->vmsd = &vmstate_tcx; 894 894 - dc->props = tcx_properties; 896 896 + device_class_set_props(dc, tcx_properties); 895 897 } 896 898 897 899 static const TypeInfo tcx_info = {

+1 -1

hw/display/vga-isa.c

··· 95 95 dc->realize = vga_isa_realizefn; 96 96 dc->reset = vga_isa_reset; 97 97 dc->vmsd = &vmstate_vga_common; 98 98 - dc->props = vga_isa_properties; 98 98 + device_class_set_props(dc, vga_isa_properties); 99 99 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 100 100 } 101 101

+2 -2

hw/display/vga-pci.c

··· 383 383 k->realize = pci_std_vga_realize; 384 384 k->romfile = "vgabios-stdvga.bin"; 385 385 k->class_id = PCI_CLASS_DISPLAY_VGA; 386 386 - dc->props = vga_pci_properties; 386 386 + device_class_set_props(dc, vga_pci_properties); 387 387 dc->hotpluggable = false; 388 388 } 389 389 ··· 395 395 k->realize = pci_secondary_vga_realize; 396 396 k->exit = pci_secondary_vga_exit; 397 397 k->class_id = PCI_CLASS_DISPLAY_OTHER; 398 398 - dc->props = secondary_pci_properties; 398 398 + device_class_set_props(dc, secondary_pci_properties); 399 399 dc->reset = pci_secondary_vga_reset; 400 400 } 401 401

+1 -1

hw/display/vhost-user-gpu.c

··· 588 588 vdc->get_config = vhost_user_gpu_get_config; 589 589 vdc->set_config = vhost_user_gpu_set_config; 590 590 591 591 - dc->props = vhost_user_gpu_properties; 591 591 + device_class_set_props(dc, vhost_user_gpu_properties); 592 592 } 593 593 594 594 static const TypeInfo vhost_user_gpu_info = {

+1 -1

hw/display/virtio-gpu-pci.c

··· 56 56 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 57 57 58 58 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 59 59 - dc->props = virtio_gpu_pci_base_properties; 59 59 + device_class_set_props(dc, virtio_gpu_pci_base_properties); 60 60 dc->hotpluggable = false; 61 61 k->realize = virtio_gpu_pci_base_realize; 62 62 pcidev_k->class_id = PCI_CLASS_DISPLAY_OTHER;

+1 -1

hw/display/virtio-gpu.c

··· 1254 1254 vdc->set_config = virtio_gpu_set_config; 1255 1255 1256 1256 dc->vmsd = &vmstate_virtio_gpu; 1257 1257 - dc->props = virtio_gpu_properties; 1257 1257 + device_class_set_props(dc, virtio_gpu_properties); 1258 1258 } 1259 1259 1260 1260 static const TypeInfo virtio_gpu_info = {

+1 -1

hw/display/virtio-vga.c

··· 184 184 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 185 185 186 186 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 187 187 - dc->props = virtio_vga_base_properties; 187 187 + device_class_set_props(dc, virtio_vga_base_properties); 188 188 dc->vmsd = &vmstate_virtio_vga_base; 189 189 dc->hotpluggable = false; 190 190 device_class_set_parent_reset(dc, virtio_vga_base_reset,

+1 -1

hw/display/vmware_vga.c

··· 1336 1336 k->subsystem_id = SVGA_PCI_DEVICE_ID; 1337 1337 dc->reset = vmsvga_reset; 1338 1338 dc->vmsd = &vmstate_vmware_vga; 1339 1339 - dc->props = vga_vmware_properties; 1339 1339 + device_class_set_props(dc, vga_vmware_properties); 1340 1340 dc->hotpluggable = false; 1341 1341 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1342 1342 }

+1 -1

hw/dma/i82374.c

··· 149 149 150 150 dc->realize = i82374_realize; 151 151 dc->vmsd = &vmstate_i82374; 152 152 - dc->props = i82374_properties; 152 152 + device_class_set_props(dc, i82374_properties); 153 153 } 154 154 155 155 static const TypeInfo i82374_info = {

+1 -1

hw/dma/i8257.c

··· 595 595 dc->realize = i8257_realize; 596 596 dc->reset = i8257_reset; 597 597 dc->vmsd = &vmstate_i8257; 598 598 - dc->props = i8257_properties; 598 598 + device_class_set_props(dc, i8257_properties); 599 599 600 600 idc->get_transfer_mode = i8257_dma_get_transfer_mode; 601 601 idc->has_autoinitialization = i8257_dma_has_autoinitialization;

+1 -1

hw/dma/pl080.c

··· 421 421 422 422 dc->vmsd = &vmstate_pl080; 423 423 dc->realize = pl080_realize; 424 424 - dc->props = pl080_properties; 424 424 + device_class_set_props(dc, pl080_properties); 425 425 dc->reset = pl080_reset; 426 426 } 427 427

+1 -1

hw/dma/pl330.c

··· 1664 1664 1665 1665 dc->realize = pl330_realize; 1666 1666 dc->reset = pl330_reset; 1667 1667 - dc->props = pl330_properties; 1667 1667 + device_class_set_props(dc, pl330_properties); 1668 1668 dc->vmsd = &vmstate_pl330; 1669 1669 } 1670 1670

+1 -1

hw/dma/pxa2xx_dma.c

··· 566 566 567 567 dc->desc = "PXA2xx DMA controller"; 568 568 dc->vmsd = &vmstate_pxa2xx_dma; 569 569 - dc->props = pxa2xx_dma_properties; 569 569 + device_class_set_props(dc, pxa2xx_dma_properties); 570 570 dc->realize = pxa2xx_dma_realize; 571 571 } 572 572

+1 -1

hw/dma/xilinx_axidma.c

··· 599 599 600 600 dc->realize = xilinx_axidma_realize, 601 601 dc->reset = xilinx_axidma_reset; 602 602 - dc->props = axidma_properties; 602 602 + device_class_set_props(dc, axidma_properties); 603 603 } 604 604 605 605 static StreamSlaveClass xilinx_axidma_data_stream_class = {

+1 -1

hw/dma/xlnx-zdma.c

··· 820 820 821 821 dc->reset = zdma_reset; 822 822 dc->realize = zdma_realize; 823 823 - dc->props = zdma_props; 823 823 + device_class_set_props(dc, zdma_props); 824 824 dc->vmsd = &vmstate_zdma; 825 825 } 826 826

+1 -1

hw/gpio/imx_gpio.c

··· 335 335 336 336 dc->realize = imx_gpio_realize; 337 337 dc->reset = imx_gpio_reset; 338 338 - dc->props = imx_gpio_properties; 338 338 + device_class_set_props(dc, imx_gpio_properties); 339 339 dc->vmsd = &vmstate_imx_gpio; 340 340 dc->desc = "i.MX GPIO controller"; 341 341 }

+2 -2

hw/gpio/omap_gpio.c

··· 755 755 756 756 dc->realize = omap_gpio_realize; 757 757 dc->reset = omap_gpif_reset; 758 758 - dc->props = omap_gpio_properties; 758 758 + device_class_set_props(dc, omap_gpio_properties); 759 759 /* Reason: pointer property "clk" */ 760 760 dc->user_creatable = false; 761 761 } ··· 790 790 791 791 dc->realize = omap2_gpio_realize; 792 792 dc->reset = omap2_gpif_reset; 793 793 - dc->props = omap2_gpio_properties; 793 793 + device_class_set_props(dc, omap2_gpio_properties); 794 794 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */ 795 795 dc->user_creatable = false; 796 796 }

+1 -1

hw/i2c/aspeed_i2c.c

··· 832 832 833 833 dc->vmsd = &aspeed_i2c_vmstate; 834 834 dc->reset = aspeed_i2c_reset; 835 835 - dc->props = aspeed_i2c_properties; 835 835 + device_class_set_props(dc, aspeed_i2c_properties); 836 836 dc->realize = aspeed_i2c_realize; 837 837 dc->desc = "Aspeed I2C Controller"; 838 838 }

+1 -1

hw/i2c/core.c

··· 281 281 DeviceClass *k = DEVICE_CLASS(klass); 282 282 set_bit(DEVICE_CATEGORY_MISC, k->categories); 283 283 k->bus_type = TYPE_I2C_BUS; 284 284 - k->props = i2c_props; 284 284 + device_class_set_props(k, i2c_props); 285 285 } 286 286 287 287 static const TypeInfo i2c_slave_type_info = {

+1 -1

hw/i2c/omap_i2c.c

··· 520 520 { 521 521 DeviceClass *dc = DEVICE_CLASS(klass); 522 522 523 523 - dc->props = omap_i2c_properties; 523 523 + device_class_set_props(dc, omap_i2c_properties); 524 524 dc->reset = omap_i2c_reset; 525 525 /* Reason: pointer properties "iclk", "fclk" */ 526 526 dc->user_creatable = false;

+1 -1

hw/i386/intel_iommu.c

··· 3845 3845 3846 3846 dc->reset = vtd_reset; 3847 3847 dc->vmsd = &vtd_vmstate; 3848 3848 - dc->props = vtd_properties; 3848 3848 + device_class_set_props(dc, vtd_properties); 3849 3849 dc->hotpluggable = false; 3850 3850 x86_class->realize = vtd_realize; 3851 3851 x86_class->int_remap = vtd_int_remap;

+1 -1

hw/i386/kvm/clock.c

··· 317 317 318 318 dc->realize = kvmclock_realize; 319 319 dc->vmsd = &kvmclock_vmsd; 320 320 - dc->props = kvmclock_properties; 320 320 + device_class_set_props(dc, kvmclock_properties); 321 321 } 322 322 323 323 static const TypeInfo kvmclock_info = {

+1 -1

hw/i386/kvm/i8254.c

··· 322 322 k->set_channel_gate = kvm_pit_set_gate; 323 323 k->get_channel_info = kvm_pit_get_channel_info; 324 324 dc->reset = kvm_pit_reset; 325 325 - dc->props = kvm_pit_properties; 325 325 + device_class_set_props(dc, kvm_pit_properties); 326 326 } 327 327 328 328 static const TypeInfo kvm_pit_info = {

+1 -1

hw/i386/kvm/ioapic.c

··· 149 149 k->pre_save = kvm_ioapic_get; 150 150 k->post_load = kvm_ioapic_put; 151 151 dc->reset = kvm_ioapic_reset; 152 152 - dc->props = kvm_ioapic_properties; 152 152 + device_class_set_props(dc, kvm_ioapic_properties); 153 153 } 154 154 155 155 static const TypeInfo kvm_ioapic_info = {

+1 -1

hw/i386/vmmouse.c

··· 286 286 dc->realize = vmmouse_realizefn; 287 287 dc->reset = vmmouse_reset; 288 288 dc->vmsd = &vmstate_vmmouse; 289 289 - dc->props = vmmouse_properties; 289 289 + device_class_set_props(dc, vmmouse_properties); 290 290 } 291 291 292 292 static const TypeInfo vmmouse_info = {

+1 -1

hw/i386/x86-iommu.c

··· 153 153 { 154 154 DeviceClass *dc = DEVICE_CLASS(klass); 155 155 dc->realize = x86_iommu_realize; 156 156 - dc->props = x86_iommu_properties; 156 156 + device_class_set_props(dc, x86_iommu_properties); 157 157 } 158 158 159 159 bool x86_iommu_ir_supported(X86IOMMUState *s)

+1 -1

hw/i386/xen/xen_pvdevice.c

··· 131 131 k->realize = xen_pv_realize; 132 132 k->class_id = PCI_CLASS_SYSTEM_OTHER; 133 133 dc->desc = "Xen PV Device"; 134 134 - dc->props = xen_pv_props; 134 134 + device_class_set_props(dc, xen_pv_props); 135 135 dc->vmsd = &vmstate_xen_pvdevice; 136 136 } 137 137

+1 -1

hw/ide/ahci.c

··· 1795 1795 1796 1796 dc->realize = sysbus_ahci_realize; 1797 1797 dc->vmsd = &vmstate_sysbus_ahci; 1798 1798 - dc->props = sysbus_ahci_properties; 1798 1798 + device_class_set_props(dc, sysbus_ahci_properties); 1799 1799 dc->reset = sysbus_ahci_reset; 1800 1800 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1801 1801 }

+1 -1

hw/ide/cmd646.c

··· 347 347 k->class_id = PCI_CLASS_STORAGE_IDE; 348 348 k->config_read = cmd646_pci_config_read; 349 349 k->config_write = cmd646_pci_config_write; 350 350 - dc->props = cmd646_ide_properties; 350 350 + device_class_set_props(dc, cmd646_ide_properties); 351 351 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 352 352 } 353 353

+1 -1

hw/ide/isa.c

··· 117 117 dc->realize = isa_ide_realizefn; 118 118 dc->fw_name = "ide"; 119 119 dc->reset = isa_ide_reset; 120 120 - dc->props = isa_ide_properties; 120 120 + device_class_set_props(dc, isa_ide_properties); 121 121 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 122 122 } 123 123

+1 -1

hw/ide/macio.c

··· 474 474 475 475 dc->realize = macio_ide_realizefn; 476 476 dc->reset = macio_ide_reset; 477 477 - dc->props = macio_ide_properties; 477 477 + device_class_set_props(dc, macio_ide_properties); 478 478 dc->vmsd = &vmstate_pmac; 479 479 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 480 480 }

+1 -1

hw/ide/mmio.c

··· 154 154 155 155 dc->realize = mmio_ide_realizefn; 156 156 dc->reset = mmio_ide_reset; 157 157 - dc->props = mmio_ide_properties; 157 157 + device_class_set_props(dc, mmio_ide_properties); 158 158 dc->vmsd = &vmstate_ide_mmio; 159 159 } 160 160

+4 -4

hw/ide/qdev.c

··· 319 319 k->realize = ide_hd_realize; 320 320 dc->fw_name = "drive"; 321 321 dc->desc = "virtual IDE disk"; 322 322 - dc->props = ide_hd_properties; 322 322 + device_class_set_props(dc, ide_hd_properties); 323 323 } 324 324 325 325 static const TypeInfo ide_hd_info = { ··· 342 342 k->realize = ide_cd_realize; 343 343 dc->fw_name = "drive"; 344 344 dc->desc = "virtual IDE CD-ROM"; 345 345 - dc->props = ide_cd_properties; 345 345 + device_class_set_props(dc, ide_cd_properties); 346 346 } 347 347 348 348 static const TypeInfo ide_cd_info = { ··· 365 365 k->realize = ide_drive_realize; 366 366 dc->fw_name = "drive"; 367 367 dc->desc = "virtual IDE disk or CD-ROM (legacy)"; 368 368 - dc->props = ide_drive_properties; 368 368 + device_class_set_props(dc, ide_drive_properties); 369 369 } 370 370 371 371 static const TypeInfo ide_drive_info = { ··· 381 381 k->realize = ide_qdev_realize; 382 382 set_bit(DEVICE_CATEGORY_STORAGE, k->categories); 383 383 k->bus_type = TYPE_IDE_BUS; 384 384 - k->props = ide_props; 384 384 + device_class_set_props(k, ide_props); 385 385 } 386 386 387 387 static const TypeInfo ide_device_type_info = {

+1 -1

hw/input/adb.c

··· 128 128 DeviceClass *dc = DEVICE_CLASS(oc); 129 129 130 130 dc->realize = adb_device_realizefn; 131 131 - dc->props = adb_device_properties; 131 131 + device_class_set_props(dc, adb_device_properties); 132 132 dc->bus_type = TYPE_ADB_BUS; 133 133 } 134 134

+1 -1

hw/input/milkymist-softusb.c

··· 302 302 dc->realize = milkymist_softusb_realize; 303 303 dc->reset = milkymist_softusb_reset; 304 304 dc->vmsd = &vmstate_milkymist_softusb; 305 305 - dc->props = milkymist_softusb_properties; 305 305 + device_class_set_props(dc, milkymist_softusb_properties); 306 306 } 307 307 308 308 static const TypeInfo milkymist_softusb_info = {

+3 -3

hw/input/virtio-input-hid.c

··· 222 222 DeviceClass *dc = DEVICE_CLASS(klass); 223 223 VirtIOInputClass *vic = VIRTIO_INPUT_CLASS(klass); 224 224 225 225 - dc->props = virtio_input_hid_properties; 225 225 + device_class_set_props(dc, virtio_input_hid_properties); 226 226 vic->realize = virtio_input_hid_realize; 227 227 vic->unrealize = virtio_input_hid_unrealize; 228 228 vic->change_active = virtio_input_hid_change_active; ··· 362 362 { 363 363 DeviceClass *dc = DEVICE_CLASS(klass); 364 364 365 365 - dc->props = virtio_mouse_properties; 365 365 + device_class_set_props(dc, virtio_mouse_properties); 366 366 } 367 367 368 368 static void virtio_mouse_init(Object *obj) ··· 486 486 { 487 487 DeviceClass *dc = DEVICE_CLASS(klass); 488 488 489 489 - dc->props = virtio_tablet_properties; 489 489 + device_class_set_props(dc, virtio_tablet_properties); 490 490 } 491 491 492 492 static void virtio_tablet_init(Object *obj)

+1 -1

hw/input/virtio-input-host.c

··· 226 226 DeviceClass *dc = DEVICE_CLASS(klass); 227 227 228 228 dc->vmsd = &vmstate_virtio_input_host; 229 229 - dc->props = virtio_input_host_properties; 229 229 + device_class_set_props(dc, virtio_input_host_properties); 230 230 vic->realize = virtio_input_host_realize; 231 231 vic->unrealize = virtio_input_host_unrealize; 232 232 vic->handle_status = virtio_input_host_handle_status;

+1 -1

hw/input/virtio-input.c

··· 316 316 DeviceClass *dc = DEVICE_CLASS(klass); 317 317 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 318 318 319 319 - dc->props = virtio_input_properties; 319 319 + device_class_set_props(dc, virtio_input_properties); 320 320 dc->vmsd = &vmstate_virtio_input; 321 321 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 322 322 vdc->realize = virtio_input_device_realize;

+1 -1

hw/intc/apic_common.c

··· 453 453 DeviceClass *dc = DEVICE_CLASS(klass); 454 454 455 455 dc->reset = apic_reset_common; 456 456 - dc->props = apic_properties_common; 456 456 + device_class_set_props(dc, apic_properties_common); 457 457 dc->realize = apic_common_realize; 458 458 dc->unrealize = apic_common_unrealize; 459 459 /*

+1 -1

hw/intc/arm_gic_common.c

··· 367 367 368 368 dc->reset = arm_gic_common_reset; 369 369 dc->realize = arm_gic_common_realize; 370 370 - dc->props = arm_gic_common_properties; 370 370 + device_class_set_props(dc, arm_gic_common_properties); 371 371 dc->vmsd = &vmstate_gic; 372 372 albifc->arm_linux_init = arm_gic_common_linux_init; 373 373 }

+1 -1

hw/intc/arm_gicv2m.c

··· 179 179 { 180 180 DeviceClass *dc = DEVICE_CLASS(klass); 181 181 182 182 - dc->props = gicv2m_properties; 182 182 + device_class_set_props(dc, gicv2m_properties); 183 183 dc->realize = gicv2m_realize; 184 184 } 185 185

+1 -1

hw/intc/arm_gicv3_common.c

··· 507 507 508 508 dc->reset = arm_gicv3_common_reset; 509 509 dc->realize = arm_gicv3_common_realize; 510 510 - dc->props = arm_gicv3_common_properties; 510 510 + device_class_set_props(dc, arm_gicv3_common_properties); 511 511 dc->vmsd = &vmstate_gicv3; 512 512 albifc->arm_linux_init = arm_gic_common_linux_init; 513 513 }

+1 -1

hw/intc/arm_gicv3_its_kvm.c

··· 246 246 KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass); 247 247 248 248 dc->realize = kvm_arm_its_realize; 249 249 - dc->props = kvm_arm_its_props; 249 249 + device_class_set_props(dc, kvm_arm_its_props); 250 250 device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset); 251 251 icc->send_msi = kvm_its_send_msi; 252 252 icc->pre_save = kvm_arm_its_pre_save;

+1 -1

hw/intc/armv7m_nvic.c

··· 2749 2749 DeviceClass *dc = DEVICE_CLASS(klass); 2750 2750 2751 2751 dc->vmsd = &vmstate_nvic; 2752 2752 - dc->props = props_nvic; 2752 2752 + device_class_set_props(dc, props_nvic); 2753 2753 dc->reset = armv7m_nvic_reset; 2754 2754 dc->realize = armv7m_nvic_realize; 2755 2755 }

+1 -1

hw/intc/exynos4210_combiner.c

··· 442 442 DeviceClass *dc = DEVICE_CLASS(klass); 443 443 444 444 dc->reset = exynos4210_combiner_reset; 445 445 - dc->props = exynos4210_combiner_properties; 445 445 + device_class_set_props(dc, exynos4210_combiner_properties); 446 446 dc->vmsd = &vmstate_exynos4210_combiner; 447 447 } 448 448

+2 -2

hw/intc/exynos4210_gic.c

··· 355 355 { 356 356 DeviceClass *dc = DEVICE_CLASS(klass); 357 357 358 358 - dc->props = exynos4210_gic_properties; 358 358 + device_class_set_props(dc, exynos4210_gic_properties); 359 359 dc->realize = exynos4210_gic_realize; 360 360 } 361 361 ··· 462 462 463 463 dc->reset = exynos4210_irq_gate_reset; 464 464 dc->vmsd = &vmstate_exynos4210_irq_gate; 465 465 - dc->props = exynos4210_irq_gate_properties; 465 465 + device_class_set_props(dc, exynos4210_irq_gate_properties); 466 466 dc->realize = exynos4210_irq_gate_realize; 467 467 } 468 468

+1 -1

hw/intc/i8259_common.c

··· 184 184 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); 185 185 186 186 dc->vmsd = &vmstate_pic_common; 187 187 - dc->props = pic_properties_common; 187 187 + device_class_set_props(dc, pic_properties_common); 188 188 dc->realize = pic_common_realize; 189 189 /* 190 190 * Reason: unlike ordinary ISA devices, the PICs need additional

+1 -1

hw/intc/ioapic.c

··· 477 477 */ 478 478 k->post_load = ioapic_update_kvm_routes; 479 479 dc->reset = ioapic_reset_common; 480 480 - dc->props = ioapic_properties; 480 480 + device_class_set_props(dc, ioapic_properties); 481 481 } 482 482 483 483 static const TypeInfo ioapic_info = {

+1 -1

hw/intc/mips_gic.c

··· 448 448 { 449 449 DeviceClass *dc = DEVICE_CLASS(klass); 450 450 451 451 - dc->props = mips_gic_properties; 451 451 + device_class_set_props(dc, mips_gic_properties); 452 452 dc->realize = mips_gic_realize; 453 453 } 454 454

+2 -2

hw/intc/omap_intc.c

··· 407 407 DeviceClass *dc = DEVICE_CLASS(klass); 408 408 409 409 dc->reset = omap_inth_reset; 410 410 - dc->props = omap_intc_properties; 410 410 + device_class_set_props(dc, omap_intc_properties); 411 411 /* Reason: pointer property "clk" */ 412 412 dc->user_creatable = false; 413 413 dc->realize = omap_intc_realize; ··· 660 660 DeviceClass *dc = DEVICE_CLASS(klass); 661 661 662 662 dc->reset = omap_inth_reset; 663 663 - dc->props = omap2_intc_properties; 663 663 + device_class_set_props(dc, omap2_intc_properties); 664 664 /* Reason: pointer property "iclk", "fclk" */ 665 665 dc->user_creatable = false; 666 666 dc->realize = omap2_intc_realize;

+1 -1

hw/intc/ompic.c

··· 161 161 { 162 162 DeviceClass *dc = DEVICE_CLASS(klass); 163 163 164 164 - dc->props = or1k_ompic_properties; 164 164 + device_class_set_props(dc, or1k_ompic_properties); 165 165 dc->realize = or1k_ompic_realize; 166 166 dc->vmsd = &vmstate_or1k_ompic; 167 167 }

+1 -1

hw/intc/openpic.c

··· 1628 1628 DeviceClass *dc = DEVICE_CLASS(oc); 1629 1629 1630 1630 dc->realize = openpic_realize; 1631 1631 - dc->props = openpic_properties; 1631 1631 + device_class_set_props(dc, openpic_properties); 1632 1632 dc->reset = openpic_reset; 1633 1633 dc->vmsd = &vmstate_openpic; 1634 1634 set_bit(DEVICE_CATEGORY_MISC, dc->categories);

+1 -1

hw/intc/openpic_kvm.c

··· 274 274 DeviceClass *dc = DEVICE_CLASS(oc); 275 275 276 276 dc->realize = kvm_openpic_realize; 277 277 - dc->props = kvm_openpic_properties; 277 277 + device_class_set_props(dc, kvm_openpic_properties); 278 278 dc->reset = kvm_openpic_reset; 279 279 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 280 280 }

+1 -1

hw/intc/pnv_xive.c

··· 1957 1957 dc->desc = "PowerNV XIVE Interrupt Controller"; 1958 1958 device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize); 1959 1959 dc->realize = pnv_xive_realize; 1960 1960 - dc->props = pnv_xive_properties; 1960 1960 + device_class_set_props(dc, pnv_xive_properties); 1961 1961 1962 1962 xrc->get_eas = pnv_xive_get_eas; 1963 1963 xrc->get_end = pnv_xive_get_end;

+1 -1

hw/intc/s390_flic.c

··· 427 427 { 428 428 DeviceClass *dc = DEVICE_CLASS(oc); 429 429 430 430 - dc->props = s390_flic_common_properties; 430 430 + device_class_set_props(dc, s390_flic_common_properties); 431 431 dc->realize = s390_flic_common_realize; 432 432 } 433 433

+1 -1

hw/intc/spapr_xive.c

··· 770 770 SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass); 771 771 772 772 dc->desc = "sPAPR XIVE Interrupt Controller"; 773 773 - dc->props = spapr_xive_properties; 773 773 + device_class_set_props(dc, spapr_xive_properties); 774 774 device_class_set_parent_realize(dc, spapr_xive_realize, 775 775 &sxc->parent_realize); 776 776 dc->vmsd = &vmstate_spapr_xive;

+2 -2

hw/intc/xics.c

··· 358 358 359 359 dc->realize = icp_realize; 360 360 dc->unrealize = icp_unrealize; 361 361 - dc->props = icp_properties; 361 361 + device_class_set_props(dc, icp_properties); 362 362 /* 363 363 * Reason: part of XICS interrupt controller, needs to be wired up 364 364 * by icp_create(). ··· 680 680 DeviceClass *dc = DEVICE_CLASS(klass); 681 681 682 682 dc->realize = ics_realize; 683 683 - dc->props = ics_properties; 683 683 + device_class_set_props(dc, ics_properties); 684 684 dc->reset = ics_reset; 685 685 dc->vmsd = &vmstate_ics; 686 686 /*

+1 -1

hw/intc/xilinx_intc.c

··· 185 185 { 186 186 DeviceClass *dc = DEVICE_CLASS(klass); 187 187 188 188 - dc->props = xilinx_intc_properties; 188 188 + device_class_set_props(dc, xilinx_intc_properties); 189 189 } 190 190 191 191 static const TypeInfo xilinx_intc_info = {

+4 -4

hw/intc/xive.c

··· 740 740 dc->desc = "XIVE Interrupt Thread Context"; 741 741 dc->realize = xive_tctx_realize; 742 742 dc->vmsd = &vmstate_xive_tctx; 743 743 - dc->props = xive_tctx_properties; 743 743 + device_class_set_props(dc, xive_tctx_properties); 744 744 /* 745 745 * Reason: part of XIVE interrupt controller, needs to be wired up 746 746 * by xive_tctx_create(). ··· 1192 1192 DeviceClass *dc = DEVICE_CLASS(klass); 1193 1193 1194 1194 dc->desc = "XIVE Interrupt Source"; 1195 1195 - dc->props = xive_source_properties; 1195 1195 + device_class_set_props(dc, xive_source_properties); 1196 1196 dc->realize = xive_source_realize; 1197 1197 dc->vmsd = &vmstate_xive_source; 1198 1198 /* ··· 1736 1736 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1737 1737 1738 1738 dc->desc = "XIVE Router Engine"; 1739 1739 - dc->props = xive_router_properties; 1739 1739 + device_class_set_props(dc, xive_router_properties); 1740 1740 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1741 1741 dc->realize = xive_router_realize; 1742 1742 xnc->notify = xive_router_notify; ··· 1899 1899 DeviceClass *dc = DEVICE_CLASS(klass); 1900 1900 1901 1901 dc->desc = "XIVE END Source"; 1902 1902 - dc->props = xive_end_source_properties; 1902 1902 + device_class_set_props(dc, xive_end_source_properties); 1903 1903 dc->realize = xive_end_source_realize; 1904 1904 /* 1905 1905 * Reason: part of XIVE interrupt controller, needs to be wired up,

+1 -1

hw/intc/xlnx-pmu-iomod-intc.c

··· 539 539 dc->reset = xlnx_pmu_io_intc_reset; 540 540 dc->realize = xlnx_pmu_io_intc_realize; 541 541 dc->vmsd = &vmstate_xlnx_pmu_io_intc; 542 542 - dc->props = xlnx_pmu_io_intc_properties; 542 542 + device_class_set_props(dc, xlnx_pmu_io_intc_properties); 543 543 } 544 544 545 545 static const TypeInfo xlnx_pmu_io_intc_info = {

+1 -1

hw/ipack/ipack.c

··· 88 88 k->bus_type = TYPE_IPACK_BUS; 89 89 k->realize = ipack_device_realize; 90 90 k->unrealize = ipack_device_unrealize; 91 91 - k->props = ipack_device_props; 91 91 + device_class_set_props(k, ipack_device_props); 92 92 } 93 93 94 94 const VMStateDescription vmstate_ipack_device = {

+1 -1

hw/ipmi/ipmi.c

··· 118 118 { 119 119 DeviceClass *dc = DEVICE_CLASS(oc); 120 120 121 121 - dc->props = ipmi_bmc_properties; 121 121 + device_class_set_props(dc, ipmi_bmc_properties); 122 122 } 123 123 124 124 static TypeInfo ipmi_bmc_type_info = {

+1 -1

hw/ipmi/ipmi_bmc_extern.c

··· 528 528 bk->handle_reset = ipmi_bmc_extern_handle_reset; 529 529 dc->hotpluggable = false; 530 530 dc->realize = ipmi_bmc_extern_realize; 531 531 - dc->props = ipmi_bmc_extern_properties; 531 531 + device_class_set_props(dc, ipmi_bmc_extern_properties); 532 532 } 533 533 534 534 static const TypeInfo ipmi_bmc_extern_type = {

+1 -1

hw/ipmi/ipmi_bmc_sim.c

··· 1989 1989 1990 1990 dc->hotpluggable = false; 1991 1991 dc->realize = ipmi_sim_realize; 1992 1992 - dc->props = ipmi_sim_properties; 1992 1992 + device_class_set_props(dc, ipmi_sim_properties); 1993 1993 bk->handle_command = ipmi_sim_handle_command; 1994 1994 } 1995 1995

+1 -1

hw/ipmi/isa_ipmi_bt.c

··· 147 147 IPMIInterfaceClass *iic = IPMI_INTERFACE_CLASS(oc); 148 148 149 149 dc->realize = isa_ipmi_bt_realize; 150 150 - dc->props = ipmi_isa_properties; 150 150 + device_class_set_props(dc, ipmi_isa_properties); 151 151 152 152 iic->get_backend_data = isa_ipmi_bt_get_backend_data; 153 153 ipmi_bt_class_init(iic);

+1 -1

hw/ipmi/isa_ipmi_kcs.c

··· 154 154 IPMIInterfaceClass *iic = IPMI_INTERFACE_CLASS(oc); 155 155 156 156 dc->realize = ipmi_isa_realize; 157 157 - dc->props = ipmi_isa_properties; 157 157 + device_class_set_props(dc, ipmi_isa_properties); 158 158 159 159 iic->get_backend_data = isa_ipmi_kcs_get_backend_data; 160 160 ipmi_kcs_class_init(iic);

+1 -1

hw/isa/lpc_ich9.c

··· 784 784 dc->reset = ich9_lpc_reset; 785 785 k->realize = ich9_lpc_realize; 786 786 dc->vmsd = &vmstate_ich9_lpc; 787 787 - dc->props = ich9_lpc_properties; 787 787 + device_class_set_props(dc, ich9_lpc_properties); 788 788 k->config_write = ich9_lpc_config_write; 789 789 dc->desc = "ICH9 LPC bridge"; 790 790 k->vendor_id = PCI_VENDOR_ID_INTEL;

+1 -1

hw/isa/pc87312.c

··· 342 342 dc->realize = pc87312_realize; 343 343 dc->reset = pc87312_reset; 344 344 dc->vmsd = &vmstate_pc87312; 345 345 - dc->props = pc87312_properties; 345 345 + device_class_set_props(dc, pc87312_properties); 346 346 347 347 sc->parallel = (ISASuperIOFuncs){ 348 348 .count = 1,

+1 -1

hw/isa/vt82c686.c

··· 417 417 dc->desc = "PM"; 418 418 dc->vmsd = &vmstate_acpi; 419 419 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 420 420 - dc->props = via_pm_properties; 420 420 + device_class_set_props(dc, via_pm_properties); 421 421 } 422 422 423 423 static const TypeInfo via_pm_info = {

+1 -1

hw/mem/nvdimm.c

··· 202 202 203 203 ddc->realize = nvdimm_realize; 204 204 mdc->get_memory_region = nvdimm_md_get_memory_region; 205 205 - dc->props = nvdimm_properties; 205 205 + device_class_set_props(dc, nvdimm_properties); 206 206 207 207 nvc->read_label_data = nvdimm_read_label_data; 208 208 nvc->write_label_data = nvdimm_write_label_data;

+1 -1

hw/mem/pc-dimm.c

··· 271 271 272 272 dc->realize = pc_dimm_realize; 273 273 dc->unrealize = pc_dimm_unrealize; 274 274 - dc->props = pc_dimm_properties; 274 274 + device_class_set_props(dc, pc_dimm_properties); 275 275 dc->desc = "DIMM memory module"; 276 276 277 277 ddc->get_vmstate_memory_region = pc_dimm_get_memory_region;

+1 -1

hw/mips/cps.c

··· 178 178 DeviceClass *dc = DEVICE_CLASS(klass); 179 179 180 180 dc->realize = mips_cps_realize; 181 181 - dc->props = mips_cps_properties; 181 181 + device_class_set_props(dc, mips_cps_properties); 182 182 } 183 183 184 184 static const TypeInfo mips_cps_info = {

+1 -1

hw/misc/a9scu.c

··· 135 135 { 136 136 DeviceClass *dc = DEVICE_CLASS(klass); 137 137 138 138 - dc->props = a9_scu_properties; 138 138 + device_class_set_props(dc, a9_scu_properties); 139 139 dc->vmsd = &vmstate_a9_scu; 140 140 dc->reset = a9_scu_reset; 141 141 }

+1 -1

hw/misc/applesmc.c

··· 353 353 354 354 dc->realize = applesmc_isa_realize; 355 355 dc->reset = qdev_applesmc_isa_reset; 356 356 - dc->props = applesmc_isa_properties; 356 356 + device_class_set_props(dc, applesmc_isa_properties); 357 357 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 358 358 } 359 359

+1 -1

hw/misc/arm11scu.c

··· 85 85 DeviceClass *dc = DEVICE_CLASS(oc); 86 86 87 87 dc->realize = arm11_scu_realize; 88 88 - dc->props = arm11_scu_properties; 88 88 + device_class_set_props(dc, arm11_scu_properties); 89 89 } 90 90 91 91 static const TypeInfo arm11_scu_type_info = {

+1 -1

hw/misc/arm_l2x0.c

··· 182 182 DeviceClass *dc = DEVICE_CLASS(klass); 183 183 184 184 dc->vmsd = &vmstate_l2x0; 185 185 - dc->props = l2x0_properties; 185 185 + device_class_set_props(dc, l2x0_properties); 186 186 dc->reset = l2x0_priv_reset; 187 187 } 188 188

+1 -1

hw/misc/arm_sysctl.c

··· 642 642 dc->realize = arm_sysctl_realize; 643 643 dc->reset = arm_sysctl_reset; 644 644 dc->vmsd = &vmstate_arm_sysctl; 645 645 - dc->props = arm_sysctl_properties; 645 645 + device_class_set_props(dc, arm_sysctl_properties); 646 646 } 647 647 648 648 static const TypeInfo arm_sysctl_info = {

+1 -1

hw/misc/armsse-cpuid.c

··· 116 116 * does not need a reset function or VMState. 117 117 */ 118 118 119 119 - dc->props = armsse_cpuid_props; 119 119 + device_class_set_props(dc, armsse_cpuid_props); 120 120 } 121 121 122 122 static const TypeInfo armsse_cpuid_info = {

+1 -1

hw/misc/aspeed_scu.c

··· 447 447 dc->reset = aspeed_scu_reset; 448 448 dc->desc = "ASPEED System Control Unit"; 449 449 dc->vmsd = &vmstate_aspeed_scu; 450 450 - dc->props = aspeed_scu_properties; 450 450 + device_class_set_props(dc, aspeed_scu_properties); 451 451 } 452 452 453 453 static const TypeInfo aspeed_scu_info = {

+1 -1

hw/misc/aspeed_sdmc.c

··· 261 261 dc->reset = aspeed_sdmc_reset; 262 262 dc->desc = "ASPEED SDRAM Memory Controller"; 263 263 dc->vmsd = &vmstate_aspeed_sdmc; 264 264 - dc->props = aspeed_sdmc_properties; 264 264 + device_class_set_props(dc, aspeed_sdmc_properties); 265 265 } 266 266 267 267 static const TypeInfo aspeed_sdmc_info = {

+1 -1

hw/misc/bcm2835_property.c

··· 426 426 { 427 427 DeviceClass *dc = DEVICE_CLASS(klass); 428 428 429 429 - dc->props = bcm2835_property_props; 429 429 + device_class_set_props(dc, bcm2835_property_props); 430 430 dc->realize = bcm2835_property_realize; 431 431 dc->vmsd = &vmstate_bcm2835_property; 432 432 }

+1 -1

hw/misc/debugexit.c

··· 65 65 DeviceClass *dc = DEVICE_CLASS(klass); 66 66 67 67 dc->realize = debug_exit_realizefn; 68 68 - dc->props = debug_exit_properties; 68 68 + device_class_set_props(dc, debug_exit_properties); 69 69 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 70 70 } 71 71

+1 -1

hw/misc/eccmemctl.c

··· 336 336 dc->realize = ecc_realize; 337 337 dc->reset = ecc_reset; 338 338 dc->vmsd = &vmstate_ecc; 339 339 - dc->props = ecc_properties; 339 339 + device_class_set_props(dc, ecc_properties); 340 340 } 341 341 342 342 static const TypeInfo ecc_info = {

+1 -1

hw/misc/iotkit-sysctl.c

··· 508 508 509 509 dc->vmsd = &iotkit_sysctl_vmstate; 510 510 dc->reset = iotkit_sysctl_reset; 511 511 - dc->props = iotkit_sysctl_props; 511 511 + device_class_set_props(dc, iotkit_sysctl_props); 512 512 dc->realize = iotkit_sysctl_realize; 513 513 } 514 514

+1 -1

hw/misc/iotkit-sysinfo.c

··· 121 121 * does not need a reset function or VMState. 122 122 */ 123 123 124 124 - dc->props = iotkit_sysinfo_props; 124 124 + device_class_set_props(dc, iotkit_sysinfo_props); 125 125 } 126 126 127 127 static const TypeInfo iotkit_sysinfo_info = {

+2 -2

hw/misc/ivshmem.c

··· 1055 1055 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1056 1056 1057 1057 k->realize = ivshmem_plain_realize; 1058 1058 - dc->props = ivshmem_plain_properties; 1058 1058 + device_class_set_props(dc, ivshmem_plain_properties); 1059 1059 dc->vmsd = &ivshmem_plain_vmsd; 1060 1060 } 1061 1061 ··· 1115 1115 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1116 1116 1117 1117 k->realize = ivshmem_doorbell_realize; 1118 1118 - dc->props = ivshmem_doorbell_properties; 1118 1118 + device_class_set_props(dc, ivshmem_doorbell_properties); 1119 1119 dc->vmsd = &ivshmem_doorbell_vmsd; 1120 1120 } 1121 1121

+1 -1

hw/misc/mac_via.c

··· 1021 1021 dc->realize = mac_via_realize; 1022 1022 dc->reset = mac_via_reset; 1023 1023 dc->vmsd = &vmstate_mac_via; 1024 1024 - dc->props = mac_via_properties; 1024 1024 + device_class_set_props(dc, mac_via_properties); 1025 1025 } 1026 1026 1027 1027 static TypeInfo mac_via_info = {

+1 -1

hw/misc/macio/cuda.c

··· 571 571 dc->realize = cuda_realize; 572 572 dc->reset = cuda_reset; 573 573 dc->vmsd = &vmstate_cuda; 574 574 - dc->props = cuda_properties; 574 574 + device_class_set_props(dc, cuda_properties); 575 575 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 576 576 } 577 577

+2 -2

hw/misc/macio/macio.c

··· 466 466 pdc->realize = macio_newworld_realize; 467 467 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL; 468 468 dc->vmsd = &vmstate_macio_newworld; 469 469 - dc->props = macio_newworld_properties; 469 469 + device_class_set_props(dc, macio_newworld_properties); 470 470 } 471 471 472 472 static Property macio_properties[] = { ··· 481 481 482 482 k->vendor_id = PCI_VENDOR_ID_APPLE; 483 483 k->class_id = PCI_CLASS_OTHERS << 8; 484 484 - dc->props = macio_properties; 484 484 + device_class_set_props(dc, macio_properties); 485 485 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 486 486 /* Reason: Uses serial_hds in macio_instance_init */ 487 487 dc->user_creatable = false;

+1 -1

hw/misc/macio/pmu.c

··· 795 795 dc->realize = pmu_realize; 796 796 dc->reset = pmu_reset; 797 797 dc->vmsd = &vmstate_pmu; 798 798 - dc->props = pmu_properties; 798 798 + device_class_set_props(dc, pmu_properties); 799 799 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 800 800 } 801 801

+1 -1

hw/misc/mips_cmgcr.c

··· 233 233 static void mips_gcr_class_init(ObjectClass *klass, void *data) 234 234 { 235 235 DeviceClass *dc = DEVICE_CLASS(klass); 236 236 - dc->props = mips_gcr_properties; 236 236 + device_class_set_props(dc, mips_gcr_properties); 237 237 dc->vmsd = &vmstate_mips_gcr; 238 238 dc->reset = mips_gcr_reset; 239 239 dc->realize = mips_gcr_realize;

+1 -1

hw/misc/mips_cpc.c

··· 175 175 dc->realize = mips_cpc_realize; 176 176 dc->reset = mips_cpc_reset; 177 177 dc->vmsd = &vmstate_mips_cpc; 178 178 - dc->props = mips_cpc_properties; 178 178 + device_class_set_props(dc, mips_cpc_properties); 179 179 } 180 180 181 181 static const TypeInfo mips_cpc_info = {

+1 -1

hw/misc/mips_itu.c

··· 561 561 { 562 562 DeviceClass *dc = DEVICE_CLASS(klass); 563 563 564 564 - dc->props = mips_itu_properties; 564 564 + device_class_set_props(dc, mips_itu_properties); 565 565 dc->realize = mips_itu_realize; 566 566 dc->reset = mips_itu_reset; 567 567 }

+1 -1

hw/misc/mos6522.c

··· 502 502 503 503 dc->reset = mos6522_reset; 504 504 dc->vmsd = &vmstate_mos6522; 505 505 - dc->props = mos6522_properties; 505 505 + device_class_set_props(dc, mos6522_properties); 506 506 mdc->parent_reset = dc->reset; 507 507 mdc->set_sr_int = mos6522_set_sr_int; 508 508 mdc->portB_write = mos6522_portB_write;

+1 -1

hw/misc/mps2-fpgaio.c

··· 300 300 301 301 dc->vmsd = &mps2_fpgaio_vmstate; 302 302 dc->reset = mps2_fpgaio_reset; 303 303 - dc->props = mps2_fpgaio_properties; 303 303 + device_class_set_props(dc, mps2_fpgaio_properties); 304 304 } 305 305 306 306 static const TypeInfo mps2_fpgaio_info = {

+1 -1

hw/misc/mps2-scc.c

··· 293 293 dc->realize = mps2_scc_realize; 294 294 dc->vmsd = &mps2_scc_vmstate; 295 295 dc->reset = mps2_scc_reset; 296 296 - dc->props = mps2_scc_properties; 296 296 + device_class_set_props(dc, mps2_scc_properties); 297 297 } 298 298 299 299 static const TypeInfo mps2_scc_info = {

+1 -1

hw/misc/msf2-sysreg.c

··· 143 143 144 144 dc->vmsd = &vmstate_msf2_sysreg; 145 145 dc->reset = msf2_sysreg_reset; 146 146 - dc->props = msf2_sysreg_properties; 146 146 + device_class_set_props(dc, msf2_sysreg_properties); 147 147 dc->realize = msf2_sysreg_realize; 148 148 } 149 149

+1 -1

hw/misc/nrf51_rng.c

··· 245 245 { 246 246 DeviceClass *dc = DEVICE_CLASS(klass); 247 247 248 248 - dc->props = nrf51_rng_properties; 248 248 + device_class_set_props(dc, nrf51_rng_properties); 249 249 dc->vmsd = &vmstate_rng; 250 250 dc->reset = nrf51_rng_reset; 251 251 }

+1 -1

hw/misc/pci-testdev.c

··· 339 339 dc->desc = "PCI Test Device"; 340 340 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 341 341 dc->reset = qdev_pci_testdev_reset; 342 342 - dc->props = pci_testdev_properties; 342 342 + device_class_set_props(dc, pci_testdev_properties); 343 343 } 344 344 345 345 static const TypeInfo pci_testdev_info = {

+10 -3

hw/misc/pvpanic.c

··· 21 21 #include "hw/qdev-properties.h" 22 22 #include "hw/misc/pvpanic.h" 23 23 24 24 - /* The bit of supported pv event */ 24 24 + /* The bit of supported pv event, TODO: include uapi header and remove this */ 25 25 #define PVPANIC_F_PANICKED 0 26 26 + #define PVPANIC_F_CRASHLOADED 1 26 27 27 28 /* The pv event value */ 28 29 #define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED) 30 30 + #define PVPANIC_CRASHLOADED (1 << PVPANIC_F_CRASHLOADED) 29 31 30 32 #define ISA_PVPANIC_DEVICE(obj) \ 31 33 OBJECT_CHECK(PVPanicState, (obj), TYPE_PVPANIC) ··· 34 36 { 35 37 static bool logged; 36 38 37 37 - if (event & ~PVPANIC_PANICKED && !logged) { 39 39 + if (event & ~(PVPANIC_PANICKED | PVPANIC_CRASHLOADED) && !logged) { 38 40 qemu_log_mask(LOG_GUEST_ERROR, "pvpanic: unknown event %#x.\n", event); 39 41 logged = true; 40 42 } 41 43 42 44 if (event & PVPANIC_PANICKED) { 43 45 qemu_system_guest_panicked(NULL); 46 46 + return; 47 47 + } 48 48 + 49 49 + if (event & PVPANIC_CRASHLOADED) { 50 50 + qemu_system_guest_crashloaded(NULL); 44 51 return; 45 52 } 46 53 } ··· 111 118 DeviceClass *dc = DEVICE_CLASS(klass); 112 119 113 120 dc->realize = pvpanic_isa_realizefn; 114 114 - dc->props = pvpanic_isa_properties; 121 121 + device_class_set_props(dc, pvpanic_isa_properties); 115 122 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 116 123 } 117 124

+1 -1

hw/misc/tz-mpc.c

··· 596 596 dc->realize = tz_mpc_realize; 597 597 dc->vmsd = &tz_mpc_vmstate; 598 598 dc->reset = tz_mpc_reset; 599 599 - dc->props = tz_mpc_properties; 599 599 + device_class_set_props(dc, tz_mpc_properties); 600 600 } 601 601 602 602 static const TypeInfo tz_mpc_info = {

+1 -1

hw/misc/tz-msc.c

··· 293 293 dc->realize = tz_msc_realize; 294 294 dc->vmsd = &tz_msc_vmstate; 295 295 dc->reset = tz_msc_reset; 296 296 - dc->props = tz_msc_properties; 296 296 + device_class_set_props(dc, tz_msc_properties); 297 297 } 298 298 299 299 static const TypeInfo tz_msc_info = {

+1 -1

hw/misc/tz-ppc.c

··· 319 319 dc->realize = tz_ppc_realize; 320 320 dc->vmsd = &tz_ppc_vmstate; 321 321 dc->reset = tz_ppc_reset; 322 322 - dc->props = tz_ppc_properties; 322 322 + device_class_set_props(dc, tz_ppc_properties); 323 323 } 324 324 325 325 static const TypeInfo tz_ppc_info = {

+1 -1

hw/misc/unimp.c

··· 79 79 DeviceClass *dc = DEVICE_CLASS(klass); 80 80 81 81 dc->realize = unimp_realize; 82 82 - dc->props = unimp_properties; 82 82 + device_class_set_props(dc, unimp_properties); 83 83 } 84 84 85 85 static const TypeInfo unimp_info = {

+1 -1

hw/net/allwinner_emac.c

··· 519 519 DeviceClass *dc = DEVICE_CLASS(klass); 520 520 521 521 dc->realize = aw_emac_realize; 522 522 - dc->props = aw_emac_properties; 522 522 + device_class_set_props(dc, aw_emac_properties); 523 523 dc->reset = aw_emac_reset; 524 524 dc->vmsd = &vmstate_aw_emac; 525 525 }

+1 -1

hw/net/cadence_gem.c

··· 1627 1627 DeviceClass *dc = DEVICE_CLASS(klass); 1628 1628 1629 1629 dc->realize = gem_realize; 1630 1630 - dc->props = gem_properties; 1630 1630 + device_class_set_props(dc, gem_properties); 1631 1631 dc->vmsd = &vmstate_cadence_gem; 1632 1632 dc->reset = gem_reset; 1633 1633 }

+1 -1

hw/net/dp8393x.c

··· 963 963 dc->realize = dp8393x_realize; 964 964 dc->reset = dp8393x_reset; 965 965 dc->vmsd = &vmstate_dp8393x; 966 966 - dc->props = dp8393x_properties; 966 966 + device_class_set_props(dc, dp8393x_properties); 967 967 } 968 968 969 969 static const TypeInfo dp8393x_info = {

+1 -1

hw/net/e1000.c

··· 1764 1764 dc->desc = "Intel Gigabit Ethernet"; 1765 1765 dc->reset = qdev_e1000_reset; 1766 1766 dc->vmsd = &vmstate_e1000; 1767 1767 - dc->props = e1000_properties; 1767 1767 + device_class_set_props(dc, e1000_properties); 1768 1768 } 1769 1769 1770 1770 static void e1000_instance_init(Object *obj)

+1 -1

hw/net/e1000e.c

··· 684 684 dc->desc = "Intel 82574L GbE Controller"; 685 685 dc->reset = e1000e_qdev_reset; 686 686 dc->vmsd = &e1000e_vmstate; 687 687 - dc->props = e1000e_properties; 688 687 689 688 e1000e_prop_disable_vnet = qdev_prop_uint8; 690 689 e1000e_prop_disable_vnet.description = "Do not use virtio headers, " ··· 697 696 e1000e_prop_subsys = qdev_prop_uint16; 698 697 e1000e_prop_subsys.description = "PCI device Subsystem ID"; 699 698 699 699 + device_class_set_props(dc, e1000e_properties); 700 700 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 701 701 } 702 702

+1 -1

hw/net/eepro100.c

··· 2060 2060 info = eepro100_get_class_by_name(object_class_get_name(klass)); 2061 2061 2062 2062 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2063 2063 - dc->props = e100_properties; 2063 2063 + device_class_set_props(dc, e100_properties); 2064 2064 dc->desc = info->desc; 2065 2065 k->vendor_id = PCI_VENDOR_ID_INTEL; 2066 2066 k->class_id = PCI_CLASS_NETWORK_ETHERNET;

+1 -1

hw/net/etraxfs_eth.c

··· 639 639 640 640 dc->realize = etraxfs_eth_realize; 641 641 dc->reset = etraxfs_eth_reset; 642 642 - dc->props = etraxfs_eth_properties; 642 642 + device_class_set_props(dc, etraxfs_eth_properties); 643 643 /* Reason: dma_out, dma_in are not user settable */ 644 644 dc->user_creatable = false; 645 645 }

+1 -1

hw/net/fsl_etsec/etsec.c

··· 423 423 424 424 dc->realize = etsec_realize; 425 425 dc->reset = etsec_reset; 426 426 - dc->props = etsec_properties; 426 426 + device_class_set_props(dc, etsec_properties); 427 427 /* Supported by ppce500 machine */ 428 428 dc->user_creatable = true; 429 429 }

+2 -2

hw/net/ftgmac100.c

··· 1075 1075 1076 1076 dc->vmsd = &vmstate_ftgmac100; 1077 1077 dc->reset = ftgmac100_reset; 1078 1078 - dc->props = ftgmac100_properties; 1078 1078 + device_class_set_props(dc, ftgmac100_properties); 1079 1079 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1080 1080 dc->realize = ftgmac100_realize; 1081 1081 dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation"; ··· 1237 1237 dc->reset = aspeed_mii_reset; 1238 1238 dc->realize = aspeed_mii_realize; 1239 1239 dc->desc = "Aspeed MII controller"; 1240 1240 - dc->props = aspeed_mii_properties; 1240 1240 + device_class_set_props(dc, aspeed_mii_properties); 1241 1241 } 1242 1242 1243 1243 static const TypeInfo aspeed_mii_info = {

+5 -4

hw/net/imx_fec.c

··· 901 901 s->regs[index] = 0; 902 902 } 903 903 break; 904 904 - case ENET_TDAR1: /* FALLTHROUGH */ 905 905 - case ENET_TDAR2: /* FALLTHROUGH */ 904 904 + case ENET_TDAR1: 905 905 + case ENET_TDAR2: 906 906 if (unlikely(single_tx_ring)) { 907 907 qemu_log_mask(LOG_GUEST_ERROR, 908 908 "[%s]%s: trying to access TDAR2 or TDAR1\n", 909 909 TYPE_IMX_FEC, __func__); 910 910 return; 911 911 } 912 912 - case ENET_TDAR: /* FALLTHROUGH */ 912 912 + /* fall through */ 913 913 + case ENET_TDAR: 913 914 if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { 914 915 s->regs[index] = ENET_TDAR_TDAR; 915 916 imx_eth_do_tx(s, index); ··· 1337 1338 1338 1339 dc->vmsd = &vmstate_imx_eth; 1339 1340 dc->reset = imx_eth_reset; 1340 1340 - dc->props = imx_eth_properties; 1341 1341 + device_class_set_props(dc, imx_eth_properties); 1341 1342 dc->realize = imx_eth_realize; 1342 1343 dc->desc = "i.MX FEC/ENET Ethernet Controller"; 1343 1344 }

+1 -1

hw/net/lan9118.c

··· 1369 1369 DeviceClass *dc = DEVICE_CLASS(klass); 1370 1370 1371 1371 dc->reset = lan9118_reset; 1372 1372 - dc->props = lan9118_properties; 1372 1372 + device_class_set_props(dc, lan9118_properties); 1373 1373 dc->vmsd = &vmstate_lan9118; 1374 1374 dc->realize = lan9118_realize; 1375 1375 }

+1 -1

hw/net/lance.c

··· 153 153 dc->fw_name = "ethernet"; 154 154 dc->reset = lance_reset; 155 155 dc->vmsd = &vmstate_lance; 156 156 - dc->props = lance_properties; 156 156 + device_class_set_props(dc, lance_properties); 157 157 } 158 158 159 159 static const TypeInfo lance_info = {

+1 -1

hw/net/mcf_fec.c

··· 670 670 dc->realize = mcf_fec_realize; 671 671 dc->desc = "MCF Fast Ethernet Controller network device"; 672 672 dc->reset = mcf_fec_reset; 673 673 - dc->props = mcf_fec_properties; 673 673 + device_class_set_props(dc, mcf_fec_properties); 674 674 } 675 675 676 676 static const TypeInfo mcf_fec_info = {

+1 -1

hw/net/milkymist-minimac2.c

··· 530 530 dc->realize = milkymist_minimac2_realize; 531 531 dc->reset = milkymist_minimac2_reset; 532 532 dc->vmsd = &vmstate_milkymist_minimac2; 533 533 - dc->props = milkymist_minimac2_properties; 533 533 + device_class_set_props(dc, milkymist_minimac2_properties); 534 534 } 535 535 536 536 static const TypeInfo milkymist_minimac2_info = {

+1 -1

hw/net/mipsnet.c

··· 278 278 dc->desc = "MIPS Simulator network device"; 279 279 dc->reset = mipsnet_sysbus_reset; 280 280 dc->vmsd = &vmstate_mipsnet; 281 281 - dc->props = mipsnet_properties; 281 281 + device_class_set_props(dc, mipsnet_properties); 282 282 } 283 283 284 284 static const TypeInfo mipsnet_info = {

+1 -1

hw/net/ne2000-isa.c

··· 89 89 DeviceClass *dc = DEVICE_CLASS(klass); 90 90 91 91 dc->realize = isa_ne2000_realizefn; 92 92 - dc->props = ne2000_isa_properties; 92 92 + device_class_set_props(dc, ne2000_isa_properties); 93 93 dc->vmsd = &vmstate_isa_ne2000; 94 94 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 95 95 }

+1 -1

hw/net/ne2000-pci.c

··· 112 112 k->device_id = PCI_DEVICE_ID_REALTEK_8029; 113 113 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 114 114 dc->vmsd = &vmstate_pci_ne2000; 115 115 - dc->props = ne2000_properties; 115 115 + device_class_set_props(dc, ne2000_properties); 116 116 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 117 117 } 118 118

+1 -1

hw/net/opencores_eth.c

··· 755 755 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 756 756 dc->desc = "Opencores 10/100 Mbit Ethernet"; 757 757 dc->reset = qdev_open_eth_reset; 758 758 - dc->props = open_eth_properties; 758 758 + device_class_set_props(dc, open_eth_properties); 759 759 } 760 760 761 761 static const TypeInfo open_eth_info = {

+1 -1

hw/net/pcnet-pci.c

··· 272 272 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 273 273 dc->reset = pci_reset; 274 274 dc->vmsd = &vmstate_pci_pcnet; 275 275 - dc->props = pcnet_properties; 275 275 + device_class_set_props(dc, pcnet_properties); 276 276 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 277 277 } 278 278

+1 -1

hw/net/rocker/rocker.c

··· 1519 1519 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1520 1520 dc->desc = "Rocker Switch"; 1521 1521 dc->reset = rocker_reset; 1522 1522 - dc->props = rocker_properties; 1522 1522 + device_class_set_props(dc, rocker_properties); 1523 1523 dc->vmsd = &rocker_vmsd; 1524 1524 } 1525 1525

+1 -1

hw/net/rtl8139.c

··· 3435 3435 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3436 3436 dc->reset = rtl8139_reset; 3437 3437 dc->vmsd = &vmstate_rtl8139; 3438 3438 - dc->props = rtl8139_properties; 3438 3438 + device_class_set_props(dc, rtl8139_properties); 3439 3439 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3440 3440 } 3441 3441

+1 -1

hw/net/smc91c111.c

··· 798 798 dc->realize = smc91c111_realize; 799 799 dc->reset = smc91c111_reset; 800 800 dc->vmsd = &vmstate_smc91c111; 801 801 - dc->props = smc91c111_properties; 801 801 + device_class_set_props(dc, smc91c111_properties); 802 802 } 803 803 804 804 static const TypeInfo smc91c111_info = {

+1 -1

hw/net/spapr_llan.c

··· 856 856 k->dt_compatible = "IBM,l-lan"; 857 857 k->signal_mask = 0x1; 858 858 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 859 859 - dc->props = spapr_vlan_properties; 859 859 + device_class_set_props(dc, spapr_vlan_properties); 860 860 k->rtce_window_size = 0x10000000; 861 861 dc->vmsd = &vmstate_spapr_llan; 862 862 }

+1 -1

hw/net/stellaris_enet.c

··· 507 507 508 508 dc->realize = stellaris_enet_realize; 509 509 dc->reset = stellaris_enet_reset; 510 510 - dc->props = stellaris_enet_properties; 510 510 + device_class_set_props(dc, stellaris_enet_properties); 511 511 dc->vmsd = &vmstate_stellaris_enet; 512 512 } 513 513

+1 -1

hw/net/sungem.c

··· 1429 1429 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 1430 1430 dc->vmsd = &vmstate_sungem; 1431 1431 dc->reset = sungem_reset; 1432 1432 - dc->props = sungem_properties; 1432 1432 + device_class_set_props(dc, sungem_properties); 1433 1433 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1434 1434 } 1435 1435

+1 -1

hw/net/sunhme.c

··· 958 958 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 959 959 dc->vmsd = &vmstate_hme; 960 960 dc->reset = sunhme_reset; 961 961 - dc->props = sunhme_properties; 961 961 + device_class_set_props(dc, sunhme_properties); 962 962 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 963 963 } 964 964

+1 -1

hw/net/tulip.c

··· 1004 1004 k->subsystem_id = 0x104f; 1005 1005 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 1006 1006 dc->vmsd = &vmstate_pci_tulip; 1007 1007 - dc->props = tulip_properties; 1007 1007 + device_class_set_props(dc, tulip_properties); 1008 1008 dc->reset = tulip_qdev_reset; 1009 1009 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1010 1010 }

+1 -1

hw/net/virtio-net.c

··· 3236 3236 DeviceClass *dc = DEVICE_CLASS(klass); 3237 3237 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 3238 3238 3239 3239 - dc->props = virtio_net_properties; 3239 3239 + device_class_set_props(dc, virtio_net_properties); 3240 3240 dc->vmsd = &vmstate_virtio_net; 3241 3241 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3242 3242 vdc->realize = virtio_net_device_realize;

+1 -1

hw/net/vmxnet3.c

··· 2506 2506 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2507 2507 dc->reset = vmxnet3_qdev_reset; 2508 2508 dc->vmsd = &vmstate_vmxnet3; 2509 2509 - dc->props = vmxnet3_properties; 2509 2509 + device_class_set_props(dc, vmxnet3_properties); 2510 2510 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2511 2511 } 2512 2512

+1 -1

hw/net/xgmac.c

··· 414 414 415 415 dc->realize = xgmac_enet_realize; 416 416 dc->vmsd = &vmstate_xgmac; 417 417 - dc->props = xgmac_properties; 417 417 + device_class_set_props(dc, xgmac_properties); 418 418 } 419 419 420 420 static const TypeInfo xgmac_enet_info = {

+1 -1

hw/net/xilinx_axienet.c

··· 1025 1025 DeviceClass *dc = DEVICE_CLASS(klass); 1026 1026 1027 1027 dc->realize = xilinx_enet_realize; 1028 1028 - dc->props = xilinx_enet_properties; 1028 1028 + device_class_set_props(dc, xilinx_enet_properties); 1029 1029 dc->reset = xilinx_axienet_reset; 1030 1030 } 1031 1031

+1 -1

hw/net/xilinx_ethlite.c

··· 262 262 263 263 dc->realize = xilinx_ethlite_realize; 264 264 dc->reset = xilinx_ethlite_reset; 265 265 - dc->props = xilinx_ethlite_properties; 265 265 + device_class_set_props(dc, xilinx_ethlite_properties); 266 266 } 267 267 268 268 static const TypeInfo xilinx_ethlite_info = {

+1 -1

hw/nvram/ds1225y.c

··· 153 153 154 154 dc->realize = nvram_sysbus_realize; 155 155 dc->vmsd = &vmstate_nvram; 156 156 - dc->props = nvram_sysbus_properties; 156 156 + device_class_set_props(dc, nvram_sysbus_properties); 157 157 } 158 158 159 159 static const TypeInfo nvram_sysbus_info = {

+1 -1

hw/nvram/eeprom_at24c.c

··· 182 182 k->recv = &at24c_eeprom_recv; 183 183 k->send = &at24c_eeprom_send; 184 184 185 185 - dc->props = at24c_eeprom_props; 185 185 + device_class_set_props(dc, at24c_eeprom_props); 186 186 dc->reset = at24c_eeprom_reset; 187 187 } 188 188

+2 -2

hw/nvram/fw_cfg.c

··· 1171 1171 DeviceClass *dc = DEVICE_CLASS(klass); 1172 1172 1173 1173 dc->realize = fw_cfg_io_realize; 1174 1174 - dc->props = fw_cfg_io_properties; 1174 1174 + device_class_set_props(dc, fw_cfg_io_properties); 1175 1175 } 1176 1176 1177 1177 static const TypeInfo fw_cfg_io_info = { ··· 1234 1234 DeviceClass *dc = DEVICE_CLASS(klass); 1235 1235 1236 1236 dc->realize = fw_cfg_mem_realize; 1237 1237 - dc->props = fw_cfg_mem_properties; 1237 1237 + device_class_set_props(dc, fw_cfg_mem_properties); 1238 1238 } 1239 1239 1240 1240 static const TypeInfo fw_cfg_mem_info = {

+1 -1

hw/nvram/mac_nvram.c

··· 128 128 dc->unrealize = macio_nvram_unrealizefn; 129 129 dc->reset = macio_nvram_reset; 130 130 dc->vmsd = &vmstate_macio_nvram; 131 131 - dc->props = macio_nvram_properties; 131 131 + device_class_set_props(dc, macio_nvram_properties); 132 132 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 133 133 } 134 134

+1 -1

hw/nvram/nrf51_nvm.c

··· 369 369 { 370 370 DeviceClass *dc = DEVICE_CLASS(klass); 371 371 372 372 - dc->props = nrf51_nvm_properties; 372 372 + device_class_set_props(dc, nrf51_nvm_properties); 373 373 dc->vmsd = &vmstate_nvm; 374 374 dc->realize = nrf51_nvm_realize; 375 375 dc->reset = nrf51_nvm_reset;

+1 -1

hw/nvram/spapr_nvram.c

··· 269 269 k->dt_type = "nvram"; 270 270 k->dt_compatible = "qemu,spapr-nvram"; 271 271 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 272 272 - dc->props = spapr_nvram_properties; 272 272 + device_class_set_props(dc, spapr_nvram_properties); 273 273 dc->vmsd = &vmstate_spapr_nvram; 274 274 /* Reason: Internal device only, uses spapr_rtas_register() in realize() */ 275 275 dc->user_creatable = false;

+1 -1

hw/pci-bridge/gen_pcie_root_port.c

··· 147 147 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP; 148 148 dc->desc = "PCI Express Root Port"; 149 149 dc->vmsd = &vmstate_rp_dev; 150 150 - dc->props = gen_rp_props; 150 150 + device_class_set_props(dc, gen_rp_props); 151 151 152 152 device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize); 153 153

+1 -1

hw/pci-bridge/pci_bridge_dev.c

··· 258 258 k->is_bridge = true; 259 259 dc->desc = "Standard PCI Bridge"; 260 260 dc->reset = qdev_pci_bridge_dev_reset; 261 261 - dc->props = pci_bridge_dev_properties; 261 261 + device_class_set_props(dc, pci_bridge_dev_properties); 262 262 dc->vmsd = &pci_bridge_dev_vmstate; 263 263 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 264 264 hc->plug = pci_bridge_dev_plug_cb;

+2 -2

hw/pci-bridge/pci_expander_bridge.c

··· 309 309 k->class_id = PCI_CLASS_BRIDGE_HOST; 310 310 311 311 dc->desc = "PCI Expander Bridge"; 312 312 - dc->props = pxb_dev_properties; 312 312 + device_class_set_props(dc, pxb_dev_properties); 313 313 dc->hotpluggable = false; 314 314 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 315 315 } ··· 347 347 k->class_id = PCI_CLASS_BRIDGE_HOST; 348 348 349 349 dc->desc = "PCI Express Expander Bridge"; 350 350 - dc->props = pxb_dev_properties; 350 350 + device_class_set_props(dc, pxb_dev_properties); 351 351 dc->hotpluggable = false; 352 352 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 353 353 }

+1 -1

hw/pci-bridge/pcie_pci_bridge.c

··· 152 152 k->exit = pcie_pci_bridge_exit; 153 153 k->config_write = pcie_pci_bridge_write_config; 154 154 dc->vmsd = &pcie_pci_bridge_dev_vmstate; 155 155 - dc->props = pcie_pci_bridge_dev_properties; 155 155 + device_class_set_props(dc, pcie_pci_bridge_dev_properties); 156 156 dc->reset = &pcie_pci_bridge_reset; 157 157 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 158 158 hc->plug = pci_bridge_dev_plug_cb;

+1 -1

hw/pci-bridge/pcie_root_port.c

··· 174 174 k->exit = rp_exit; 175 175 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 176 176 dc->reset = rp_reset; 177 177 - dc->props = rp_props; 177 177 + device_class_set_props(dc, rp_props); 178 178 } 179 179 180 180 static const TypeInfo rp_info = {

+1 -1

hw/pci-bridge/xio3130_downstream.c

··· 169 169 dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; 170 170 dc->reset = xio3130_downstream_reset; 171 171 dc->vmsd = &vmstate_xio3130_downstream; 172 172 - dc->props = xio3130_downstream_props; 172 172 + device_class_set_props(dc, xio3130_downstream_props); 173 173 } 174 174 175 175 static const TypeInfo xio3130_downstream_info = {

+1 -1

hw/pci-host/designware.c

··· 182 182 break; 183 183 184 184 case DESIGNWARE_PCIE_ATU_CR1: 185 185 - case DESIGNWARE_PCIE_ATU_CR2: /* FALLTHROUGH */ 185 185 + case DESIGNWARE_PCIE_ATU_CR2: 186 186 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / 187 187 sizeof(uint32_t)]; 188 188 break;

+1 -1

hw/pci-host/grackle.c

··· 168 168 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 169 169 170 170 dc->realize = grackle_realize; 171 171 - dc->props = grackle_properties; 171 171 + device_class_set_props(dc, grackle_properties); 172 172 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 173 173 dc->fw_name = "pci"; 174 174 sbc->explicit_ofw_unit_address = grackle_ofw_unit_address;

+1 -1

hw/pci-host/i440fx.c

··· 396 396 hc->root_bus_path = i440fx_pcihost_root_bus_path; 397 397 dc->realize = i440fx_pcihost_realize; 398 398 dc->fw_name = "pci"; 399 399 - dc->props = i440fx_props; 399 399 + device_class_set_props(dc, i440fx_props); 400 400 /* Reason: needs to be wired up by pc_init1 */ 401 401 dc->user_creatable = false; 402 402 }

+1 -1

hw/pci-host/ppce500.c

··· 531 531 532 532 dc->realize = e500_pcihost_realize; 533 533 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 534 534 - dc->props = pcihost_properties; 534 534 + device_class_set_props(dc, pcihost_properties); 535 535 dc->vmsd = &vmstate_ppce500_pci; 536 536 } 537 537

+1 -1

hw/pci-host/prep.c

··· 415 415 416 416 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 417 417 dc->realize = raven_pcihost_realizefn; 418 418 - dc->props = raven_pcihost_properties; 418 418 + device_class_set_props(dc, raven_pcihost_properties); 419 419 dc->fw_name = "pci"; 420 420 } 421 421

+2 -2

hw/pci-host/q35.c

··· 202 202 203 203 hc->root_bus_path = q35_host_root_bus_path; 204 204 dc->realize = q35_host_realize; 205 205 - dc->props = q35_host_props; 205 205 + device_class_set_props(dc, q35_host_props); 206 206 /* Reason: needs to be wired up by pc_q35_init */ 207 207 dc->user_creatable = false; 208 208 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); ··· 682 682 k->realize = mch_realize; 683 683 k->config_write = mch_write_config; 684 684 dc->reset = mch_reset; 685 685 - dc->props = mch_props; 685 685 + device_class_set_props(dc, mch_props); 686 686 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 687 687 dc->desc = "Host bridge"; 688 688 dc->vmsd = &vmstate_mch;

+1 -1

hw/pci-host/sabre.c

··· 521 521 522 522 dc->realize = sabre_realize; 523 523 dc->reset = sabre_reset; 524 524 - dc->props = sabre_properties; 524 524 + device_class_set_props(dc, sabre_properties); 525 525 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 526 526 dc->fw_name = "pci"; 527 527 sbc->explicit_ofw_unit_address = sabre_ofw_unit_address;

+1 -1

hw/pci-host/uninorth.c

··· 476 476 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 477 477 478 478 dc->realize = pci_unin_main_realize; 479 479 - dc->props = pci_unin_main_pci_host_props; 479 479 + device_class_set_props(dc, pci_unin_main_pci_host_props); 480 480 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 481 481 dc->fw_name = "pci"; 482 482 sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address;

+1 -1

hw/pci-host/versatile.c

··· 509 509 dc->realize = pci_vpb_realize; 510 510 dc->reset = pci_vpb_reset; 511 511 dc->vmsd = &pci_vpb_vmstate; 512 512 - dc->props = pci_vpb_properties; 512 512 + device_class_set_props(dc, pci_vpb_properties); 513 513 } 514 514 515 515 static const TypeInfo pci_vpb_info = {

+1 -1

hw/pci-host/xilinx-pcie.c

··· 177 177 dc->realize = xilinx_pcie_host_realize; 178 178 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 179 179 dc->fw_name = "pci"; 180 180 - dc->props = xilinx_pcie_host_props; 180 180 + device_class_set_props(dc, xilinx_pcie_host_props); 181 181 } 182 182 183 183 static const TypeInfo xilinx_pcie_host_info = {

+1 -1

hw/pci/pci.c

··· 2624 2624 k->realize = pci_qdev_realize; 2625 2625 k->unrealize = pci_qdev_unrealize; 2626 2626 k->bus_type = TYPE_PCI_BUS; 2627 2627 - k->props = pci_props; 2627 2627 + device_class_set_props(k, pci_props); 2628 2628 } 2629 2629 2630 2630 static void pci_device_class_base_init(ObjectClass *klass, void *data)

+2 -2

hw/pci/pcie_port.c

··· 133 133 { 134 134 DeviceClass *dc = DEVICE_CLASS(oc); 135 135 136 136 - dc->props = pcie_port_props; 136 136 + device_class_set_props(dc, pcie_port_props); 137 137 } 138 138 139 139 static const TypeInfo pcie_port_type_info = { ··· 155 155 DeviceClass *dc = DEVICE_CLASS(oc); 156 156 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 157 157 158 158 - dc->props = pcie_slot_props; 158 158 + device_class_set_props(dc, pcie_slot_props); 159 159 hc->pre_plug = pcie_cap_slot_pre_plug_cb; 160 160 hc->plug = pcie_cap_slot_plug_cb; 161 161 hc->unplug = pcie_cap_slot_unplug_cb;

+1 -1

hw/ppc/pnv.c

··· 1614 1614 1615 1615 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1616 1616 dc->realize = pnv_chip_realize; 1617 1617 - dc->props = pnv_chip_properties; 1617 1617 + device_class_set_props(dc, pnv_chip_properties); 1618 1618 dc->desc = "PowerNV Chip"; 1619 1619 } 1620 1620

+2 -2

hw/ppc/pnv_core.c

··· 323 323 324 324 dc->realize = pnv_core_realize; 325 325 dc->unrealize = pnv_core_unrealize; 326 326 - dc->props = pnv_core_properties; 326 326 + device_class_set_props(dc, pnv_core_properties); 327 327 } 328 328 329 329 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ ··· 421 421 DeviceClass *dc = DEVICE_CLASS(oc); 422 422 423 423 dc->realize = pnv_quad_realize; 424 424 - dc->props = pnv_quad_properties; 424 424 + device_class_set_props(dc, pnv_quad_properties); 425 425 } 426 426 427 427 static const TypeInfo pnv_quad_info = {

+1 -1

hw/ppc/pnv_homer.c

··· 359 359 360 360 dc->realize = pnv_homer_realize; 361 361 dc->desc = "PowerNV HOMER Memory"; 362 362 - dc->props = pnv_homer_properties; 362 362 + device_class_set_props(dc, pnv_homer_properties); 363 363 } 364 364 365 365 static const TypeInfo pnv_homer_type_info = {

+1 -1

hw/ppc/pnv_lpc.c

··· 761 761 762 762 dc->realize = pnv_lpc_realize; 763 763 dc->desc = "PowerNV LPC Controller"; 764 764 - dc->props = pnv_lpc_properties; 764 764 + device_class_set_props(dc, pnv_lpc_properties); 765 765 } 766 766 767 767 static const TypeInfo pnv_lpc_info = {

+1 -1

hw/ppc/pnv_occ.c

··· 279 279 280 280 dc->realize = pnv_occ_realize; 281 281 dc->desc = "PowerNV OCC Controller"; 282 282 - dc->props = pnv_occ_properties; 282 282 + device_class_set_props(dc, pnv_occ_properties); 283 283 } 284 284 285 285 static const TypeInfo pnv_occ_type_info = {

+1 -1

hw/ppc/pnv_pnor.c

··· 121 121 DeviceClass *dc = DEVICE_CLASS(klass); 122 122 123 123 dc->realize = pnv_pnor_realize; 124 124 - dc->props = pnv_pnor_properties; 124 124 + device_class_set_props(dc, pnv_pnor_properties); 125 125 } 126 126 127 127 static const TypeInfo pnv_pnor_info = {

+1 -1

hw/ppc/pnv_psi.c

··· 937 937 xdc->dt_xscom = pnv_psi_dt_xscom; 938 938 939 939 dc->desc = "PowerNV PSI Controller"; 940 940 - dc->props = pnv_psi_properties; 940 940 + device_class_set_props(dc, pnv_psi_properties); 941 941 dc->reset = pnv_psi_reset; 942 942 } 943 943

+1 -1

hw/ppc/ppc440_uc.c

··· 1296 1296 1297 1297 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1298 1298 dc->realize = ppc460ex_pcie_realize; 1299 1299 - dc->props = ppc460ex_pcie_props; 1299 1299 + device_class_set_props(dc, ppc460ex_pcie_props); 1300 1300 dc->hotpluggable = false; 1301 1301 } 1302 1302

+1 -1

hw/ppc/prep_systemio.c

··· 289 289 290 290 dc->realize = prep_systemio_realize; 291 291 dc->vmsd = &vmstate_prep_systemio; 292 292 - dc->props = prep_systemio_properties; 292 292 + device_class_set_props(dc, prep_systemio_properties); 293 293 } 294 294 295 295 static TypeInfo prep_systemio800_info = {

+1 -1

hw/ppc/rs6000_mc.c

··· 222 222 223 223 dc->realize = rs6000mc_realize; 224 224 dc->vmsd = &vmstate_rs6000mc; 225 225 - dc->props = rs6000mc_properties; 225 225 + device_class_set_props(dc, rs6000mc_properties); 226 226 } 227 227 228 228 static const TypeInfo rs6000mc_info = {

+1 -1

hw/ppc/spapr_cpu_core.c

··· 383 383 dc->realize = spapr_cpu_core_realize; 384 384 dc->unrealize = spapr_cpu_core_unrealize; 385 385 dc->reset = spapr_cpu_core_reset; 386 386 - dc->props = spapr_cpu_core_properties; 386 386 + device_class_set_props(dc, spapr_cpu_core_properties); 387 387 scc->cpu_type = data; 388 388 } 389 389

+1 -1

hw/ppc/spapr_pci.c

··· 2217 2217 hc->root_bus_path = spapr_phb_root_bus_path; 2218 2218 dc->realize = spapr_phb_realize; 2219 2219 dc->unrealize = spapr_phb_unrealize; 2220 2220 - dc->props = spapr_phb_properties; 2220 2220 + device_class_set_props(dc, spapr_phb_properties); 2221 2221 dc->reset = spapr_phb_reset; 2222 2222 dc->vmsd = &vmstate_spapr_pci; 2223 2223 /* Supported by TYPE_SPAPR_MACHINE */

+1 -1

hw/ppc/spapr_rng.c

··· 146 146 147 147 dc->realize = spapr_rng_realize; 148 148 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 149 149 - dc->props = spapr_rng_properties; 149 149 + device_class_set_props(dc, spapr_rng_properties); 150 150 dc->hotpluggable = false; 151 151 } 152 152

+4 -5

hw/ppc/spapr_rtas.c

··· 267 267 uint32_t nret, target_ulong rets) 268 268 { 269 269 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 270 270 - MachineState *ms = MACHINE(qdev_get_machine()); 271 271 - unsigned int max_cpus = ms->smp.max_cpus; 270 270 + MachineState *ms = MACHINE(spapr); 272 271 target_ulong parameter = rtas_ld(args, 0); 273 272 target_ulong buffer = rtas_ld(args, 1); 274 273 target_ulong length = rtas_ld(args, 2); ··· 280 279 "DesMem=%" PRIu64 "," 281 280 "DesProcs=%d," 282 281 "MaxPlatProcs=%d", 283 283 - max_cpus, 284 284 - current_machine->ram_size / MiB, 282 282 + ms->smp.max_cpus, 283 283 + ms->ram_size / MiB, 285 284 ms->smp.cpus, 286 286 - max_cpus); 285 285 + ms->smp.max_cpus); 287 286 if (pcc->n_host_threads > 0) { 288 287 char *hostthr_val, *old = param_val; 289 288

+1 -1

hw/ppc/spapr_tpm_proxy.c

··· 159 159 dk->realize = spapr_tpm_proxy_realize; 160 160 dk->unrealize = spapr_tpm_proxy_unrealize; 161 161 dk->user_creatable = true; 162 162 - dk->props = spapr_tpm_proxy_properties; 162 162 + device_class_set_props(dk, spapr_tpm_proxy_properties); 163 163 } 164 164 165 165 static const TypeInfo spapr_tpm_proxy_info = {

+1 -1

hw/rdma/vmw/pvrdma_main.c

··· 690 690 k->class_id = PCI_CLASS_NETWORK_OTHER; 691 691 692 692 dc->desc = "RDMA Device"; 693 693 - dc->props = pvrdma_dev_properties; 693 693 + device_class_set_props(dc, pvrdma_dev_properties); 694 694 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 695 695 696 696 ir->print_statistics = pvrdma_print_statistics;

+1 -1

hw/riscv/riscv_hart.c

··· 74 74 { 75 75 DeviceClass *dc = DEVICE_CLASS(klass); 76 76 77 77 - dc->props = riscv_harts_props; 77 77 + device_class_set_props(dc, riscv_harts_props); 78 78 dc->realize = riscv_harts_realize; 79 79 } 80 80

+1 -1

hw/riscv/sifive_clint.c

··· 205 205 { 206 206 DeviceClass *dc = DEVICE_CLASS(klass); 207 207 dc->realize = sifive_clint_realize; 208 208 - dc->props = sifive_clint_properties; 208 208 + device_class_set_props(dc, sifive_clint_properties); 209 209 } 210 210 211 211 static const TypeInfo sifive_clint_info = {

+1 -1

hw/riscv/sifive_plic.c

··· 466 466 { 467 467 DeviceClass *dc = DEVICE_CLASS(klass); 468 468 469 469 - dc->props = sifive_plic_properties; 469 469 + device_class_set_props(dc, sifive_plic_properties); 470 470 dc->realize = sifive_plic_realize; 471 471 } 472 472

+1 -1

hw/riscv/sifive_u_otp.c

··· 171 171 { 172 172 DeviceClass *dc = DEVICE_CLASS(klass); 173 173 174 174 - dc->props = sifive_u_otp_properties; 174 174 + device_class_set_props(dc, sifive_u_otp_properties); 175 175 dc->realize = sifive_u_otp_realize; 176 176 dc->reset = sifive_u_otp_reset; 177 177 }

+1 -1

hw/rtc/m48t59-isa.c

··· 137 137 138 138 dc->realize = m48t59_isa_realize; 139 139 dc->reset = m48t59_reset_isa; 140 140 - dc->props = m48t59_isa_properties; 140 140 + device_class_set_props(dc, m48t59_isa_properties); 141 141 nc->read = m48txx_isa_read; 142 142 nc->write = m48txx_isa_write; 143 143 nc->toggle_lock = m48txx_isa_toggle_lock;

+1 -1

hw/rtc/m48t59.c

··· 667 667 668 668 dc->realize = m48t59_realize; 669 669 dc->reset = m48t59_reset_sysbus; 670 670 - dc->props = m48t59_sysbus_properties; 670 670 + device_class_set_props(dc, m48t59_sysbus_properties); 671 671 dc->vmsd = &vmstate_m48t59; 672 672 nc->read = m48txx_sysbus_read; 673 673 nc->write = m48txx_sysbus_write;

+1 -1

hw/rtc/mc146818rtc.c

··· 1015 1015 dc->realize = rtc_realizefn; 1016 1016 dc->reset = rtc_resetdev; 1017 1017 dc->vmsd = &vmstate_rtc; 1018 1018 - dc->props = mc146818rtc_properties; 1018 1018 + device_class_set_props(dc, mc146818rtc_properties); 1019 1019 } 1020 1020 1021 1021 static const TypeInfo mc146818rtc_info = {

+1 -1

hw/rtc/pl031.c

··· 321 321 DeviceClass *dc = DEVICE_CLASS(klass); 322 322 323 323 dc->vmsd = &vmstate_pl031; 324 324 - dc->props = pl031_properties; 324 324 + device_class_set_props(dc, pl031_properties); 325 325 } 326 326 327 327 static const TypeInfo pl031_info = {

+1 -1

hw/s390x/3270-ccw.c

··· 155 155 { 156 156 DeviceClass *dc = DEVICE_CLASS(klass); 157 157 158 158 - dc->props = emulated_ccw_3270_properties; 158 158 + device_class_set_props(dc, emulated_ccw_3270_properties); 159 159 dc->bus_type = TYPE_VIRTUAL_CSS_BUS; 160 160 dc->realize = emulated_ccw_3270_realize; 161 161 dc->hotpluggable = false;

+1 -1

hw/s390x/ccw-device.c

··· 57 57 58 58 k->realize = ccw_device_realize; 59 59 k->refill_ids = ccw_device_refill_ids; 60 60 - dc->props = ccw_device_properties; 60 60 + device_class_set_props(dc, ccw_device_properties); 61 61 dc->reset = ccw_device_reset; 62 62 } 63 63

+1 -1

hw/s390x/css-bridge.c

··· 139 139 140 140 hc->unplug = ccw_device_unplug; 141 141 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 142 142 - dc->props = virtual_css_bridge_properties; 142 142 + device_class_set_props(dc, virtual_css_bridge_properties); 143 143 object_class_property_add_bool(klass, "cssid-unrestricted", 144 144 prop_get_true, NULL, NULL); 145 145 object_class_property_set_description(klass, "cssid-unrestricted",

+1 -1

hw/s390x/ipl.c

··· 666 666 DeviceClass *dc = DEVICE_CLASS(klass); 667 667 668 668 dc->realize = s390_ipl_realize; 669 669 - dc->props = s390_ipl_properties; 669 669 + device_class_set_props(dc, s390_ipl_properties); 670 670 dc->reset = s390_ipl_reset; 671 671 dc->vmsd = &vmstate_ipl; 672 672 set_bit(DEVICE_CATEGORY_MISC, dc->categories);

+1 -1

hw/s390x/s390-pci-bus.c

··· 1314 1314 dc->reset = s390_pci_device_reset; 1315 1315 dc->bus_type = TYPE_S390_PCI_BUS; 1316 1316 dc->realize = s390_pci_device_realize; 1317 1317 - dc->props = s390_pci_device_properties; 1317 1317 + device_class_set_props(dc, s390_pci_device_properties); 1318 1318 dc->vmsd = &s390_pci_device_vmstate; 1319 1319 } 1320 1320

+1 -1

hw/s390x/vhost-vsock-ccw.c

··· 35 35 36 36 k->realize = vhost_vsock_ccw_realize; 37 37 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 38 38 - dc->props = vhost_vsock_ccw_properties; 38 38 + device_class_set_props(dc, vhost_vsock_ccw_properties); 39 39 } 40 40 41 41 static void vhost_vsock_ccw_instance_init(Object *obj)

+1 -1

hw/s390x/virtio-ccw-9p.c

··· 47 47 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 48 48 49 49 k->realize = virtio_ccw_9p_realize; 50 50 - dc->props = virtio_ccw_9p_properties; 50 50 + device_class_set_props(dc, virtio_ccw_9p_properties); 51 51 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 52 52 } 53 53

+1 -1

hw/s390x/virtio-ccw-balloon.c

··· 52 52 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 53 53 54 54 k->realize = virtio_ccw_balloon_realize; 55 55 - dc->props = virtio_ccw_balloon_properties; 55 55 + device_class_set_props(dc, virtio_ccw_balloon_properties); 56 56 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 57 57 } 58 58

+1 -1

hw/s390x/virtio-ccw-blk.c

··· 49 49 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 50 50 51 51 k->realize = virtio_ccw_blk_realize; 52 52 - dc->props = virtio_ccw_blk_properties; 52 52 + device_class_set_props(dc, virtio_ccw_blk_properties); 53 53 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 54 54 } 55 55

+1 -1

hw/s390x/virtio-ccw-crypto.c

··· 57 57 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 58 58 59 59 k->realize = virtio_ccw_crypto_realize; 60 60 - dc->props = virtio_ccw_crypto_properties; 60 60 + device_class_set_props(dc, virtio_ccw_crypto_properties); 61 61 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 62 62 } 63 63

+1 -1

hw/s390x/virtio-ccw-gpu.c

··· 48 48 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 49 49 50 50 k->realize = virtio_ccw_gpu_realize; 51 51 - dc->props = virtio_ccw_gpu_properties; 51 51 + device_class_set_props(dc, virtio_ccw_gpu_properties); 52 52 dc->hotpluggable = false; 53 53 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 54 54 }

+1 -1

hw/s390x/virtio-ccw-input.c

··· 38 38 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 39 39 40 40 k->realize = virtio_ccw_input_realize; 41 41 - dc->props = virtio_ccw_input_properties; 41 41 + device_class_set_props(dc, virtio_ccw_input_properties); 42 42 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 43 43 } 44 44

+1 -1

hw/s390x/virtio-ccw-net.c

··· 52 52 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 53 53 54 54 k->realize = virtio_ccw_net_realize; 55 55 - dc->props = virtio_ccw_net_properties; 55 55 + device_class_set_props(dc, virtio_ccw_net_properties); 56 56 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 57 57 } 58 58

+1 -1

hw/s390x/virtio-ccw-rng.c

··· 56 56 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 57 57 58 58 k->realize = virtio_ccw_rng_realize; 59 59 - dc->props = virtio_ccw_rng_properties; 59 59 + device_class_set_props(dc, virtio_ccw_rng_properties); 60 60 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 61 61 } 62 62

+2 -2

hw/s390x/virtio-ccw-scsi.c

··· 59 59 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 60 60 61 61 k->realize = virtio_ccw_scsi_realize; 62 62 - dc->props = virtio_ccw_scsi_properties; 62 62 + device_class_set_props(dc, virtio_ccw_scsi_properties); 63 63 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 64 64 } 65 65 ··· 102 102 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 103 103 104 104 k->realize = vhost_ccw_scsi_realize; 105 105 - dc->props = vhost_ccw_scsi_properties; 105 105 + device_class_set_props(dc, vhost_ccw_scsi_properties); 106 106 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 107 107 } 108 108

+1 -1

hw/s390x/virtio-ccw-serial.c

··· 60 60 VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass); 61 61 62 62 k->realize = virtio_ccw_serial_realize; 63 63 - dc->props = virtio_ccw_serial_properties; 63 63 + device_class_set_props(dc, virtio_ccw_serial_properties); 64 64 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 65 65 } 66 66

+1 -1

hw/scsi/megasas.c

··· 2511 2511 e->osts = info->osts; 2512 2512 e->product_name = info->product_name; 2513 2513 e->product_version = info->product_version; 2514 2514 - dc->props = info->props; 2514 2514 + device_class_set_props(dc, info->props); 2515 2515 dc->reset = megasas_scsi_reset; 2516 2516 dc->vmsd = info->vmsd; 2517 2517 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);

+1 -1

hw/scsi/mptsas.c

··· 1431 1431 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 1432 1432 pc->subsystem_id = 0x8000; 1433 1433 pc->class_id = PCI_CLASS_STORAGE_SCSI; 1434 1434 - dc->props = mptsas_properties; 1434 1434 + device_class_set_props(dc, mptsas_properties); 1435 1435 dc->reset = mptsas_reset; 1436 1436 dc->vmsd = &vmstate_mptsas; 1437 1437 dc->desc = "LSI SAS 1068";

+1 -1

hw/scsi/scsi-bus.c

··· 1728 1728 k->bus_type = TYPE_SCSI_BUS; 1729 1729 k->realize = scsi_qdev_realize; 1730 1730 k->unrealize = scsi_qdev_unrealize; 1731 1731 - k->props = scsi_props; 1731 1731 + device_class_set_props(k, scsi_props); 1732 1732 } 1733 1733 1734 1734 static void scsi_dev_instance_init(Object *obj)

+4 -4

hw/scsi/scsi-disk.c

··· 3036 3036 sc->alloc_req = scsi_new_request; 3037 3037 sc->unit_attention_reported = scsi_disk_unit_attention_reported; 3038 3038 dc->desc = "virtual SCSI disk"; 3039 3039 - dc->props = scsi_hd_properties; 3039 3039 + device_class_set_props(dc, scsi_hd_properties); 3040 3040 dc->vmsd = &vmstate_scsi_disk_state; 3041 3041 } 3042 3042 ··· 3067 3067 sc->alloc_req = scsi_new_request; 3068 3068 sc->unit_attention_reported = scsi_disk_unit_attention_reported; 3069 3069 dc->desc = "virtual SCSI CD-ROM"; 3070 3070 - dc->props = scsi_cd_properties; 3070 3070 + device_class_set_props(dc, scsi_cd_properties); 3071 3071 dc->vmsd = &vmstate_scsi_disk_state; 3072 3072 } 3073 3073 ··· 3106 3106 sdc->update_sense = scsi_block_update_sense; 3107 3107 sdc->need_fua_emulation = scsi_block_no_fua; 3108 3108 dc->desc = "SCSI block device passthrough"; 3109 3109 - dc->props = scsi_block_properties; 3109 3109 + device_class_set_props(dc, scsi_block_properties); 3110 3110 dc->vmsd = &vmstate_scsi_disk_state; 3111 3111 } 3112 3112 ··· 3146 3146 dc->fw_name = "disk"; 3147 3147 dc->desc = "virtual SCSI disk or CD-ROM (legacy)"; 3148 3148 dc->reset = scsi_disk_reset; 3149 3149 - dc->props = scsi_disk_properties; 3149 3149 + device_class_set_props(dc, scsi_disk_properties); 3150 3150 dc->vmsd = &vmstate_scsi_disk_state; 3151 3151 } 3152 3152

+1 -1

hw/scsi/scsi-generic.c

··· 768 768 dc->fw_name = "disk"; 769 769 dc->desc = "pass through generic scsi device (/dev/sg*)"; 770 770 dc->reset = scsi_generic_reset; 771 771 - dc->props = scsi_generic_properties; 771 771 + device_class_set_props(dc, scsi_generic_properties); 772 772 dc->vmsd = &vmstate_scsi_device; 773 773 } 774 774

+1 -1

hw/scsi/spapr_vscsi.c

··· 1267 1267 k->dt_compatible = "IBM,v-scsi"; 1268 1268 k->signal_mask = 0x00000001; 1269 1269 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1270 1270 - dc->props = spapr_vscsi_properties; 1270 1270 + device_class_set_props(dc, spapr_vscsi_properties); 1271 1271 k->rtce_window_size = 0x10000000; 1272 1272 dc->vmsd = &vmstate_spapr_vscsi; 1273 1273 }

+1 -1

hw/scsi/vhost-scsi.c

··· 293 293 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 294 294 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(klass); 295 295 296 296 - dc->props = vhost_scsi_properties; 296 296 + device_class_set_props(dc, vhost_scsi_properties); 297 297 dc->vmsd = &vmstate_virtio_vhost_scsi; 298 298 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 299 299 vdc->realize = vhost_scsi_realize;

+1 -1

hw/scsi/vhost-user-scsi.c

··· 197 197 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 198 198 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(klass); 199 199 200 200 - dc->props = vhost_user_scsi_properties; 200 200 + device_class_set_props(dc, vhost_user_scsi_properties); 201 201 dc->vmsd = &vmstate_vhost_scsi; 202 202 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 203 203 vdc->realize = vhost_user_scsi_realize;

+1 -1

hw/scsi/virtio-scsi.c

··· 1006 1006 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 1007 1007 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 1008 1008 1009 1009 - dc->props = virtio_scsi_properties; 1009 1009 + device_class_set_props(dc, virtio_scsi_properties); 1010 1010 dc->vmsd = &vmstate_virtio_scsi; 1011 1011 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1012 1012 vdc->realize = virtio_scsi_device_realize;

+1 -1

hw/scsi/vmw_pvscsi.c

··· 1292 1292 &pvs_k->parent_dc_realize); 1293 1293 dc->reset = pvscsi_reset; 1294 1294 dc->vmsd = &vmstate_pvscsi; 1295 1295 - dc->props = pvscsi_properties; 1295 1295 + device_class_set_props(dc, pvscsi_properties); 1296 1296 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1297 1297 hc->unplug = pvscsi_hot_unplug; 1298 1298 hc->plug = pvscsi_hotplug;

+1 -1

hw/sd/sd.c

··· 2118 2118 SDCardClass *sc = SD_CARD_CLASS(klass); 2119 2119 2120 2120 dc->realize = sd_realize; 2121 2121 - dc->props = sd_properties; 2121 2121 + device_class_set_props(dc, sd_properties); 2122 2122 dc->vmsd = &sd_vmstate; 2123 2123 dc->reset = sd_reset; 2124 2124 dc->bus_type = TYPE_SD_BUS;

+1 -1

hw/sd/sdhci-pci.c

··· 64 64 k->vendor_id = PCI_VENDOR_ID_REDHAT; 65 65 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 66 66 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 67 67 - dc->props = sdhci_pci_properties; 67 67 + device_class_set_props(dc, sdhci_pci_properties); 68 68 69 69 sdhci_common_class_init(klass, data); 70 70 }

+1 -1

hw/sd/sdhci.c

··· 1499 1499 { 1500 1500 DeviceClass *dc = DEVICE_CLASS(klass); 1501 1501 1502 1502 - dc->props = sdhci_sysbus_properties; 1502 1502 + device_class_set_props(dc, sdhci_sysbus_properties); 1503 1503 dc->realize = sdhci_sysbus_realize; 1504 1504 dc->unrealize = sdhci_sysbus_unrealize; 1505 1505

+2 -2

hw/sparc/sun4m.c

··· 761 761 { 762 762 DeviceClass *dc = DEVICE_CLASS(klass); 763 763 764 764 - dc->props = prom_properties; 764 764 + device_class_set_props(dc, prom_properties); 765 765 dc->realize = prom_realize; 766 766 } 767 767 ··· 827 827 DeviceClass *dc = DEVICE_CLASS(klass); 828 828 829 829 dc->realize = ram_realize; 830 830 - dc->props = ram_properties; 830 830 + device_class_set_props(dc, ram_properties); 831 831 } 832 832 833 833 static const TypeInfo ram_info = {

+1 -1

hw/sparc/sun4m_iommu.c

··· 379 379 380 380 dc->reset = iommu_reset; 381 381 dc->vmsd = &vmstate_iommu; 382 382 - dc->props = iommu_properties; 382 382 + device_class_set_props(dc, iommu_properties); 383 383 } 384 384 385 385 static const TypeInfo iommu_info = {

+3 -3

hw/sparc64/sun4u.c

··· 389 389 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 390 390 k->revision = 0x01; 391 391 k->class_id = PCI_CLASS_BRIDGE_OTHER; 392 392 - dc->props = ebus_properties; 392 392 + device_class_set_props(dc, ebus_properties); 393 393 } 394 394 395 395 static const TypeInfo ebus_info = { ··· 479 479 { 480 480 DeviceClass *dc = DEVICE_CLASS(klass); 481 481 482 482 - dc->props = prom_properties; 482 482 + device_class_set_props(dc, prom_properties); 483 483 dc->realize = prom_realize; 484 484 } 485 485 ··· 540 540 DeviceClass *dc = DEVICE_CLASS(klass); 541 541 542 542 dc->realize = ram_realize; 543 543 - dc->props = ram_properties; 543 543 + device_class_set_props(dc, ram_properties); 544 544 } 545 545 546 546 static const TypeInfo ram_info = {

+1 -1

hw/ssi/aspeed_smc.c

··· 1401 1401 1402 1402 dc->realize = aspeed_smc_realize; 1403 1403 dc->reset = aspeed_smc_reset; 1404 1404 - dc->props = aspeed_smc_properties; 1404 1404 + device_class_set_props(dc, aspeed_smc_properties); 1405 1405 dc->vmsd = &vmstate_aspeed_smc; 1406 1406 mc->ctrl = data; 1407 1407 }

+1 -1

hw/ssi/xilinx_spi.c

··· 372 372 373 373 dc->realize = xilinx_spi_realize; 374 374 dc->reset = xlx_spi_reset; 375 375 - dc->props = xilinx_spi_properties; 375 375 + device_class_set_props(dc, xilinx_spi_properties); 376 376 dc->vmsd = &vmstate_xilinx_spi; 377 377 } 378 378

+2 -2

hw/ssi/xilinx_spips.c

··· 1455 1455 1456 1456 dc->realize = xilinx_spips_realize; 1457 1457 dc->reset = xilinx_spips_reset; 1458 1458 - dc->props = xilinx_spips_properties; 1458 1458 + device_class_set_props(dc, xilinx_spips_properties); 1459 1459 dc->vmsd = &vmstate_xilinx_spips; 1460 1460 1461 1461 xsc->reg_ops = &spips_ops; ··· 1471 1471 dc->realize = xlnx_zynqmp_qspips_realize; 1472 1472 dc->reset = xlnx_zynqmp_qspips_reset; 1473 1473 dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 1474 1474 - dc->props = xilinx_zynqmp_qspips_properties; 1474 1474 + device_class_set_props(dc, xilinx_zynqmp_qspips_properties); 1475 1475 xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1476 1476 xsc->rx_fifo_size = RXFF_A_Q; 1477 1477 xsc->tx_fifo_size = TXFF_A_Q;

+1 -1

hw/timer/a9gtimer.c

··· 359 359 dc->realize = a9_gtimer_realize; 360 360 dc->vmsd = &vmstate_a9_gtimer; 361 361 dc->reset = a9_gtimer_reset; 362 362 - dc->props = a9_gtimer_properties; 362 362 + device_class_set_props(dc, a9_gtimer_properties); 363 363 } 364 364 365 365 static const TypeInfo a9_gtimer_info = {

+1 -1

hw/timer/allwinner-a10-pit.c

··· 284 284 DeviceClass *dc = DEVICE_CLASS(klass); 285 285 286 286 dc->reset = a10_pit_reset; 287 287 - dc->props = a10_pit_properties; 287 287 + device_class_set_props(dc, a10_pit_properties); 288 288 dc->desc = "allwinner a10 timer"; 289 289 dc->vmsd = &vmstate_a10_pit; 290 290 }

+1 -1

hw/timer/altera_timer.c

··· 224 224 DeviceClass *dc = DEVICE_CLASS(klass); 225 225 226 226 dc->realize = altera_timer_realize; 227 227 - dc->props = altera_timer_properties; 227 227 + device_class_set_props(dc, altera_timer_properties); 228 228 dc->reset = altera_timer_reset; 229 229 } 230 230

+1 -1

hw/timer/arm_mptimer.c

··· 312 312 dc->realize = arm_mptimer_realize; 313 313 dc->vmsd = &vmstate_arm_mptimer; 314 314 dc->reset = arm_mptimer_reset; 315 315 - dc->props = arm_mptimer_properties; 315 315 + device_class_set_props(dc, arm_mptimer_properties); 316 316 } 317 317 318 318 static const TypeInfo arm_mptimer_info = {

+1 -1

hw/timer/arm_timer.c

··· 397 397 DeviceClass *k = DEVICE_CLASS(klass); 398 398 399 399 k->realize = sp804_realize; 400 400 - k->props = sp804_properties; 400 400 + device_class_set_props(k, sp804_properties); 401 401 k->vmsd = &vmstate_sp804; 402 402 } 403 403

+2 -2

hw/timer/aspeed_timer.c

··· 283 283 if (old_reload || !t->reload) { 284 284 break; 285 285 } 286 286 - 286 286 + /* fall through to re-enable */ 287 287 case TIMER_REG_STATUS: 288 288 if (timer_enabled(t)) { 289 289 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ··· 685 685 dc->reset = aspeed_timer_reset; 686 686 dc->desc = "ASPEED Timer"; 687 687 dc->vmsd = &vmstate_aspeed_timer_state; 688 688 - dc->props = aspeed_timer_properties; 688 688 + device_class_set_props(dc, aspeed_timer_properties); 689 689 } 690 690 691 691 static const TypeInfo aspeed_timer_info = {

+1 -1

hw/timer/cmsdk-apb-dualtimer.c

··· 510 510 dc->realize = cmsdk_apb_dualtimer_realize; 511 511 dc->vmsd = &cmsdk_apb_dualtimer_vmstate; 512 512 dc->reset = cmsdk_apb_dualtimer_reset; 513 513 - dc->props = cmsdk_apb_dualtimer_properties; 513 513 + device_class_set_props(dc, cmsdk_apb_dualtimer_properties); 514 514 } 515 515 516 516 static const TypeInfo cmsdk_apb_dualtimer_info = {

+1 -1

hw/timer/cmsdk-apb-timer.c

··· 260 260 dc->realize = cmsdk_apb_timer_realize; 261 261 dc->vmsd = &cmsdk_apb_timer_vmstate; 262 262 dc->reset = cmsdk_apb_timer_reset; 263 263 - dc->props = cmsdk_apb_timer_properties; 263 263 + device_class_set_props(dc, cmsdk_apb_timer_properties); 264 264 } 265 265 266 266 static const TypeInfo cmsdk_apb_timer_info = {

+1 -1

hw/timer/grlib_gptimer.c

··· 415 415 416 416 dc->realize = grlib_gptimer_realize; 417 417 dc->reset = grlib_gptimer_reset; 418 418 - dc->props = grlib_gptimer_properties; 418 418 + device_class_set_props(dc, grlib_gptimer_properties); 419 419 } 420 420 421 421 static const TypeInfo grlib_gptimer_info = {

+1 -1

hw/timer/hpet.c

··· 800 800 dc->realize = hpet_realize; 801 801 dc->reset = hpet_reset; 802 802 dc->vmsd = &vmstate_hpet; 803 803 - dc->props = hpet_device_properties; 803 803 + device_class_set_props(dc, hpet_device_properties); 804 804 } 805 805 806 806 static const TypeInfo hpet_device_info = {

+1 -1

hw/timer/i8254.c

··· 364 364 k->get_channel_info = pit_get_channel_info_common; 365 365 k->post_load = pit_post_load; 366 366 dc->reset = pit_reset; 367 367 - dc->props = pit_properties; 367 367 + device_class_set_props(dc, pit_properties); 368 368 } 369 369 370 370 static const TypeInfo pit_info = {

+1 -1

hw/timer/lm32_timer.c

··· 230 230 dc->realize = lm32_timer_realize; 231 231 dc->reset = timer_reset; 232 232 dc->vmsd = &vmstate_lm32_timer; 233 233 - dc->props = lm32_timer_properties; 233 233 + device_class_set_props(dc, lm32_timer_properties); 234 234 } 235 235 236 236 static const TypeInfo lm32_timer_info = {

+1 -1

hw/timer/milkymist-sysctl.c

··· 343 343 dc->realize = milkymist_sysctl_realize; 344 344 dc->reset = milkymist_sysctl_reset; 345 345 dc->vmsd = &vmstate_milkymist_sysctl; 346 346 - dc->props = milkymist_sysctl_properties; 346 346 + device_class_set_props(dc, milkymist_sysctl_properties); 347 347 } 348 348 349 349 static const TypeInfo milkymist_sysctl_info = {

+1 -1

hw/timer/mss-timer.c

··· 278 278 { 279 279 DeviceClass *dc = DEVICE_CLASS(klass); 280 280 281 281 - dc->props = mss_timer_properties; 281 281 + device_class_set_props(dc, mss_timer_properties); 282 282 dc->vmsd = &vmstate_mss_timer; 283 283 } 284 284

+2 -2

hw/timer/pxa2xx_timer.c

··· 562 562 DeviceClass *dc = DEVICE_CLASS(klass); 563 563 564 564 dc->desc = "PXA25x timer"; 565 565 - dc->props = pxa25x_timer_dev_properties; 565 565 + device_class_set_props(dc, pxa25x_timer_dev_properties); 566 566 } 567 567 568 568 static const TypeInfo pxa25x_timer_dev_info = { ··· 584 584 DeviceClass *dc = DEVICE_CLASS(klass); 585 585 586 586 dc->desc = "PXA27x timer"; 587 587 - dc->props = pxa27x_timer_dev_properties; 587 587 + device_class_set_props(dc, pxa27x_timer_dev_properties); 588 588 } 589 589 590 590 static const TypeInfo pxa27x_timer_dev_info = {

+1 -1

hw/timer/slavio_timer.c

··· 427 427 428 428 dc->reset = slavio_timer_reset; 429 429 dc->vmsd = &vmstate_slavio_timer; 430 430 - dc->props = slavio_timer_properties; 430 430 + device_class_set_props(dc, slavio_timer_properties); 431 431 } 432 432 433 433 static const TypeInfo slavio_timer_info = {

+1 -1

hw/timer/stm32f2xx_timer.c

··· 323 323 DeviceClass *dc = DEVICE_CLASS(klass); 324 324 325 325 dc->reset = stm32f2xx_timer_reset; 326 326 - dc->props = stm32f2xx_timer_properties; 326 326 + device_class_set_props(dc, stm32f2xx_timer_properties); 327 327 dc->vmsd = &vmstate_stm32f2xx_timer; 328 328 } 329 329

+1 -1

hw/timer/xilinx_timer.c

··· 253 253 DeviceClass *dc = DEVICE_CLASS(klass); 254 254 255 255 dc->realize = xilinx_timer_realize; 256 256 - dc->props = xilinx_timer_properties; 256 256 + device_class_set_props(dc, xilinx_timer_properties); 257 257 } 258 258 259 259 static const TypeInfo xilinx_timer_info = {

+1 -1

hw/tpm/tpm_crb.c

··· 313 313 TPMIfClass *tc = TPM_IF_CLASS(klass); 314 314 315 315 dc->realize = tpm_crb_realize; 316 316 - dc->props = tpm_crb_properties; 316 316 + device_class_set_props(dc, tpm_crb_properties); 317 317 dc->vmsd = &vmstate_tpm_crb; 318 318 dc->user_creatable = true; 319 319 tc->model = TPM_MODEL_TPM_CRB;

+1 -1

hw/tpm/tpm_tis.c

··· 1023 1023 TPMIfClass *tc = TPM_IF_CLASS(klass); 1024 1024 1025 1025 dc->realize = tpm_tis_realizefn; 1026 1026 - dc->props = tpm_tis_properties; 1026 1026 + device_class_set_props(dc, tpm_tis_properties); 1027 1027 dc->reset = tpm_tis_reset; 1028 1028 dc->vmsd = &vmstate_tpm_tis; 1029 1029 tc->model = TPM_MODEL_TPM_TIS;

+1 -1

hw/usb/bus.c

··· 768 768 k->bus_type = TYPE_USB_BUS; 769 769 k->realize = usb_qdev_realize; 770 770 k->unrealize = usb_qdev_unrealize; 771 771 - k->props = usb_props; 771 771 + device_class_set_props(k, usb_props); 772 772 } 773 773 774 774 static const TypeInfo usb_device_type_info = {

+1 -1

hw/usb/ccid-card-emulated.c

··· 603 603 cc->apdu_from_guest = emulated_apdu_from_guest; 604 604 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 605 605 dc->desc = "emulated smartcard"; 606 606 - dc->props = emulated_card_properties; 606 606 + device_class_set_props(dc, emulated_card_properties); 607 607 } 608 608 609 609 static const TypeInfo emulated_card_info = {

+1 -1

hw/usb/ccid-card-passthru.c

··· 403 403 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 404 404 dc->desc = "passthrough smartcard"; 405 405 dc->vmsd = &passthru_vmstate; 406 406 - dc->props = passthru_card_properties; 406 406 + device_class_set_props(dc, passthru_card_properties); 407 407 } 408 408 409 409 static const TypeInfo passthru_card_info = {

+1 -1

hw/usb/dev-audio.c

··· 1002 1002 USBDeviceClass *k = USB_DEVICE_CLASS(klass); 1003 1003 1004 1004 dc->vmsd = &vmstate_usb_audio; 1005 1005 - dc->props = usb_audio_properties; 1005 1005 + device_class_set_props(dc, usb_audio_properties); 1006 1006 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1007 1007 k->product_desc = "QEMU USB Audio Interface"; 1008 1008 k->realize = usb_audio_realize;

+3 -3

hw/usb/dev-hid.c

··· 819 819 uc->realize = usb_tablet_realize; 820 820 uc->product_desc = "QEMU USB Tablet"; 821 821 dc->vmsd = &vmstate_usb_ptr; 822 822 - dc->props = usb_tablet_properties; 822 822 + device_class_set_props(dc, usb_tablet_properties); 823 823 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 824 824 } 825 825 ··· 842 842 uc->realize = usb_mouse_realize; 843 843 uc->product_desc = "QEMU USB Mouse"; 844 844 dc->vmsd = &vmstate_usb_ptr; 845 845 - dc->props = usb_mouse_properties; 845 845 + device_class_set_props(dc, usb_mouse_properties); 846 846 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 847 847 } 848 848 ··· 866 866 uc->realize = usb_keyboard_realize; 867 867 uc->product_desc = "QEMU USB Keyboard"; 868 868 dc->vmsd = &vmstate_usb_kbd; 869 869 - dc->props = usb_keyboard_properties; 869 869 + device_class_set_props(dc, usb_keyboard_properties); 870 870 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 871 871 } 872 872

+1 -1

hw/usb/dev-hub.c

··· 686 686 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 687 687 dc->fw_name = "hub"; 688 688 dc->vmsd = &vmstate_usb_hub; 689 689 - dc->props = usb_hub_properties; 689 689 + device_class_set_props(dc, usb_hub_properties); 690 690 } 691 691 692 692 static const TypeInfo hub_info = {

+1 -1

hw/usb/dev-mtp.c

··· 2105 2105 dc->desc = "USB Media Transfer Protocol device"; 2106 2106 dc->fw_name = "mtp"; 2107 2107 dc->vmsd = &vmstate_usb_mtp; 2108 2108 - dc->props = mtp_properties; 2108 2108 + device_class_set_props(dc, mtp_properties); 2109 2109 } 2110 2110 2111 2111 static TypeInfo mtp_info = {

+1 -1

hw/usb/dev-network.c

··· 1409 1409 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1410 1410 dc->fw_name = "network"; 1411 1411 dc->vmsd = &vmstate_usb_net; 1412 1412 - dc->props = net_properties; 1412 1412 + device_class_set_props(dc, net_properties); 1413 1413 } 1414 1414 1415 1415 static const TypeInfo net_info = {

+2 -2

hw/usb/dev-serial.c

··· 567 567 568 568 uc->product_desc = "QEMU USB Serial"; 569 569 uc->usb_desc = &desc_serial; 570 570 - dc->props = serial_properties; 570 570 + device_class_set_props(dc, serial_properties); 571 571 } 572 572 573 573 static const TypeInfo serial_info = { ··· 588 588 589 589 uc->product_desc = "QEMU USB Braille"; 590 590 uc->usb_desc = &desc_braille; 591 591 - dc->props = braille_properties; 591 591 + device_class_set_props(dc, braille_properties); 592 592 } 593 593 594 594 static const TypeInfo braille_info = {

+2 -2

hw/usb/dev-smartcard-reader.c

··· 1456 1456 uc->unrealize = ccid_unrealize; 1457 1457 dc->desc = "CCID Rev 1.1 smartcard reader"; 1458 1458 dc->vmsd = &ccid_vmstate; 1459 1459 - dc->props = ccid_properties; 1459 1459 + device_class_set_props(dc, ccid_properties); 1460 1460 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 1461 1461 hc->unplug = qdev_simple_device_unplug_cb; 1462 1462 } ··· 1478 1478 k->bus_type = TYPE_CCID_BUS; 1479 1479 k->realize = ccid_card_realize; 1480 1480 k->unrealize = ccid_card_unrealize; 1481 1481 - k->props = ccid_props; 1481 1481 + device_class_set_props(k, ccid_props); 1482 1482 } 1483 1483 1484 1484 static const TypeInfo ccid_card_type_info = {

+1 -1

hw/usb/dev-storage.c

··· 702 702 USBDeviceClass *uc = USB_DEVICE_CLASS(klass); 703 703 704 704 uc->realize = usb_msd_storage_realize; 705 705 - dc->props = msd_properties; 705 705 + device_class_set_props(dc, msd_properties); 706 706 } 707 707 708 708 static void usb_msd_get_bootindex(Object *obj, Visitor *v, const char *name,

+1 -1

hw/usb/dev-uas.c

··· 952 952 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 953 953 dc->fw_name = "storage"; 954 954 dc->vmsd = &vmstate_usb_uas; 955 955 - dc->props = uas_properties; 955 955 + device_class_set_props(dc, uas_properties); 956 956 } 957 957 958 958 static const TypeInfo uas_info = {

+1 -1

hw/usb/hcd-ehci-pci.c

··· 161 161 k->class_id = PCI_CLASS_SERIAL_USB; 162 162 k->config_write = usb_ehci_pci_write_config; 163 163 dc->vmsd = &vmstate_ehci_pci; 164 164 - dc->props = ehci_pci_properties; 164 164 + device_class_set_props(dc, ehci_pci_properties); 165 165 dc->reset = usb_ehci_pci_reset; 166 166 } 167 167

+1 -1

hw/usb/hcd-ehci-sysbus.c

··· 82 82 83 83 dc->realize = usb_ehci_sysbus_realize; 84 84 dc->vmsd = &vmstate_ehci_sysbus; 85 85 - dc->props = ehci_sysbus_properties; 85 85 + device_class_set_props(dc, ehci_sysbus_properties); 86 86 dc->reset = usb_ehci_sysbus_reset; 87 87 set_bit(DEVICE_CATEGORY_USB, dc->categories); 88 88 }

+1 -1

hw/usb/hcd-ohci-pci.c

··· 139 139 k->class_id = PCI_CLASS_SERIAL_USB; 140 140 set_bit(DEVICE_CATEGORY_USB, dc->categories); 141 141 dc->desc = "Apple USB Controller"; 142 142 - dc->props = ohci_pci_properties; 142 142 + device_class_set_props(dc, ohci_pci_properties); 143 143 dc->hotpluggable = false; 144 144 dc->vmsd = &vmstate_ohci; 145 145 dc->reset = usb_ohci_reset_pci;

+1 -1

hw/usb/hcd-ohci.c

··· 2000 2000 dc->realize = ohci_realize_pxa; 2001 2001 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2002 2002 dc->desc = "OHCI USB Controller"; 2003 2003 - dc->props = ohci_sysbus_properties; 2003 2003 + device_class_set_props(dc, ohci_sysbus_properties); 2004 2004 dc->reset = usb_ohci_reset_sysbus; 2005 2005 } 2006 2006

+2 -2

hw/usb/hcd-uhci.c

··· 1349 1349 if (!info->unplug) { 1350 1350 /* uhci controllers in companion setups can't be hotplugged */ 1351 1351 dc->hotpluggable = false; 1352 1352 - dc->props = uhci_properties_companion; 1352 1352 + device_class_set_props(dc, uhci_properties_companion); 1353 1353 } else { 1354 1354 - dc->props = uhci_properties_standalone; 1354 1354 + device_class_set_props(dc, uhci_properties_standalone); 1355 1355 } 1356 1356 u->info = *info; 1357 1357 }

+1 -1

hw/usb/hcd-xhci-nec.c

··· 44 44 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 45 45 DeviceClass *dc = DEVICE_CLASS(klass); 46 46 47 47 - dc->props = nec_xhci_properties; 47 47 + device_class_set_props(dc, nec_xhci_properties); 48 48 k->vendor_id = PCI_VENDOR_ID_NEC; 49 49 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 50 50 k->revision = 0x03;

+1 -1

hw/usb/hcd-xhci.c

··· 3707 3707 DeviceClass *dc = DEVICE_CLASS(klass); 3708 3708 3709 3709 dc->vmsd = &vmstate_xhci; 3710 3710 - dc->props = xhci_properties; 3710 3710 + device_class_set_props(dc, xhci_properties); 3711 3711 dc->reset = xhci_reset; 3712 3712 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3713 3713 k->realize = usb_xhci_realize;

+1 -1

hw/usb/host-libusb.c

··· 1635 1635 uc->alloc_streams = usb_host_alloc_streams; 1636 1636 uc->free_streams = usb_host_free_streams; 1637 1637 dc->vmsd = &vmstate_usb_host; 1638 1638 - dc->props = usb_host_dev_properties; 1638 1638 + device_class_set_props(dc, usb_host_dev_properties); 1639 1639 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1640 1640 } 1641 1641

+1 -1

hw/usb/redirect.c

··· 2584 2584 uc->alloc_streams = usbredir_alloc_streams; 2585 2585 uc->free_streams = usbredir_free_streams; 2586 2586 dc->vmsd = &usbredir_vmstate; 2587 2587 - dc->props = usbredir_properties; 2587 2587 + device_class_set_props(dc, usbredir_properties); 2588 2588 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 2589 2589 } 2590 2590

+1 -1

hw/vfio/ap.c

··· 161 161 { 162 162 DeviceClass *dc = DEVICE_CLASS(klass); 163 163 164 164 - dc->props = vfio_ap_properties; 164 164 + device_class_set_props(dc, vfio_ap_properties); 165 165 dc->vmsd = &vfio_ap_vmstate; 166 166 dc->desc = "VFIO-based AP device assignment"; 167 167 set_bit(DEVICE_CATEGORY_MISC, dc->categories);

+1 -1

hw/vfio/ccw.c

··· 561 561 DeviceClass *dc = DEVICE_CLASS(klass); 562 562 S390CCWDeviceClass *cdc = S390_CCW_DEVICE_CLASS(klass); 563 563 564 564 - dc->props = vfio_ccw_properties; 564 564 + device_class_set_props(dc, vfio_ccw_properties); 565 565 dc->vmsd = &vfio_ccw_vmstate; 566 566 dc->desc = "VFIO-based subchannel assignment"; 567 567 set_bit(DEVICE_CATEGORY_MISC, dc->categories);

+2 -2

hw/vfio/pci.c

··· 3199 3199 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); 3200 3200 3201 3201 dc->reset = vfio_pci_reset; 3202 3202 - dc->props = vfio_pci_dev_properties; 3202 3202 + device_class_set_props(dc, vfio_pci_dev_properties); 3203 3203 dc->desc = "VFIO-based PCI device assignment"; 3204 3204 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3205 3205 pdc->realize = vfio_realize; ··· 3231 3231 { 3232 3232 DeviceClass *dc = DEVICE_CLASS(klass); 3233 3233 3234 3234 - dc->props = vfio_pci_dev_nohotplug_properties; 3234 3234 + device_class_set_props(dc, vfio_pci_dev_nohotplug_properties); 3235 3235 dc->hotpluggable = false; 3236 3236 } 3237 3237

+1 -1

hw/vfio/platform.c

··· 699 699 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 700 700 701 701 dc->realize = vfio_platform_realize; 702 702 - dc->props = vfio_platform_dev_properties; 702 702 + device_class_set_props(dc, vfio_platform_dev_properties); 703 703 dc->vmsd = &vfio_platform_vmstate; 704 704 dc->desc = "VFIO-based platform device assignment"; 705 705 sbc->connect_irq_notifier = vfio_start_irqfd_injection;

+1 -1

hw/virtio/vhost-scsi-pci.c

··· 64 64 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 65 65 k->realize = vhost_scsi_pci_realize; 66 66 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 67 67 - dc->props = vhost_scsi_pci_properties; 67 67 + device_class_set_props(dc, vhost_scsi_pci_properties); 68 68 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 69 69 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI; 70 70 pcidev_k->revision = 0x00;

+1 -1

hw/virtio/vhost-user-blk-pci.c

··· 69 69 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 70 70 71 71 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 72 72 - dc->props = vhost_user_blk_pci_properties; 72 72 + device_class_set_props(dc, vhost_user_blk_pci_properties); 73 73 k->realize = vhost_user_blk_pci_realize; 74 74 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 75 75 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;

+1 -1

hw/virtio/vhost-user-fs-pci.c

··· 55 55 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 56 56 k->realize = vhost_user_fs_pci_realize; 57 57 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 58 58 - dc->props = vhost_user_fs_pci_properties; 58 58 + device_class_set_props(dc, vhost_user_fs_pci_properties); 59 59 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 60 60 pcidev_k->device_id = 0; /* Set by virtio-pci based on virtio id */ 61 61 pcidev_k->revision = 0x00;

+1 -1

hw/virtio/vhost-user-fs.c

··· 271 271 DeviceClass *dc = DEVICE_CLASS(klass); 272 272 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 273 273 274 274 - dc->props = vuf_properties; 274 274 + device_class_set_props(dc, vuf_properties); 275 275 dc->vmsd = &vuf_vmstate; 276 276 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 277 277 vdc->realize = vuf_device_realize;

+1 -1

hw/virtio/vhost-user-scsi-pci.c

··· 70 70 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 71 71 k->realize = vhost_user_scsi_pci_realize; 72 72 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 73 73 - dc->props = vhost_user_scsi_pci_properties; 73 73 + device_class_set_props(dc, vhost_user_scsi_pci_properties); 74 74 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 75 75 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI; 76 76 pcidev_k->revision = 0x00;

+1 -1

hw/virtio/vhost-vsock-pci.c

··· 55 55 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 56 56 k->realize = vhost_vsock_pci_realize; 57 57 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 58 58 - dc->props = vhost_vsock_pci_properties; 58 58 + device_class_set_props(dc, vhost_vsock_pci_properties); 59 59 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 60 60 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_VSOCK; 61 61 pcidev_k->revision = 0x00;

+1 -1

hw/virtio/vhost-vsock.c

··· 401 401 DeviceClass *dc = DEVICE_CLASS(klass); 402 402 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 403 403 404 404 - dc->props = vhost_vsock_properties; 404 404 + device_class_set_props(dc, vhost_vsock_properties); 405 405 dc->vmsd = &vmstate_virtio_vhost_vsock; 406 406 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 407 407 vdc->realize = vhost_vsock_device_realize;

+1 -1

hw/virtio/virtio-9p-pci.c

··· 61 61 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION; 62 62 pcidev_k->class_id = 0x2; 63 63 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 64 64 - dc->props = virtio_9p_pci_properties; 64 64 + device_class_set_props(dc, virtio_9p_pci_properties); 65 65 } 66 66 67 67 static void virtio_9p_pci_instance_init(Object *obj)

+1 -1

hw/virtio/virtio-balloon-pci.c

··· 59 59 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 60 60 k->realize = virtio_balloon_pci_realize; 61 61 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 62 62 - dc->props = virtio_balloon_pci_properties; 62 62 + device_class_set_props(dc, virtio_balloon_pci_properties); 63 63 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 64 64 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BALLOON; 65 65 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;

+1 -1

hw/virtio/virtio-balloon.c

··· 932 932 DeviceClass *dc = DEVICE_CLASS(klass); 933 933 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 934 934 935 935 - dc->props = virtio_balloon_properties; 935 935 + device_class_set_props(dc, virtio_balloon_properties); 936 936 dc->vmsd = &vmstate_virtio_balloon; 937 937 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 938 938 vdc->realize = virtio_balloon_device_realize;

+1 -1

hw/virtio/virtio-blk-pci.c

··· 66 66 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 67 67 68 68 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 69 69 - dc->props = virtio_blk_pci_properties; 69 69 + device_class_set_props(dc, virtio_blk_pci_properties); 70 70 k->realize = virtio_blk_pci_realize; 71 71 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 72 72 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;

+1 -1

hw/virtio/virtio-crypto-pci.c

··· 69 69 70 70 k->realize = virtio_crypto_pci_realize; 71 71 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 72 72 - dc->props = virtio_crypto_pci_properties; 72 72 + device_class_set_props(dc, virtio_crypto_pci_properties); 73 73 pcidev_k->class_id = PCI_CLASS_OTHERS; 74 74 } 75 75

+1 -1

hw/virtio/virtio-crypto.c

··· 955 955 DeviceClass *dc = DEVICE_CLASS(klass); 956 956 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 957 957 958 958 - dc->props = virtio_crypto_properties; 958 958 + device_class_set_props(dc, virtio_crypto_properties); 959 959 dc->vmsd = &vmstate_virtio_crypto; 960 960 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 961 961 vdc->realize = virtio_crypto_device_realize;

+1 -1

hw/virtio/virtio-input-pci.c

··· 60 60 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); 61 61 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 62 62 63 63 - dc->props = virtio_input_pci_properties; 63 63 + device_class_set_props(dc, virtio_input_pci_properties); 64 64 k->realize = virtio_input_pci_realize; 65 65 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 66 66

+1 -1

hw/virtio/virtio-mmio.c

··· 712 712 dc->realize = virtio_mmio_realizefn; 713 713 dc->reset = virtio_mmio_reset; 714 714 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 715 715 - dc->props = virtio_mmio_properties; 715 715 + device_class_set_props(dc, virtio_mmio_properties); 716 716 } 717 717 718 718 static const TypeInfo virtio_mmio_info = {

+1 -1

hw/virtio/virtio-net-pci.c

··· 68 68 k->revision = VIRTIO_PCI_ABI_VERSION; 69 69 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 70 70 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 71 71 - dc->props = virtio_net_properties; 71 71 + device_class_set_props(dc, virtio_net_properties); 72 72 vpciklass->realize = virtio_net_pci_realize; 73 73 } 74 74

+2 -2

hw/virtio/virtio-pci.c

··· 1886 1886 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1887 1887 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass); 1888 1888 1889 1889 - dc->props = virtio_pci_properties; 1889 1889 + device_class_set_props(dc, virtio_pci_properties); 1890 1890 k->realize = virtio_pci_realize; 1891 1891 k->exit = virtio_pci_exit; 1892 1892 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; ··· 1925 1925 { 1926 1926 DeviceClass *dc = DEVICE_CLASS(klass); 1927 1927 1928 1928 - dc->props = virtio_pci_generic_properties; 1928 1928 + device_class_set_props(dc, virtio_pci_generic_properties); 1929 1929 } 1930 1930 1931 1931 static void virtio_pci_transitional_instance_init(Object *obj)

+1 -1

hw/virtio/virtio-pmem.c

··· 165 165 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 166 166 VirtIOPMEMClass *vpc = VIRTIO_PMEM_CLASS(klass); 167 167 168 168 - dc->props = virtio_pmem_properties; 168 168 + device_class_set_props(dc, virtio_pmem_properties); 169 169 170 170 vdc->realize = virtio_pmem_realize; 171 171 vdc->unrealize = virtio_pmem_unrealize;

+1 -1

hw/virtio/virtio-rng.c

··· 269 269 DeviceClass *dc = DEVICE_CLASS(klass); 270 270 VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass); 271 271 272 272 - dc->props = virtio_rng_properties; 272 272 + device_class_set_props(dc, virtio_rng_properties); 273 273 dc->vmsd = &vmstate_virtio_rng; 274 274 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 275 275 vdc->realize = virtio_rng_device_realize;

+1 -1

hw/virtio/virtio-scsi-pci.c

··· 76 76 77 77 k->realize = virtio_scsi_pci_realize; 78 78 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 79 79 - dc->props = virtio_scsi_pci_properties; 79 79 + device_class_set_props(dc, virtio_scsi_pci_properties); 80 80 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 81 81 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI; 82 82 pcidev_k->revision = 0x00;

+1 -1

hw/virtio/virtio-serial-pci.c

··· 84 84 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); 85 85 k->realize = virtio_serial_pci_realize; 86 86 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 87 87 - dc->props = virtio_serial_pci_properties; 87 87 + device_class_set_props(dc, virtio_serial_pci_properties); 88 88 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; 89 89 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_CONSOLE; 90 90 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;

+1 -1

hw/virtio/virtio.c

··· 3713 3713 dc->realize = virtio_device_realize; 3714 3714 dc->unrealize = virtio_device_unrealize; 3715 3715 dc->bus_type = TYPE_VIRTIO_BUS; 3716 3716 - dc->props = virtio_properties; 3716 3716 + device_class_set_props(dc, virtio_properties); 3717 3717 vdc->start_ioeventfd = virtio_device_start_ioeventfd_impl; 3718 3718 vdc->stop_ioeventfd = virtio_device_stop_ioeventfd_impl; 3719 3719

+1 -1

hw/watchdog/cmsdk-apb-watchdog.c

··· 371 371 dc->realize = cmsdk_apb_watchdog_realize; 372 372 dc->vmsd = &cmsdk_apb_watchdog_vmstate; 373 373 dc->reset = cmsdk_apb_watchdog_reset; 374 374 - dc->props = cmsdk_apb_watchdog_properties; 374 374 + device_class_set_props(dc, cmsdk_apb_watchdog_properties); 375 375 } 376 376 377 377 static const TypeInfo cmsdk_apb_watchdog_info = {

+1 -1

hw/watchdog/wdt_aspeed.c

··· 271 271 dc->reset = aspeed_wdt_reset; 272 272 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 273 273 dc->vmsd = &vmstate_aspeed_wdt; 274 274 - dc->props = aspeed_wdt_properties; 274 274 + device_class_set_props(dc, aspeed_wdt_properties); 275 275 } 276 276 277 277 static const TypeInfo aspeed_wdt_info = {

+1 -1

hw/xen/xen-bus.c

··· 1332 1332 1333 1333 dev_class->realize = xen_device_realize; 1334 1334 dev_class->unrealize = xen_device_unrealize; 1335 1335 - dev_class->props = xen_device_props; 1335 1335 + device_class_set_props(dev_class, xen_device_props); 1336 1336 dev_class->bus_type = TYPE_XEN_BUS; 1337 1337 } 1338 1338

+2 -2

hw/xen/xen-legacy-backend.c

··· 786 786 { 787 787 DeviceClass *dc = DEVICE_CLASS(klass); 788 788 789 789 - dc->props = xendev_properties; 789 789 + device_class_set_props(dc, xendev_properties); 790 790 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 791 791 /* xen-backend devices can be plugged/unplugged dynamically */ 792 792 dc->user_creatable = true; ··· 824 824 { 825 825 DeviceClass *dc = DEVICE_CLASS(klass); 826 826 827 827 - dc->props = xen_sysdev_properties; 827 827 + device_class_set_props(dc, xen_sysdev_properties); 828 828 dc->bus_type = TYPE_XENSYSBUS; 829 829 } 830 830

+1 -1

hw/xen/xen_pt.c

··· 964 964 k->config_write = xen_pt_pci_write_config; 965 965 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 966 966 dc->desc = "Assign an host PCI device with Xen"; 967 967 - dc->props = xen_pci_passthrough_properties; 967 967 + device_class_set_props(dc, xen_pci_passthrough_properties); 968 968 }; 969 969 970 970 static void xen_pci_passthrough_finalize(Object *obj)

+4

include/hw/core/cpu.h

··· 1135 1135 */ 1136 1136 bool target_words_bigendian(void); 1137 1137 1138 1138 + void cpu_class_set_parent_reset(CPUClass *cc, 1139 1139 + void (*child_reset)(CPUState *cpu), 1140 1140 + void (**parent_reset)(CPUState *cpu)); 1141 1141 + 1138 1142 #ifdef NEED_CPU_H 1139 1143 1140 1144 #ifdef CONFIG_SOFTMMU

+10 -5

include/hw/qdev-core.h

··· 100 100 DECLARE_BITMAP(categories, DEVICE_CATEGORY_MAX); 101 101 const char *fw_name; 102 102 const char *desc; 103 103 - Property *props; 103 103 + 104 104 + /* 105 105 + * The underscore at the end ensures a compile-time error if someone 106 106 + * assigns to dc->props instead of using device_class_set_props. 107 107 + */ 108 108 + Property *props_; 104 109 105 110 /* 106 111 * Can this device be instantiated with -device / device_add? ··· 258 263 const char *description; 259 264 const QEnumLookup *enum_table; 260 265 int (*print)(DeviceState *dev, Property *prop, char *dest, size_t len); 261 261 - void (*set_default_value)(Object *obj, const Property *prop); 262 262 - void (*create)(Object *obj, Property *prop, Error **errp); 266 266 + void (*set_default_value)(ObjectProperty *op, const Property *prop); 267 267 + void (*create)(ObjectClass *oc, Property *prop, Error **errp); 263 268 ObjectPropertyAccessor *get; 264 269 ObjectPropertyAccessor *set; 265 270 ObjectPropertyRelease *release; ··· 433 438 */ 434 439 void device_reset(DeviceState *dev); 435 440 441 441 + void device_class_set_props(DeviceClass *dc, Property *props); 442 442 + 436 443 void device_class_set_parent_reset(DeviceClass *dc, 437 444 DeviceReset dev_reset, 438 445 DeviceReset *parent_reset); ··· 456 463 extern bool qdev_hot_removed; 457 464 458 465 char *qdev_get_dev_path(DeviceState *dev); 459 459 - 460 460 - GSList *qdev_build_hotpluggable_device_list(Object *peripheral); 461 466 462 467 void qbus_set_hotplug_handler(BusState *bus, Object *handler, Error **errp); 463 468

+1 -2

include/hw/qdev-properties.h

··· 253 253 * qdev_property_add_static: 254 254 * @dev: Device to add the property to. 255 255 * @prop: The qdev property definition. 256 256 - * @errp: location to store error information. 257 256 * 258 257 * Add a static QOM property to @dev for qdev property @prop. 259 258 * On error, store error in @errp. Static properties access data in a struct. 260 259 * The type of the QOM property is derived from prop->info. 261 260 */ 262 262 - void qdev_property_add_static(DeviceState *dev, Property *prop, Error **errp); 261 261 + void qdev_property_add_static(DeviceState *dev, Property *prop); 263 262 264 263 void qdev_alias_all_properties(DeviceState *target, Object *source); 265 264

+1

include/qapi/qmp/qstring.h

··· 33 33 void qstring_append(QString *qstring, const char *str); 34 34 void qstring_append_chr(QString *qstring, int c); 35 35 bool qstring_is_equal(const QObject *x, const QObject *y); 36 36 + char *qstring_free(QString *qstring, bool return_str); 36 37 void qstring_destroy_obj(QObject *obj); 37 38 38 39 #endif /* QSTRING_H */

+96 -13

include/qom/object.h

··· 309 309 */ 310 310 311 311 312 312 + typedef struct ObjectProperty ObjectProperty; 313 313 + 312 314 /** 313 315 * ObjectPropertyAccessor: 314 316 * @obj: the object that owns the property ··· 356 358 const char *name, 357 359 void *opaque); 358 360 359 359 - typedef struct ObjectProperty 361 361 + /** 362 362 + * ObjectPropertyInit: 363 363 + * @obj: the object that owns the property 364 364 + * @prop: the property to set 365 365 + * 366 366 + * Called when a property is initialized. 367 367 + */ 368 368 + typedef void (ObjectPropertyInit)(Object *obj, ObjectProperty *prop); 369 369 + 370 370 + struct ObjectProperty 360 371 { 361 372 gchar *name; 362 373 gchar *type; ··· 365 376 ObjectPropertyAccessor *set; 366 377 ObjectPropertyResolve *resolve; 367 378 ObjectPropertyRelease *release; 379 379 + ObjectPropertyInit *init; 368 380 void *opaque; 369 369 - } ObjectProperty; 381 381 + QObject *defval; 382 382 + }; 370 383 371 384 /** 372 385 * ObjectUnparent: ··· 992 1005 * 993 1006 * Increase the reference count of a object. A object cannot be freed as long 994 1007 * as its reference count is greater than zero. 1008 1008 + * Returns: @obj 995 1009 */ 996 996 - void object_ref(Object *obj); 1010 1010 + Object *object_ref(Object *obj); 997 1011 998 1012 /** 999 1013 * object_unref: ··· 1044 1058 void *opaque, Error **errp); 1045 1059 1046 1060 /** 1061 1061 + * object_property_set_default_bool: 1062 1062 + * @prop: the property to set 1063 1063 + * @value: the value to be written to the property 1064 1064 + * 1065 1065 + * Set the property default value. 1066 1066 + */ 1067 1067 + void object_property_set_default_bool(ObjectProperty *prop, bool value); 1068 1068 + 1069 1069 + /** 1070 1070 + * object_property_set_default_str: 1071 1071 + * @prop: the property to set 1072 1072 + * @value: the value to be written to the property 1073 1073 + * 1074 1074 + * Set the property default value. 1075 1075 + */ 1076 1076 + void object_property_set_default_str(ObjectProperty *prop, const char *value); 1077 1077 + 1078 1078 + /** 1079 1079 + * object_property_set_default_int: 1080 1080 + * @prop: the property to set 1081 1081 + * @value: the value to be written to the property 1082 1082 + * 1083 1083 + * Set the property default value. 1084 1084 + */ 1085 1085 + void object_property_set_default_int(ObjectProperty *prop, int64_t value); 1086 1086 + 1087 1087 + /** 1088 1088 + * object_property_set_default_uint: 1089 1089 + * @prop: the property to set 1090 1090 + * @value: the value to be written to the property 1091 1091 + * 1092 1092 + * Set the property default value. 1093 1093 + */ 1094 1094 + void object_property_set_default_uint(ObjectProperty *prop, uint64_t value); 1095 1095 + 1096 1096 + /** 1047 1097 * object_property_find: 1048 1098 * @obj: the object 1049 1099 * @name: the name of the property ··· 1462 1512 typedef enum { 1463 1513 /* Unref the link pointer when the property is deleted */ 1464 1514 OBJ_PROP_LINK_STRONG = 0x1, 1515 1515 + 1516 1516 + /* private */ 1517 1517 + OBJ_PROP_LINK_DIRECT = 0x2, 1518 1518 + OBJ_PROP_LINK_CLASS = 0x4, 1465 1519 } ObjectPropertyLinkFlags; 1466 1520 1467 1521 /** ··· 1479 1533 * @obj: the object to add a property to 1480 1534 * @name: the name of the property 1481 1535 * @type: the qobj type of the link 1482 1482 - * @child: a pointer to where the link object reference is stored 1536 1536 + * @targetp: a pointer to where the link object reference is stored 1483 1537 * @check: callback to veto setting or NULL if the property is read-only 1484 1538 * @flags: additional options for the link 1485 1539 * @errp: if an error occurs, a pointer to an area to store the error ··· 1504 1558 * modified. 1505 1559 */ 1506 1560 void object_property_add_link(Object *obj, const char *name, 1507 1507 - const char *type, Object **child, 1561 1561 + const char *type, Object **targetp, 1562 1562 + void (*check)(const Object *obj, const char *name, 1563 1563 + Object *val, Error **errp), 1564 1564 + ObjectPropertyLinkFlags flags, 1565 1565 + Error **errp); 1566 1566 + 1567 1567 + ObjectProperty *object_class_property_add_link(ObjectClass *oc, 1568 1568 + const char *name, 1569 1569 + const char *type, ptrdiff_t offset, 1508 1570 void (*check)(const Object *obj, const char *name, 1509 1571 Object *val, Error **errp), 1510 1572 ObjectPropertyLinkFlags flags, ··· 1527 1589 void (*set)(Object *, const char *, Error **), 1528 1590 Error **errp); 1529 1591 1530 1530 - void object_class_property_add_str(ObjectClass *klass, const char *name, 1592 1592 + ObjectProperty *object_class_property_add_str(ObjectClass *klass, 1593 1593 + const char *name, 1531 1594 char *(*get)(Object *, Error **), 1532 1595 void (*set)(Object *, const char *, 1533 1596 Error **), ··· 1549 1612 void (*set)(Object *, bool, Error **), 1550 1613 Error **errp); 1551 1614 1552 1552 - void object_class_property_add_bool(ObjectClass *klass, const char *name, 1615 1615 + ObjectProperty *object_class_property_add_bool(ObjectClass *klass, 1616 1616 + const char *name, 1553 1617 bool (*get)(Object *, Error **), 1554 1618 void (*set)(Object *, bool, Error **), 1555 1619 Error **errp); ··· 1573 1637 void (*set)(Object *, int, Error **), 1574 1638 Error **errp); 1575 1639 1576 1576 - void object_class_property_add_enum(ObjectClass *klass, const char *name, 1640 1640 + ObjectProperty *object_class_property_add_enum(ObjectClass *klass, 1641 1641 + const char *name, 1577 1642 const char *typename, 1578 1643 const QEnumLookup *lookup, 1579 1644 int (*get)(Object *, Error **), ··· 1594 1659 void (*get)(Object *, struct tm *, Error **), 1595 1660 Error **errp); 1596 1661 1597 1597 - void object_class_property_add_tm(ObjectClass *klass, const char *name, 1662 1662 + ObjectProperty *object_class_property_add_tm(ObjectClass *klass, 1663 1663 + const char *name, 1598 1664 void (*get)(Object *, struct tm *, Error **), 1599 1665 Error **errp); 1600 1666 ··· 1610 1676 */ 1611 1677 void object_property_add_uint8_ptr(Object *obj, const char *name, 1612 1678 const uint8_t *v, Error **errp); 1613 1613 - void object_class_property_add_uint8_ptr(ObjectClass *klass, const char *name, 1679 1679 + ObjectProperty *object_class_property_add_uint8_ptr(ObjectClass *klass, 1680 1680 + const char *name, 1614 1681 const uint8_t *v, Error **errp); 1615 1682 1616 1683 /** ··· 1625 1692 */ 1626 1693 void object_property_add_uint16_ptr(Object *obj, const char *name, 1627 1694 const uint16_t *v, Error **errp); 1628 1628 - void object_class_property_add_uint16_ptr(ObjectClass *klass, const char *name, 1695 1695 + ObjectProperty *object_class_property_add_uint16_ptr(ObjectClass *klass, 1696 1696 + const char *name, 1629 1697 const uint16_t *v, Error **errp); 1630 1698 1631 1699 /** ··· 1640 1708 */ 1641 1709 void object_property_add_uint32_ptr(Object *obj, const char *name, 1642 1710 const uint32_t *v, Error **errp); 1643 1643 - void object_class_property_add_uint32_ptr(ObjectClass *klass, const char *name, 1711 1711 + ObjectProperty *object_class_property_add_uint32_ptr(ObjectClass *klass, 1712 1712 + const char *name, 1644 1713 const uint32_t *v, Error **errp); 1645 1714 1646 1715 /** ··· 1655 1724 */ 1656 1725 void object_property_add_uint64_ptr(Object *obj, const char *name, 1657 1726 const uint64_t *v, Error **errp); 1658 1658 - void object_class_property_add_uint64_ptr(ObjectClass *klass, const char *name, 1727 1727 + ObjectProperty *object_class_property_add_uint64_ptr(ObjectClass *klass, 1728 1728 + const char *name, 1659 1729 const uint64_t *v, Error **errp); 1660 1730 1661 1731 /** ··· 1766 1836 * Returns the instance_size of the given @typename. 1767 1837 */ 1768 1838 size_t object_type_get_instance_size(const char *typename); 1839 1839 + 1840 1840 + /** 1841 1841 + * object_property_help: 1842 1842 + * @name: the name of the property 1843 1843 + * @type: the type of the property 1844 1844 + * @defval: the default value 1845 1845 + * @description: description of the property 1846 1846 + * 1847 1847 + * Returns: a user-friendly formatted string describing the property 1848 1848 + * for help purposes. 1849 1849 + */ 1850 1850 + char *object_property_help(const char *name, const char *type, 1851 1851 + QObject *defval, const char *description); 1769 1852 1770 1853 G_DEFINE_AUTOPTR_CLEANUP_FUNC(Object, object_unref) 1771 1854

+2

include/sysemu/accel.h

··· 70 70 /* Called just before os_setup_post (ie just before drop OS privs) */ 71 71 void accel_setup_post(MachineState *ms); 72 72 73 73 + AccelState *current_accel(void); 74 74 + 73 75 #endif

+1

include/sysemu/runstate.h

··· 63 63 void qemu_system_killed(int signal, pid_t pid); 64 64 void qemu_system_reset(ShutdownCause reason); 65 65 void qemu_system_guest_panicked(GuestPanicInformation *info); 66 66 + void qemu_system_guest_crashloaded(GuestPanicInformation *info); 66 67 67 68 #endif 68 69

+1 -1

memory.c

··· 3104 3104 }; 3105 3105 GArray *fv_address_spaces; 3106 3106 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal); 3107 3107 - AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator); 3107 3107 + AccelClass *ac = ACCEL_GET_CLASS(current_accel()); 3108 3108 3109 3109 if (ac->has_memory) { 3110 3110 fvi.ac = ac;

+1 -1

migration/migration.c

··· 3514 3514 DeviceClass *dc = DEVICE_CLASS(klass); 3515 3515 3516 3516 dc->user_creatable = false; 3517 3517 - dc->props = migration_properties; 3517 3517 + device_class_set_props(dc, migration_properties); 3518 3518 } 3519 3519 3520 3520 static void migration_instance_finalize(Object *obj)

+26

monitor/misc.c

··· 1959 1959 g_slist_free(list); 1960 1960 } 1961 1961 1962 1962 + static int qdev_add_hotpluggable_device(Object *obj, void *opaque) 1963 1963 + { 1964 1964 + GSList **list = opaque; 1965 1965 + DeviceState *dev = (DeviceState *)object_dynamic_cast(OBJECT(obj), 1966 1966 + TYPE_DEVICE); 1967 1967 + 1968 1968 + if (dev == NULL) { 1969 1969 + return 0; 1970 1970 + } 1971 1971 + 1972 1972 + if (dev->realized && object_property_get_bool(obj, "hotpluggable", NULL)) { 1973 1973 + *list = g_slist_append(*list, dev); 1974 1974 + } 1975 1975 + 1976 1976 + return 0; 1977 1977 + } 1978 1978 + 1979 1979 + static GSList *qdev_build_hotpluggable_device_list(Object *peripheral) 1980 1980 + { 1981 1981 + GSList *list = NULL; 1982 1982 + 1983 1983 + object_child_foreach(peripheral, qdev_add_hotpluggable_device, &list); 1984 1984 + 1985 1985 + return list; 1986 1986 + } 1987 1987 + 1962 1988 static void peripheral_device_del_completion(ReadLineState *rs, 1963 1989 const char *str, size_t len) 1964 1990 {

+6 -1

qapi/qom.json

··· 26 26 # 27 27 # @description: if specified, the description of the property. 28 28 # 29 29 + # @default-value: the default value, if any (since 5.0) 30 30 + # 29 31 # Since: 1.2 30 32 ## 31 33 { 'struct': 'ObjectPropertyInfo', 32 32 - 'data': { 'name': 'str', 'type': 'str', '*description': 'str' } } 34 34 + 'data': { 'name': 'str', 35 35 + 'type': 'str', 36 36 + '*description': 'str', 37 37 + '*default-value': 'any' } } 33 38 34 39 ## 35 40 # @qom-list:

+22 -2

qapi/run-state.json

··· 357 357 'data': { 'action': 'GuestPanicAction', '*info': 'GuestPanicInformation' } } 358 358 359 359 ## 360 360 + # @GUEST_CRASHLOADED: 361 361 + # 362 362 + # Emitted when guest OS crash loaded is detected 363 363 + # 364 364 + # @action: action that has been taken, currently always "run" 365 365 + # 366 366 + # @info: information about a panic 367 367 + # 368 368 + # Since: 5.0 369 369 + # 370 370 + # Example: 371 371 + # 372 372 + # <- { "event": "GUEST_CRASHLOADED", 373 373 + # "data": { "action": "run" } } 374 374 + # 375 375 + ## 376 376 + { 'event': 'GUEST_CRASHLOADED', 377 377 + 'data': { 'action': 'GuestPanicAction', '*info': 'GuestPanicInformation' } } 378 378 + 379 379 + ## 360 380 # @GuestPanicAction: 361 381 # 362 382 # An enumeration of the actions taken when guest OS panic is detected 363 383 # 364 384 # @pause: system pauses 365 385 # 366 366 - # Since: 2.1 (poweroff since 2.8) 386 386 + # Since: 2.1 (poweroff since 2.8, run since 5.0) 367 387 ## 368 388 { 'enum': 'GuestPanicAction', 369 369 - 'data': [ 'pause', 'poweroff' ] } 389 389 + 'data': [ 'pause', 'poweroff', 'run' ] } 370 390 371 391 ## 372 392 # @GuestPanicInformationType:

+16 -12

qdev-monitor.c

··· 37 37 #include "sysemu/sysemu.h" 38 38 #include "migration/misc.h" 39 39 #include "migration/migration.h" 40 40 + #include "qemu/cutils.h" 40 41 41 42 /* 42 43 * Aliases were a bad idea from the start. Let's keep them ··· 256 257 const char *driver; 257 258 ObjectPropertyInfoList *prop_list; 258 259 ObjectPropertyInfoList *prop; 260 260 + GPtrArray *array; 261 261 + int i; 259 262 260 263 driver = qemu_opt_get(opts, "driver"); 261 264 if (driver && is_help_option(driver)) { ··· 285 288 } else { 286 289 qemu_printf("There are no options for %s.\n", driver); 287 290 } 291 291 + array = g_ptr_array_new(); 288 292 for (prop = prop_list; prop; prop = prop->next) { 289 289 - int len; 290 290 - qemu_printf(" %s=<%s>%n", prop->value->name, prop->value->type, &len); 291 291 - if (prop->value->has_description) { 292 292 - if (len < 24) { 293 293 - qemu_printf("%*s", 24 - len, ""); 294 294 - } 295 295 - qemu_printf(" - %s\n", prop->value->description); 296 296 - } else { 297 297 - qemu_printf("\n"); 298 298 - } 293 293 + g_ptr_array_add(array, 294 294 + object_property_help(prop->value->name, 295 295 + prop->value->type, 296 296 + prop->value->default_value, 297 297 + prop->value->description)); 298 298 + } 299 299 + g_ptr_array_sort(array, (GCompareFunc)qemu_pstrcmp0); 300 300 + for (i = 0; i < array->len; i++) { 301 301 + printf("%s\n", (char *)array->pdata[i]); 299 302 } 300 300 - 303 303 + g_ptr_array_set_free_func(array, g_free); 304 304 + g_ptr_array_free(array, true); 301 305 qapi_free_ObjectPropertyInfoList(prop_list); 302 306 return 1; 303 307 ··· 748 752 } 749 753 class = object_get_class(OBJECT(dev)); 750 754 do { 751 751 - qdev_print_props(mon, dev, DEVICE_CLASS(class)->props, indent); 755 755 + qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent); 752 756 class = object_class_get_parent(class); 753 757 } while (class != object_class_by_name(TYPE_DEVICE)); 754 758 bus_print_dev(dev->parent_bus, mon, dev, indent);

+2 -2

qga/vss-win32/Makefile.objs

··· 5 5 obj-qga-vss-dll-obj-y = $(addprefix $(obj)/, $(qga-vss-dll-obj-y)) 6 6 $(obj-qga-vss-dll-obj-y): QEMU_CXXFLAGS := $(filter-out -fstack-protector-all -fstack-protector-strong, $(QEMU_CXXFLAGS)) -Wno-unknown-pragmas -Wno-delete-non-virtual-dtor 7 7 8 8 - $(obj)/qga-vss.dll: LDFLAGS = -shared -Wl,--add-stdcall-alias,--enable-stdcall-fixup -lglib-2.0 -lole32 -loleaut32 -lshlwapi -luuid -lintl -lws2_32 -static 8 8 + QGA_VSS_LDFLAGS = -shared -Wl,--add-stdcall-alias,--enable-stdcall-fixup -lglib-2.0 -lole32 -loleaut32 -lshlwapi -luuid -lintl -lws2_32 -static 9 9 $(obj)/qga-vss.dll: $(obj-qga-vss-dll-obj-y) $(SRC_PATH)/$(obj)/qga-vss.def 10 10 - $(call quiet-command,$(CXX) -o $@ $(qga-vss-dll-obj-y) $(SRC_PATH)/qga/vss-win32/qga-vss.def $(CXXFLAGS) $(LDFLAGS),"LINK","$(TARGET_DIR)$@") 10 10 + $(call quiet-command,$(CXX) -o $@ $(qga-vss-dll-obj-y) $(SRC_PATH)/qga/vss-win32/qga-vss.def $(CXXFLAGS) $(QGA_VSS_LDFLAGS),"LINK","$(TARGET_DIR)$@") 11 11 12 12 13 13 # rules to build qga-provider.tlb

+22 -5

qobject/qstring.c

··· 150 150 } 151 151 152 152 /** 153 153 + * qstring_free(): Free the memory allocated by a QString object 154 154 + * 155 155 + * Return: if @return_str, return the underlying string, to be 156 156 + * g_free(), otherwise NULL is returned. 157 157 + */ 158 158 + char *qstring_free(QString *qstring, bool return_str) 159 159 + { 160 160 + char *rv = NULL; 161 161 + 162 162 + if (return_str) { 163 163 + rv = qstring->string; 164 164 + } else { 165 165 + g_free(qstring->string); 166 166 + } 167 167 + 168 168 + g_free(qstring); 169 169 + 170 170 + return rv; 171 171 + } 172 172 + 173 173 + /** 153 174 * qstring_destroy_obj(): Free all memory allocated by a QString 154 175 * object 155 176 */ 156 177 void qstring_destroy_obj(QObject *obj) 157 178 { 158 158 - QString *qs; 159 159 - 160 179 assert(obj != NULL); 161 161 - qs = qobject_to(QString, obj); 162 162 - g_free(qs->string); 163 163 - g_free(qs); 180 180 + qstring_free(qobject_to(QString, obj), FALSE); 164 181 }

+229 -70

qom/object.c

··· 19 19 #include "qapi/visitor.h" 20 20 #include "qapi/string-input-visitor.h" 21 21 #include "qapi/string-output-visitor.h" 22 22 + #include "qapi/qobject-input-visitor.h" 22 23 #include "qapi/qapi-builtin-visit.h" 23 24 #include "qapi/qmp/qerror.h" 25 25 + #include "qapi/qmp/qjson.h" 24 26 #include "trace.h" 25 27 26 28 /* TODO: replace QObject with a simpler visitor to avoid a dependency ··· 173 175 { 174 176 if (!type->parent_type && type->parent) { 175 177 type->parent_type = type_get_by_name(type->parent); 176 176 - g_assert(type->parent_type != NULL); 178 178 + if (!type->parent_type) { 179 179 + fprintf(stderr, "Type '%s' is missing its parent '%s'\n", 180 180 + type->name, type->parent); 181 181 + abort(); 182 182 + } 177 183 } 178 184 179 185 return type->parent_type; ··· 264 270 { 265 271 ObjectProperty *prop = data; 266 272 273 273 + if (prop->defval) { 274 274 + qobject_unref(prop->defval); 275 275 + prop->defval = NULL; 276 276 + } 267 277 g_free(prop->name); 268 278 g_free(prop->type); 269 279 g_free(prop->description); ··· 303 313 int i; 304 314 305 315 g_assert(parent->class_size <= ti->class_size); 316 316 + g_assert(parent->instance_size <= ti->instance_size); 306 317 memcpy(ti->class, parent->class, parent->class_size); 307 318 ti->class->interfaces = NULL; 308 319 ti->class->properties = g_hash_table_new_full( 309 309 - g_str_hash, g_str_equal, g_free, object_property_free); 320 320 + g_str_hash, g_str_equal, NULL, object_property_free); 310 321 311 322 for (e = parent->class->interfaces; e; e = e->next) { 312 323 InterfaceClass *iface = e->data; ··· 317 328 318 329 for (i = 0; i < ti->num_interfaces; i++) { 319 330 TypeImpl *t = type_get_by_name(ti->interfaces[i].typename); 331 331 + if (!t) { 332 332 + error_report("missing interface '%s' for object '%s'", 333 333 + ti->interfaces[i].typename, parent->name); 334 334 + abort(); 335 335 + } 320 336 for (e = ti->class->interfaces; e; e = e->next) { 321 337 TypeImpl *target_type = OBJECT_CLASS(e->data)->type; 322 338 ··· 333 349 } 334 350 } else { 335 351 ti->class->properties = g_hash_table_new_full( 336 336 - g_str_hash, g_str_equal, g_free, object_property_free); 352 352 + g_str_hash, g_str_equal, NULL, object_property_free); 337 353 } 338 354 339 355 ti->class->type = ti; ··· 468 484 } 469 485 } 470 486 487 487 + static void object_class_property_init_all(Object *obj) 488 488 + { 489 489 + ObjectPropertyIterator iter; 490 490 + ObjectProperty *prop; 491 491 + 492 492 + object_class_property_iter_init(&iter, object_get_class(obj)); 493 493 + while ((prop = object_property_iter_next(&iter))) { 494 494 + if (prop->init) { 495 495 + prop->init(obj, prop); 496 496 + } 497 497 + } 498 498 + } 499 499 + 471 500 static void object_initialize_with_type(void *data, size_t size, TypeImpl *type) 472 501 { 473 502 Object *obj = data; ··· 481 510 memset(obj, 0, type->instance_size); 482 511 obj->class = type->class; 483 512 object_ref(obj); 513 513 + object_class_property_init_all(obj); 484 514 obj->properties = g_hash_table_new_full(g_str_hash, g_str_equal, 485 515 NULL, object_property_free); 486 516 object_init_with_type(obj, type); ··· 562 592 563 593 static void object_property_del_all(Object *obj) 564 594 { 595 595 + g_autoptr(GHashTable) done = g_hash_table_new(NULL, NULL); 565 596 ObjectProperty *prop; 566 566 - GHashTableIter iter; 567 567 - gpointer key, value; 597 597 + ObjectPropertyIterator iter; 568 598 bool released; 569 599 570 600 do { 571 601 released = false; 572 572 - g_hash_table_iter_init(&iter, obj->properties); 573 573 - while (g_hash_table_iter_next(&iter, &key, &value)) { 574 574 - prop = value; 575 575 - if (prop->release) { 576 576 - prop->release(obj, prop->name, prop->opaque); 577 577 - prop->release = NULL; 578 578 - released = true; 579 579 - break; 602 602 + object_property_iter_init(&iter, obj); 603 603 + while ((prop = object_property_iter_next(&iter)) != NULL) { 604 604 + if (g_hash_table_add(done, prop)) { 605 605 + if (prop->release) { 606 606 + prop->release(obj, prop->name, prop->opaque); 607 607 + released = true; 608 608 + break; 609 609 + } 580 610 } 581 581 - g_hash_table_iter_remove(&iter); 582 611 } 583 612 } while (released); 584 613 ··· 1078 1107 object_class_cmp); 1079 1108 } 1080 1109 1081 1081 - void object_ref(Object *obj) 1110 1110 + Object *object_ref(Object *obj) 1082 1111 { 1083 1112 if (!obj) { 1084 1084 - return; 1113 1113 + return NULL; 1085 1114 } 1086 1115 atomic_inc(&obj->ref); 1116 1116 + return obj; 1087 1117 } 1088 1118 1089 1119 void object_unref(Object *obj) ··· 1177 1207 prop->release = release; 1178 1208 prop->opaque = opaque; 1179 1209 1180 1180 - g_hash_table_insert(klass->properties, g_strdup(name), prop); 1210 1210 + g_hash_table_insert(klass->properties, prop->name, prop); 1181 1211 1182 1212 return prop; 1183 1213 } ··· 1414 1444 return retval; 1415 1445 } 1416 1446 1447 1447 + static void object_property_init_defval(Object *obj, ObjectProperty *prop) 1448 1448 + { 1449 1449 + Visitor *v = qobject_input_visitor_new(prop->defval); 1450 1450 + 1451 1451 + assert(prop->set != NULL); 1452 1452 + prop->set(obj, v, prop->name, prop->opaque, &error_abort); 1453 1453 + 1454 1454 + visit_free(v); 1455 1455 + } 1456 1456 + 1457 1457 + static void object_property_set_default(ObjectProperty *prop, QObject *defval) 1458 1458 + { 1459 1459 + assert(!prop->defval); 1460 1460 + assert(!prop->init); 1461 1461 + 1462 1462 + prop->defval = defval; 1463 1463 + prop->init = object_property_init_defval; 1464 1464 + } 1465 1465 + 1466 1466 + void object_property_set_default_bool(ObjectProperty *prop, bool value) 1467 1467 + { 1468 1468 + object_property_set_default(prop, QOBJECT(qbool_from_bool(value))); 1469 1469 + } 1470 1470 + 1471 1471 + void object_property_set_default_str(ObjectProperty *prop, const char *value) 1472 1472 + { 1473 1473 + object_property_set_default(prop, QOBJECT(qstring_from_str(value))); 1474 1474 + } 1475 1475 + 1476 1476 + void object_property_set_default_int(ObjectProperty *prop, int64_t value) 1477 1477 + { 1478 1478 + object_property_set_default(prop, QOBJECT(qnum_from_int(value))); 1479 1479 + } 1480 1480 + 1481 1481 + void object_property_set_default_uint(ObjectProperty *prop, uint64_t value) 1482 1482 + { 1483 1483 + object_property_set_default(prop, QOBJECT(qnum_from_uint(value))); 1484 1484 + } 1485 1485 + 1417 1486 void object_property_set_uint(Object *obj, uint64_t value, 1418 1487 const char *name, Error **errp) 1419 1488 { ··· 1644 1713 } 1645 1714 1646 1715 typedef struct { 1647 1647 - Object **child; 1716 1716 + union { 1717 1717 + Object **targetp; 1718 1718 + Object *target; /* if OBJ_PROP_LINK_DIRECT, when holding the pointer */ 1719 1719 + ptrdiff_t offset; /* if OBJ_PROP_LINK_CLASS */ 1720 1720 + }; 1648 1721 void (*check)(const Object *, const char *, Object *, Error **); 1649 1722 ObjectPropertyLinkFlags flags; 1650 1723 } LinkProperty; 1651 1724 1725 1725 + static Object ** 1726 1726 + object_link_get_targetp(Object *obj, LinkProperty *lprop) 1727 1727 + { 1728 1728 + if (lprop->flags & OBJ_PROP_LINK_DIRECT) { 1729 1729 + return &lprop->target; 1730 1730 + } else if (lprop->flags & OBJ_PROP_LINK_CLASS) { 1731 1731 + return (void *)obj + lprop->offset; 1732 1732 + } else { 1733 1733 + return lprop->targetp; 1734 1734 + } 1735 1735 + } 1736 1736 + 1652 1737 static void object_get_link_property(Object *obj, Visitor *v, 1653 1738 const char *name, void *opaque, 1654 1739 Error **errp) 1655 1740 { 1656 1741 LinkProperty *lprop = opaque; 1657 1657 - Object **child = lprop->child; 1742 1742 + Object **targetp = object_link_get_targetp(obj, lprop); 1658 1743 gchar *path; 1659 1744 1660 1660 - if (*child) { 1661 1661 - path = object_get_canonical_path(*child); 1745 1745 + if (*targetp) { 1746 1746 + path = object_get_canonical_path(*targetp); 1662 1747 visit_type_str(v, name, &path, errp); 1663 1748 g_free(path); 1664 1749 } else { ··· 1713 1798 { 1714 1799 Error *local_err = NULL; 1715 1800 LinkProperty *prop = opaque; 1716 1716 - Object **child = prop->child; 1717 1717 - Object *old_target = *child; 1801 1801 + Object **targetp = object_link_get_targetp(obj, prop); 1802 1802 + Object *old_target = *targetp; 1718 1803 Object *new_target = NULL; 1719 1804 char *path = NULL; 1720 1805 ··· 1736 1821 return; 1737 1822 } 1738 1823 1739 1739 - *child = new_target; 1740 1740 - if (prop->flags == OBJ_PROP_LINK_STRONG) { 1824 1824 + *targetp = new_target; 1825 1825 + if (prop->flags & OBJ_PROP_LINK_STRONG) { 1741 1826 object_ref(new_target); 1742 1827 object_unref(old_target); 1743 1828 } ··· 1747 1832 { 1748 1833 LinkProperty *lprop = opaque; 1749 1834 1750 1750 - return *lprop->child; 1835 1835 + return *object_link_get_targetp(parent, lprop); 1751 1836 } 1752 1837 1753 1838 static void object_release_link_property(Object *obj, const char *name, 1754 1839 void *opaque) 1755 1840 { 1756 1841 LinkProperty *prop = opaque; 1842 1842 + Object **targetp = object_link_get_targetp(obj, prop); 1757 1843 1758 1758 - if ((prop->flags & OBJ_PROP_LINK_STRONG) && *prop->child) { 1759 1759 - object_unref(*prop->child); 1844 1844 + if ((prop->flags & OBJ_PROP_LINK_STRONG) && *targetp) { 1845 1845 + object_unref(*targetp); 1846 1846 + } 1847 1847 + if (!(prop->flags & OBJ_PROP_LINK_CLASS)) { 1848 1848 + g_free(prop); 1760 1849 } 1761 1761 - g_free(prop); 1762 1850 } 1763 1851 1764 1764 - void object_property_add_link(Object *obj, const char *name, 1765 1765 - const char *type, Object **child, 1766 1766 - void (*check)(const Object *, const char *, 1767 1767 - Object *, Error **), 1768 1768 - ObjectPropertyLinkFlags flags, 1769 1769 - Error **errp) 1852 1852 + static void object_add_link_prop(Object *obj, const char *name, 1853 1853 + const char *type, void *ptr, 1854 1854 + void (*check)(const Object *, const char *, 1855 1855 + Object *, Error **), 1856 1856 + ObjectPropertyLinkFlags flags, 1857 1857 + Error **errp) 1770 1858 { 1771 1859 Error *local_err = NULL; 1772 1860 LinkProperty *prop = g_malloc(sizeof(*prop)); 1773 1861 gchar *full_type; 1774 1862 ObjectProperty *op; 1775 1863 1776 1776 - prop->child = child; 1864 1864 + if (flags & OBJ_PROP_LINK_DIRECT) { 1865 1865 + prop->target = ptr; 1866 1866 + } else { 1867 1867 + prop->targetp = ptr; 1868 1868 + } 1777 1869 prop->check = check; 1778 1870 prop->flags = flags; 1779 1871 ··· 1797 1889 g_free(full_type); 1798 1890 } 1799 1891 1800 1800 - void object_property_add_const_link(Object *obj, const char *name, 1801 1801 - Object *target, Error **errp) 1892 1892 + void object_property_add_link(Object *obj, const char *name, 1893 1893 + const char *type, Object **targetp, 1894 1894 + void (*check)(const Object *, const char *, 1895 1895 + Object *, Error **), 1896 1896 + ObjectPropertyLinkFlags flags, 1897 1897 + Error **errp) 1802 1898 { 1803 1803 - char *link_type; 1899 1899 + object_add_link_prop(obj, name, type, targetp, check, flags, errp); 1900 1900 + } 1901 1901 + 1902 1902 + ObjectProperty * 1903 1903 + object_class_property_add_link(ObjectClass *oc, 1904 1904 + const char *name, 1905 1905 + const char *type, ptrdiff_t offset, 1906 1906 + void (*check)(const Object *obj, const char *name, 1907 1907 + Object *val, Error **errp), 1908 1908 + ObjectPropertyLinkFlags flags, 1909 1909 + Error **errp) 1910 1910 + { 1911 1911 + Error *local_err = NULL; 1912 1912 + LinkProperty *prop = g_new0(LinkProperty, 1); 1913 1913 + gchar *full_type; 1804 1914 ObjectProperty *op; 1805 1915 1806 1806 - link_type = g_strdup_printf("link<%s>", object_get_typename(target)); 1807 1807 - op = object_property_add(obj, name, link_type, 1808 1808 - object_get_child_property, NULL, 1809 1809 - NULL, target, errp); 1810 1810 - if (op != NULL) { 1811 1811 - op->resolve = object_resolve_child_property; 1916 1916 + prop->offset = offset; 1917 1917 + prop->check = check; 1918 1918 + prop->flags = flags | OBJ_PROP_LINK_CLASS; 1919 1919 + 1920 1920 + full_type = g_strdup_printf("link<%s>", type); 1921 1921 + 1922 1922 + op = object_class_property_add(oc, name, full_type, 1923 1923 + object_get_link_property, 1924 1924 + check ? object_set_link_property : NULL, 1925 1925 + object_release_link_property, 1926 1926 + prop, 1927 1927 + &local_err); 1928 1928 + if (local_err) { 1929 1929 + error_propagate(errp, local_err); 1930 1930 + g_free(prop); 1931 1931 + goto out; 1812 1932 } 1813 1813 - g_free(link_type); 1933 1933 + 1934 1934 + op->resolve = object_resolve_link_property; 1935 1935 + 1936 1936 + out: 1937 1937 + g_free(full_type); 1938 1938 + return op; 1939 1939 + } 1940 1940 + 1941 1941 + void object_property_add_const_link(Object *obj, const char *name, 1942 1942 + Object *target, Error **errp) 1943 1943 + { 1944 1944 + object_add_link_prop(obj, name, object_get_typename(target), target, 1945 1945 + NULL, OBJ_PROP_LINK_DIRECT, errp); 1814 1946 } 1815 1947 1816 1948 gchar *object_get_canonical_path_component(Object *obj) ··· 2041 2173 } 2042 2174 } 2043 2175 2044 2044 - void object_class_property_add_str(ObjectClass *klass, const char *name, 2176 2176 + ObjectProperty * 2177 2177 + object_class_property_add_str(ObjectClass *klass, const char *name, 2045 2178 char *(*get)(Object *, Error **), 2046 2179 void (*set)(Object *, const char *, 2047 2180 Error **), ··· 2049 2182 { 2050 2183 Error *local_err = NULL; 2051 2184 StringProperty *prop = g_malloc0(sizeof(*prop)); 2185 2185 + ObjectProperty *rv; 2052 2186 2053 2187 prop->get = get; 2054 2188 prop->set = set; 2055 2189 2056 2056 - object_class_property_add(klass, name, "string", 2190 2190 + rv = object_class_property_add(klass, name, "string", 2057 2191 get ? property_get_str : NULL, 2058 2192 set ? property_set_str : NULL, 2059 2059 - property_release_str, 2193 2193 + NULL, 2060 2194 prop, &local_err); 2061 2195 if (local_err) { 2062 2196 error_propagate(errp, local_err); 2063 2197 g_free(prop); 2064 2198 } 2199 2199 + 2200 2200 + return rv; 2065 2201 } 2066 2202 2067 2203 typedef struct BoolProperty ··· 2131 2267 } 2132 2268 } 2133 2269 2134 2134 - void object_class_property_add_bool(ObjectClass *klass, const char *name, 2270 2270 + ObjectProperty * 2271 2271 + object_class_property_add_bool(ObjectClass *klass, const char *name, 2135 2272 bool (*get)(Object *, Error **), 2136 2273 void (*set)(Object *, bool, Error **), 2137 2274 Error **errp) 2138 2275 { 2139 2276 Error *local_err = NULL; 2140 2277 BoolProperty *prop = g_malloc0(sizeof(*prop)); 2278 2278 + ObjectProperty *rv; 2141 2279 2142 2280 prop->get = get; 2143 2281 prop->set = set; 2144 2282 2145 2145 - object_class_property_add(klass, name, "bool", 2283 2283 + rv = object_class_property_add(klass, name, "bool", 2146 2284 get ? property_get_bool : NULL, 2147 2285 set ? property_set_bool : NULL, 2148 2148 - property_release_bool, 2286 2286 + NULL, 2149 2287 prop, &local_err); 2150 2288 if (local_err) { 2151 2289 error_propagate(errp, local_err); 2152 2290 g_free(prop); 2153 2291 } 2292 2292 + 2293 2293 + return rv; 2154 2294 } 2155 2295 2156 2296 static void property_get_enum(Object *obj, Visitor *v, const char *name, ··· 2216 2356 } 2217 2357 } 2218 2358 2219 2219 - void object_class_property_add_enum(ObjectClass *klass, const char *name, 2359 2359 + ObjectProperty * 2360 2360 + object_class_property_add_enum(ObjectClass *klass, const char *name, 2220 2361 const char *typename, 2221 2362 const QEnumLookup *lookup, 2222 2363 int (*get)(Object *, Error **), ··· 2225 2366 { 2226 2367 Error *local_err = NULL; 2227 2368 EnumProperty *prop = g_malloc(sizeof(*prop)); 2369 2369 + ObjectProperty *rv; 2228 2370 2229 2371 prop->lookup = lookup; 2230 2372 prop->get = get; 2231 2373 prop->set = set; 2232 2374 2233 2233 - object_class_property_add(klass, name, typename, 2375 2375 + rv = object_class_property_add(klass, name, typename, 2234 2376 get ? property_get_enum : NULL, 2235 2377 set ? property_set_enum : NULL, 2236 2236 - property_release_enum, 2378 2378 + NULL, 2237 2379 prop, &local_err); 2238 2380 if (local_err) { 2239 2381 error_propagate(errp, local_err); 2240 2382 g_free(prop); 2241 2383 } 2384 2384 + 2385 2385 + return rv; 2242 2386 } 2243 2387 2244 2388 typedef struct TMProperty { ··· 2319 2463 } 2320 2464 } 2321 2465 2322 2322 - void object_class_property_add_tm(ObjectClass *klass, const char *name, 2466 2466 + ObjectProperty * 2467 2467 + object_class_property_add_tm(ObjectClass *klass, const char *name, 2323 2468 void (*get)(Object *, struct tm *, Error **), 2324 2469 Error **errp) 2325 2470 { 2326 2471 Error *local_err = NULL; 2327 2472 TMProperty *prop = g_malloc0(sizeof(*prop)); 2473 2473 + ObjectProperty *rv; 2328 2474 2329 2475 prop->get = get; 2330 2476 2331 2331 - object_class_property_add(klass, name, "struct tm", 2477 2477 + rv = object_class_property_add(klass, name, "struct tm", 2332 2478 get ? property_get_tm : NULL, NULL, 2333 2333 - property_release_tm, 2479 2479 + NULL, 2334 2480 prop, &local_err); 2335 2481 if (local_err) { 2336 2482 error_propagate(errp, local_err); 2337 2483 g_free(prop); 2338 2484 } 2485 2485 + 2486 2486 + return rv; 2339 2487 } 2340 2488 2341 2489 static char *qdev_get_type(Object *obj, Error **errp) ··· 2378 2526 NULL, NULL, (void *)v, errp); 2379 2527 } 2380 2528 2381 2381 - void object_class_property_add_uint8_ptr(ObjectClass *klass, const char *name, 2529 2529 + ObjectProperty * 2530 2530 + object_class_property_add_uint8_ptr(ObjectClass *klass, const char *name, 2382 2531 const uint8_t *v, Error **errp) 2383 2532 { 2384 2384 - object_class_property_add(klass, name, "uint8", property_get_uint8_ptr, 2385 2385 - NULL, NULL, (void *)v, errp); 2533 2533 + return object_class_property_add(klass, name, "uint8", 2534 2534 + property_get_uint8_ptr, 2535 2535 + NULL, NULL, (void *)v, errp); 2386 2536 } 2387 2537 2388 2538 void object_property_add_uint16_ptr(Object *obj, const char *name, ··· 2392 2542 NULL, NULL, (void *)v, errp); 2393 2543 } 2394 2544 2395 2395 - void object_class_property_add_uint16_ptr(ObjectClass *klass, const char *name, 2545 2545 + ObjectProperty * 2546 2546 + object_class_property_add_uint16_ptr(ObjectClass *klass, const char *name, 2396 2547 const uint16_t *v, Error **errp) 2397 2548 { 2398 2398 - object_class_property_add(klass, name, "uint16", property_get_uint16_ptr, 2399 2399 - NULL, NULL, (void *)v, errp); 2549 2549 + return object_class_property_add(klass, name, "uint16", 2550 2550 + property_get_uint16_ptr, 2551 2551 + NULL, NULL, (void *)v, errp); 2400 2552 } 2401 2553 2402 2554 void object_property_add_uint32_ptr(Object *obj, const char *name, ··· 2406 2558 NULL, NULL, (void *)v, errp); 2407 2559 } 2408 2560 2409 2409 - void object_class_property_add_uint32_ptr(ObjectClass *klass, const char *name, 2561 2561 + ObjectProperty * 2562 2562 + object_class_property_add_uint32_ptr(ObjectClass *klass, const char *name, 2410 2563 const uint32_t *v, Error **errp) 2411 2564 { 2412 2412 - object_class_property_add(klass, name, "uint32", property_get_uint32_ptr, 2413 2413 - NULL, NULL, (void *)v, errp); 2565 2565 + return object_class_property_add(klass, name, "uint32", 2566 2566 + property_get_uint32_ptr, 2567 2567 + NULL, NULL, (void *)v, errp); 2414 2568 } 2415 2569 2416 2570 void object_property_add_uint64_ptr(Object *obj, const char *name, ··· 2420 2574 NULL, NULL, (void *)v, errp); 2421 2575 } 2422 2576 2423 2423 - void object_class_property_add_uint64_ptr(ObjectClass *klass, const char *name, 2577 2577 + ObjectProperty * 2578 2578 + object_class_property_add_uint64_ptr(ObjectClass *klass, const char *name, 2424 2579 const uint64_t *v, Error **errp) 2425 2580 { 2426 2426 - object_class_property_add(klass, name, "uint64", property_get_uint64_ptr, 2427 2427 - NULL, NULL, (void *)v, errp); 2581 2581 + return object_class_property_add(klass, name, "uint64", 2582 2582 + property_get_uint64_ptr, 2583 2583 + NULL, NULL, (void *)v, errp); 2428 2584 } 2429 2585 2430 2586 typedef struct { ··· 2501 2657 goto out; 2502 2658 } 2503 2659 op->resolve = property_resolve_alias; 2660 2660 + if (target_prop->defval) { 2661 2661 + op->defval = qobject_ref(target_prop->defval); 2662 2662 + } 2504 2663 2505 2664 object_property_set_description(obj, op->name, 2506 2665 target_prop->description,

+28 -11

qom/object_interfaces.c

··· 4 4 #include "qapi/error.h" 5 5 #include "qapi/qmp/qdict.h" 6 6 #include "qapi/qmp/qerror.h" 7 7 + #include "qapi/qmp/qjson.h" 8 8 + #include "qapi/qmp/qstring.h" 7 9 #include "qom/object_interfaces.h" 8 10 #include "qemu/help_option.h" 9 11 #include "qemu/module.h" ··· 158 160 return 0; 159 161 } 160 162 163 163 + char *object_property_help(const char *name, const char *type, 164 164 + QObject *defval, const char *description) 165 165 + { 166 166 + GString *str = g_string_new(NULL); 167 167 + 168 168 + g_string_append_printf(str, " %s=<%s>", name, type); 169 169 + if (description || defval) { 170 170 + if (str->len < 24) { 171 171 + g_string_append_printf(str, "%*s", 24 - (int)str->len, ""); 172 172 + } 173 173 + g_string_append(str, " - "); 174 174 + } 175 175 + if (description) { 176 176 + g_string_append(str, description); 177 177 + } 178 178 + if (defval) { 179 179 + g_autofree char *def_json = qstring_free(qobject_to_json(defval), TRUE); 180 180 + g_string_append_printf(str, " (default: %s)", def_json); 181 181 + } 182 182 + 183 183 + return g_string_free(str, false); 184 184 + } 185 185 + 161 186 bool user_creatable_print_help(const char *type, QemuOpts *opts) 162 187 { 163 188 ObjectClass *klass; ··· 184 209 185 210 object_class_property_iter_init(&iter, klass); 186 211 while ((prop = object_property_iter_next(&iter))) { 187 187 - GString *str; 188 188 - 189 212 if (!prop->set) { 190 213 continue; 191 214 } 192 215 193 193 - str = g_string_new(NULL); 194 194 - g_string_append_printf(str, " %s=<%s>", prop->name, prop->type); 195 195 - if (prop->description) { 196 196 - if (str->len < 24) { 197 197 - g_string_append_printf(str, "%*s", 24 - (int)str->len, ""); 198 198 - } 199 199 - g_string_append_printf(str, " - %s", prop->description); 200 200 - } 201 201 - g_ptr_array_add(array, g_string_free(str, false)); 216 216 + g_ptr_array_add(array, 217 217 + object_property_help(prop->name, prop->type, 218 218 + prop->defval, prop->description)); 202 219 } 203 220 g_ptr_array_sort(array, (GCompareFunc)qemu_pstrcmp0); 204 221 if (array->len > 0) {

+7 -47

qom/qom-qmp-cmds.c

··· 121 121 return ret; 122 122 } 123 123 124 124 - /* Return a DevicePropertyInfo for a qdev property. 125 125 - * 126 126 - * If a qdev property with the given name does not exist, use the given default 127 127 - * type. If the qdev property info should not be shown, return NULL. 128 128 - * 129 129 - * The caller must free the return value. 130 130 - */ 131 131 - static ObjectPropertyInfo *make_device_property_info(ObjectClass *klass, 132 132 - const char *name, 133 133 - const char *default_type, 134 134 - const char *description) 135 135 - { 136 136 - ObjectPropertyInfo *info; 137 137 - Property *prop; 138 138 - 139 139 - do { 140 140 - for (prop = DEVICE_CLASS(klass)->props; prop && prop->name; prop++) { 141 141 - if (strcmp(name, prop->name) != 0) { 142 142 - continue; 143 143 - } 144 144 - 145 145 - info = g_malloc0(sizeof(*info)); 146 146 - info->name = g_strdup(prop->name); 147 147 - info->type = default_type ? g_strdup(default_type) 148 148 - : g_strdup(prop->info->name); 149 149 - info->has_description = !!prop->info->description; 150 150 - info->description = g_strdup(prop->info->description); 151 151 - return info; 152 152 - } 153 153 - klass = object_class_get_parent(klass); 154 154 - } while (klass != object_class_by_name(TYPE_DEVICE)); 155 155 - 156 156 - /* Not a qdev property, use the default type */ 157 157 - info = g_malloc0(sizeof(*info)); 158 158 - info->name = g_strdup(name); 159 159 - info->type = g_strdup(default_type); 160 160 - info->has_description = !!description; 161 161 - info->description = g_strdup(description); 162 162 - 163 163 - return info; 164 164 - } 165 165 - 166 124 ObjectPropertyInfoList *qmp_device_list_properties(const char *typename, 167 125 Error **errp) 168 126 { ··· 214 172 continue; 215 173 } 216 174 217 217 - info = make_device_property_info(klass, prop->name, prop->type, 218 218 - prop->description); 219 219 - if (!info) { 220 220 - continue; 221 221 - } 175 175 + info = g_new0(ObjectPropertyInfo, 1); 176 176 + info->name = g_strdup(prop->name); 177 177 + info->type = g_strdup(prop->type); 178 178 + info->has_description = !!prop->description; 179 179 + info->description = g_strdup(prop->description); 180 180 + info->default_value = qobject_ref(prop->defval); 181 181 + info->has_default_value = !!info->default_value; 222 182 223 183 entry = g_malloc0(sizeof(*entry)); 224 184 entry->value = info;

+2 -2

rules.mak

··· 76 76 # must link with the C++ compiler, not the plain C compiler. 77 77 LINKPROG = $(or $(CXX),$(CC)) 78 78 79 79 - LINK = $(call quiet-command, $(LINKPROG) $(QEMU_LDFLAGS) $(QEMU_CFLAGS) $(CFLAGS) $(LDFLAGS) -o $@ \ 79 79 + LINK = $(call quiet-command, $(LINKPROG) $(CFLAGS) $(QEMU_LDFLAGS) -o $@ \ 80 80 $(call process-archive-undefs, $1) \ 81 81 $(version-obj-y) $(call extract-libs,$1) $(LIBS),"LINK","$(TARGET_DIR)$@") 82 82 ··· 105 105 106 106 DSO_OBJ_CFLAGS := -fPIC -DBUILD_DSO 107 107 module-common.o: CFLAGS += $(DSO_OBJ_CFLAGS) 108 108 - %$(DSOSUF): LDFLAGS += $(LDFLAGS_SHARED) 108 108 + %$(DSOSUF): QEMU_LDFLAGS += $(LDFLAGS_SHARED) 109 109 %$(DSOSUF): %.mo 110 110 $(call LINK,$^) 111 111 @# Copy to build root so modules can be loaded when program started without install

+14 -27

target/arm/cpu.c

··· 1104 1104 1105 1105 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1106 1106 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1107 1107 - qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 1108 1108 - &error_abort); 1107 1107 + qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1109 1108 } 1110 1109 1111 1110 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1112 1112 - qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 1113 1113 - &error_abort); 1111 1111 + qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1114 1112 } 1115 1113 1116 1114 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1117 1117 - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 1118 1118 - &error_abort); 1115 1115 + qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1119 1116 } 1120 1117 1121 1118 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1122 1119 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1123 1120 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1124 1121 */ 1125 1125 - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 1126 1126 - &error_abort); 1122 1122 + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1127 1123 1128 1124 #ifndef CONFIG_USER_ONLY 1129 1125 object_property_add_link(obj, "secure-memory", ··· 1136 1132 } 1137 1133 1138 1134 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1139 1139 - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 1140 1140 - &error_abort); 1135 1135 + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1141 1136 } 1142 1137 1143 1138 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { ··· 1154 1149 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1155 1150 cpu->has_vfp = true; 1156 1151 if (!kvm_enabled()) { 1157 1157 - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, 1158 1158 - &error_abort); 1152 1152 + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1159 1153 } 1160 1154 } 1161 1155 1162 1156 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1163 1157 cpu->has_neon = true; 1164 1158 if (!kvm_enabled()) { 1165 1165 - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, 1166 1166 - &error_abort); 1159 1159 + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1167 1160 } 1168 1161 } 1169 1162 1170 1163 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1171 1164 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1172 1172 - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, 1173 1173 - &error_abort); 1165 1165 + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1174 1166 } 1175 1167 1176 1168 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1177 1177 - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 1178 1178 - &error_abort); 1169 1169 + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1179 1170 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1180 1171 qdev_property_add_static(DEVICE(obj), 1181 1181 - &arm_cpu_pmsav7_dregion_property, 1182 1182 - &error_abort); 1172 1172 + &arm_cpu_pmsav7_dregion_property); 1183 1173 } 1184 1174 } 1185 1175 ··· 1198 1188 NULL, NULL, &error_abort); 1199 1189 } 1200 1190 1201 1201 - qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 1202 1202 - &error_abort); 1191 1191 + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1203 1192 1204 1193 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1205 1205 - qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property, 1206 1206 - &error_abort); 1194 1194 + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1207 1195 } 1208 1196 } 1209 1197 ··· 2706 2694 2707 2695 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2708 2696 &acc->parent_realize); 2709 2709 - dc->props = arm_cpu_properties; 2710 2697 2711 2711 - acc->parent_reset = cc->reset; 2712 2712 - cc->reset = arm_cpu_reset; 2698 2698 + device_class_set_props(dc, arm_cpu_properties); 2699 2699 + cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); 2713 2700 2714 2701 cc->class_by_name = arm_cpu_class_by_name; 2715 2702 cc->has_work = arm_cpu_has_work;

+1 -3

target/arm/kvm.c

··· 181 181 182 182 bool kvm_arm_pmu_supported(CPUState *cpu) 183 183 { 184 184 - KVMState *s = KVM_STATE(current_machine->accelerator); 185 185 - 186 186 - return kvm_check_extension(s, KVM_CAP_ARM_PMU_V3); 184 184 + return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3); 187 185 } 188 186 189 187 int kvm_arm_get_max_vm_ipa_size(MachineState *ms)

+2 -3

target/arm/kvm64.c

··· 26 26 #include "sysemu/kvm.h" 27 27 #include "sysemu/kvm_int.h" 28 28 #include "kvm_arm.h" 29 29 - #include "hw/boards.h" 30 29 #include "internals.h" 31 30 32 31 static bool have_guest_debug; ··· 613 612 614 613 bool kvm_arm_aarch32_supported(CPUState *cpu) 615 614 { 616 616 - KVMState *s = KVM_STATE(current_machine->accelerator); 615 615 + KVMState *s = KVM_STATE(current_accel()); 617 616 618 617 return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT); 619 618 } 620 619 621 620 bool kvm_arm_sve_supported(CPUState *cpu) 622 621 { 623 623 - KVMState *s = KVM_STATE(current_machine->accelerator); 622 622 + KVMState *s = KVM_STATE(current_accel()); 624 623 625 624 return kvm_check_extension(s, KVM_CAP_ARM_SVE); 626 625 }

+1 -2

target/cris/cpu.c

··· 264 264 device_class_set_parent_realize(dc, cris_cpu_realizefn, 265 265 &ccc->parent_realize); 266 266 267 267 - ccc->parent_reset = cc->reset; 268 268 - cc->reset = cris_cpu_reset; 267 267 + cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); 269 268 270 269 cc->class_by_name = cris_cpu_class_by_name; 271 270 cc->has_work = cris_cpu_has_work;

+21 -4

target/i386/cpu.c

··· 2905 2905 .props = (PropValue[]) { 2906 2906 { "hle", "off" }, 2907 2907 { "rtm", "off" }, 2908 2908 + { "model-id", 2909 2909 + "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2908 2910 { /* end of list */ } 2909 2911 } 2910 2912 }, ··· 3028 3030 .props = (PropValue[]) { 3029 3031 { "hle", "off" }, 3030 3032 { "rtm", "off" }, 3033 3033 + { "model-id", 3034 3034 + "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3031 3035 { /* end of list */ } 3032 3036 } 3033 3037 }, ··· 4144 4148 xcc->model_description = 4145 4149 "Enables all features supported by the accelerator in the current host"; 4146 4150 4147 4147 - dc->props = max_x86_cpu_properties; 4151 4151 + device_class_set_props(dc, max_x86_cpu_properties); 4148 4152 } 4149 4153 4150 4154 static void max_x86_cpu_initfn(Object *obj) ··· 6416 6420 &cpu->mwait.ecx, &cpu->mwait.edx); 6417 6421 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 6418 6422 } 6423 6423 + if (kvm_enabled() && cpu->ucode_rev == 0) { 6424 6424 + cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state, 6425 6425 + MSR_IA32_UCODE_REV); 6426 6426 + } 6427 6427 + } 6428 6428 + 6429 6429 + if (cpu->ucode_rev == 0) { 6430 6430 + /* The default is the same as KVM's. */ 6431 6431 + if (IS_AMD_CPU(env)) { 6432 6432 + cpu->ucode_rev = 0x01000065; 6433 6433 + } else { 6434 6434 + cpu->ucode_rev = 0x100000000ULL; 6435 6435 + } 6419 6436 } 6420 6437 6421 6438 /* mwait extended info: needed for Core compatibility */ ··· 7100 7117 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7101 7118 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7102 7119 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7120 7120 + DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7103 7121 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7104 7122 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), 7105 7123 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), ··· 7147 7165 &xcc->parent_realize); 7148 7166 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7149 7167 &xcc->parent_unrealize); 7150 7150 - dc->props = x86_cpu_properties; 7168 7168 + device_class_set_props(dc, x86_cpu_properties); 7151 7169 7152 7152 - xcc->parent_reset = cc->reset; 7153 7153 - cc->reset = x86_cpu_reset; 7170 7170 + cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); 7154 7171 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7155 7172 7156 7173 cc->class_by_name = x86_cpu_class_by_name;

+3

target/i386/cpu.h

··· 348 348 #define MSR_IA32_SPEC_CTRL 0x48 349 349 #define MSR_VIRT_SSBD 0xc001011f 350 350 #define MSR_IA32_PRED_CMD 0x49 351 351 + #define MSR_IA32_UCODE_REV 0x8b 351 352 #define MSR_IA32_CORE_CAPABILITY 0xcf 352 353 353 354 #define MSR_IA32_ARCH_CAPABILITIES 0x10a ··· 1626 1627 1627 1628 CPUNegativeOffsetState neg; 1628 1629 CPUX86State env; 1630 1630 + 1631 1631 + uint64_t ucode_rev; 1629 1632 1630 1633 uint32_t hyperv_spinlock_attempts; 1631 1634 char *hyperv_vendor_id;

+1 -3

target/i386/hvf/x86_emu.c

··· 664 664 RIP(env) += decode->len; 665 665 } 666 666 667 667 - #define MSR_IA32_UCODE_REV 0x00000017 668 668 - 669 667 void simulate_rdmsr(struct CPUState *cpu) 670 668 { 671 669 X86CPU *x86_cpu = X86_CPU(cpu); ··· 681 679 val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); 682 680 break; 683 681 case MSR_IA32_UCODE_REV: 684 684 - val = (0x100000000ULL << 32) | 0x100000000ULL; 682 682 + val = x86_cpu->ucode_rev; 685 683 break; 686 684 case MSR_EFER: 687 685 val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);

+54 -34

target/i386/kvm.c

··· 67 67 * 255 kvm_msr_entry structs */ 68 68 #define MSR_BUF_SIZE 4096 69 69 70 70 + static void kvm_init_msrs(X86CPU *cpu); 71 71 + 70 72 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 71 73 KVM_CAP_INFO(SET_TSS_ADDR), 72 74 KVM_CAP_INFO(EXT_CPUID), ··· 147 149 148 150 static bool kvm_x2apic_api_set_flags(uint64_t flags) 149 151 { 150 150 - KVMState *s = KVM_STATE(current_machine->accelerator); 152 152 + KVMState *s = KVM_STATE(current_accel()); 151 153 152 154 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags); 153 155 } ··· 1842 1844 has_msr_tsc_aux = false; 1843 1845 } 1844 1846 1847 1847 + kvm_init_msrs(cpu); 1848 1848 + 1845 1849 r = hyperv_init_vcpu(cpu); 1846 1850 if (r) { 1847 1851 goto fail; ··· 2660 2664 VMCS12_MAX_FIELD_INDEX << 1); 2661 2665 } 2662 2666 2667 2667 + static int kvm_buf_set_msrs(X86CPU *cpu) 2668 2668 + { 2669 2669 + int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 2670 2670 + if (ret < 0) { 2671 2671 + return ret; 2672 2672 + } 2673 2673 + 2674 2674 + if (ret < cpu->kvm_msr_buf->nmsrs) { 2675 2675 + struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 2676 2676 + error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, 2677 2677 + (uint32_t)e->index, (uint64_t)e->data); 2678 2678 + } 2679 2679 + 2680 2680 + assert(ret == cpu->kvm_msr_buf->nmsrs); 2681 2681 + return 0; 2682 2682 + } 2683 2683 + 2684 2684 + static void kvm_init_msrs(X86CPU *cpu) 2685 2685 + { 2686 2686 + CPUX86State *env = &cpu->env; 2687 2687 + 2688 2688 + kvm_msr_buf_reset(cpu); 2689 2689 + if (has_msr_arch_capabs) { 2690 2690 + kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, 2691 2691 + env->features[FEAT_ARCH_CAPABILITIES]); 2692 2692 + } 2693 2693 + 2694 2694 + if (has_msr_core_capabs) { 2695 2695 + kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, 2696 2696 + env->features[FEAT_CORE_CAPABILITY]); 2697 2697 + } 2698 2698 + 2699 2699 + if (kvm_arch_get_supported_msr_feature(kvm_state, 2700 2700 + MSR_IA32_UCODE_REV)) { 2701 2701 + kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); 2702 2702 + } 2703 2703 + 2704 2704 + /* 2705 2705 + * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but 2706 2706 + * all kernels with MSR features should have them. 2707 2707 + */ 2708 2708 + if (kvm_feature_msrs && cpu_has_vmx(env)) { 2709 2709 + kvm_msr_entry_add_vmx(cpu, env->features); 2710 2710 + } 2711 2711 + 2712 2712 + assert(kvm_buf_set_msrs(cpu) == 0); 2713 2713 + } 2714 2714 + 2663 2715 static int kvm_put_msrs(X86CPU *cpu, int level) 2664 2716 { 2665 2717 CPUX86State *env = &cpu->env; 2666 2718 int i; 2667 2667 - int ret; 2668 2719 2669 2720 kvm_msr_buf_reset(cpu); 2670 2721 ··· 2721 2772 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); 2722 2773 } 2723 2774 #endif 2724 2724 - 2725 2725 - /* If host supports feature MSR, write down. */ 2726 2726 - if (has_msr_arch_capabs) { 2727 2727 - kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, 2728 2728 - env->features[FEAT_ARCH_CAPABILITIES]); 2729 2729 - } 2730 2730 - 2731 2731 - if (has_msr_core_capabs) { 2732 2732 - kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, 2733 2733 - env->features[FEAT_CORE_CAPABILITY]); 2734 2734 - } 2735 2775 2736 2776 /* 2737 2777 * The following MSRs have side effects on the guest or are too heavy ··· 2910 2950 2911 2951 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see 2912 2952 * kvm_put_msr_feature_control. */ 2913 2913 - 2914 2914 - /* 2915 2915 - * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but 2916 2916 - * all kernels with MSR features should have them. 2917 2917 - */ 2918 2918 - if (kvm_feature_msrs && cpu_has_vmx(env)) { 2919 2919 - kvm_msr_entry_add_vmx(cpu, env->features); 2920 2920 - } 2921 2953 } 2922 2954 2923 2955 if (env->mcg_cap) { ··· 2933 2965 } 2934 2966 } 2935 2967 2936 2936 - ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); 2937 2937 - if (ret < 0) { 2938 2938 - return ret; 2939 2939 - } 2940 2940 - 2941 2941 - if (ret < cpu->kvm_msr_buf->nmsrs) { 2942 2942 - struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; 2943 2943 - error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, 2944 2944 - (uint32_t)e->index, (uint64_t)e->data); 2945 2945 - } 2946 2946 - 2947 2947 - assert(ret == cpu->kvm_msr_buf->nmsrs); 2948 2948 - return 0; 2968 2968 + return kvm_buf_set_msrs(cpu); 2949 2969 } 2950 2970 2951 2971

+1

target/i386/kvm_i386.h

··· 46 46 bool kvm_has_x2apic_api(void); 47 47 48 48 bool kvm_hv_vpindex_settable(void); 49 49 + 49 50 #endif

+4

target/i386/misc_helper.c

··· 229 229 #else 230 230 void helper_wrmsr(CPUX86State *env) 231 231 { 232 232 + X86CPU *x86_cpu = env_archcpu(env); 232 233 uint64_t val; 233 234 234 235 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); ··· 370 371 /* FIXME: Extend highest implemented bit of linear address. */ 371 372 env->msr_bndcfgs = val; 372 373 cpu_sync_bndcs_hflags(env); 374 374 + break; 375 375 + case MSR_IA32_UCODE_REV: 376 376 + val = x86_cpu->ucode_rev; 373 377 break; 374 378 default: 375 379 if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL

+1 -2

target/lm32/cpu.c

··· 218 218 219 219 device_class_set_parent_realize(dc, lm32_cpu_realizefn, 220 220 &lcc->parent_realize); 221 221 - lcc->parent_reset = cc->reset; 222 222 - cc->reset = lm32_cpu_reset; 221 221 + cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); 223 222 224 223 cc->class_by_name = lm32_cpu_class_by_name; 225 224 cc->has_work = lm32_cpu_has_work;

+1 -2

target/m68k/cpu.c

··· 273 273 274 274 device_class_set_parent_realize(dc, m68k_cpu_realizefn, 275 275 &mcc->parent_realize); 276 276 - mcc->parent_reset = cc->reset; 277 277 - cc->reset = m68k_cpu_reset; 276 276 + cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); 278 277 279 278 cc->class_by_name = m68k_cpu_class_by_name; 280 279 cc->has_work = m68k_cpu_has_work;

+2 -3

target/microblaze/cpu.c

··· 292 292 293 293 device_class_set_parent_realize(dc, mb_cpu_realizefn, 294 294 &mcc->parent_realize); 295 295 - mcc->parent_reset = cc->reset; 296 296 - cc->reset = mb_cpu_reset; 295 295 + cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); 297 296 298 297 cc->class_by_name = mb_cpu_class_by_name; 299 298 cc->has_work = mb_cpu_has_work; ··· 309 308 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; 310 309 #endif 311 310 dc->vmsd = &vmstate_mb_cpu; 312 312 - dc->props = mb_properties; 311 311 + device_class_set_props(dc, mb_properties); 313 312 cc->gdb_num_core_regs = 32 + 5; 314 313 315 314 cc->disas_set_info = mb_disas_set_info;

+1 -2

target/mips/cpu.c

··· 189 189 190 190 device_class_set_parent_realize(dc, mips_cpu_realizefn, 191 191 &mcc->parent_realize); 192 192 - mcc->parent_reset = cc->reset; 193 193 - cc->reset = mips_cpu_reset; 192 192 + cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); 194 193 195 194 cc->class_by_name = mips_cpu_class_by_name; 196 195 cc->has_work = mips_cpu_has_work;

+1 -2

target/moxie/cpu.c

··· 101 101 102 102 device_class_set_parent_realize(dc, moxie_cpu_realizefn, 103 103 &mcc->parent_realize); 104 104 - mcc->parent_reset = cc->reset; 105 105 - cc->reset = moxie_cpu_reset; 104 104 + cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); 106 105 107 106 cc->class_by_name = moxie_cpu_class_by_name; 108 107

+2 -3

target/nios2/cpu.c

··· 187 187 188 188 device_class_set_parent_realize(dc, nios2_cpu_realizefn, 189 189 &ncc->parent_realize); 190 190 - dc->props = nios2_properties; 191 191 - ncc->parent_reset = cc->reset; 192 192 - cc->reset = nios2_cpu_reset; 190 190 + device_class_set_props(dc, nios2_properties); 191 191 + cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); 193 192 194 193 cc->class_by_name = nios2_cpu_class_by_name; 195 194 cc->has_work = nios2_cpu_has_work;

+1 -2

target/openrisc/cpu.c

··· 150 150 151 151 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 152 152 &occ->parent_realize); 153 153 - occ->parent_reset = cc->reset; 154 154 - cc->reset = openrisc_cpu_reset; 153 153 + cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); 155 154 156 155 cc->class_by_name = openrisc_cpu_class_by_name; 157 156 cc->has_work = openrisc_cpu_has_work;

+2 -2

target/ppc/kvm.c

··· 258 258 259 259 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 260 260 { 261 261 - KVMState *s = KVM_STATE(current_machine->accelerator); 261 261 + KVMState *s = KVM_STATE(current_accel()); 262 262 struct ppc_radix_page_info *radix_page_info; 263 263 struct kvm_ppc_rmmu_info rmmu_info; 264 264 int i; ··· 2907 2907 return; 2908 2908 } 2909 2909 2910 2910 - rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF); 2910 2910 + rc = kvm_vm_ioctl(KVM_STATE(current_accel()), KVM_PPC_SVM_OFF); 2911 2911 if (rc && rc != -ENOTTY) { 2912 2912 error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed"); 2913 2913 }

+6 -7

target/ppc/translate_init.inc.c

··· 8599 8599 8600 8600 dc->fw_name = "PowerPC,POWER7"; 8601 8601 dc->desc = "POWER7"; 8602 8602 - dc->props = powerpc_servercpu_properties; 8602 8602 + device_class_set_props(dc, powerpc_servercpu_properties); 8603 8603 pcc->pvr_match = ppc_pvr_match_power7; 8604 8604 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 8605 8605 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; ··· 8764 8764 8765 8765 dc->fw_name = "PowerPC,POWER8"; 8766 8766 dc->desc = "POWER8"; 8767 8767 - dc->props = powerpc_servercpu_properties; 8767 8767 + device_class_set_props(dc, powerpc_servercpu_properties); 8768 8768 pcc->pvr_match = ppc_pvr_match_power8; 8769 8769 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8770 8770 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; ··· 8976 8976 8977 8977 dc->fw_name = "PowerPC,POWER9"; 8978 8978 dc->desc = "POWER9"; 8979 8979 - dc->props = powerpc_servercpu_properties; 8979 8979 + device_class_set_props(dc, powerpc_servercpu_properties); 8980 8980 pcc->pvr_match = ppc_pvr_match_power9; 8981 8981 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 8982 8982 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | ··· 9186 9186 9187 9187 dc->fw_name = "PowerPC,POWER10"; 9188 9188 dc->desc = "POWER10"; 9189 9189 - dc->props = powerpc_servercpu_properties; 9189 9189 + device_class_set_props(dc, powerpc_servercpu_properties); 9190 9190 pcc->pvr_match = ppc_pvr_match_power10; 9191 9191 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 9192 9192 PCR_COMPAT_3_00; ··· 10871 10871 &pcc->parent_unrealize); 10872 10872 pcc->pvr_match = ppc_pvr_match_default; 10873 10873 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; 10874 10874 - dc->props = ppc_cpu_properties; 10874 10874 + device_class_set_props(dc, ppc_cpu_properties); 10875 10875 10876 10876 - pcc->parent_reset = cc->reset; 10877 10877 - cc->reset = ppc_cpu_reset; 10876 10876 + cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); 10878 10877 10879 10878 cc->class_by_name = ppc_cpu_class_by_name; 10880 10879 pcc->parent_parse_features = cc->parse_features;

+2 -3

target/riscv/cpu.c

··· 462 462 device_class_set_parent_realize(dc, riscv_cpu_realize, 463 463 &mcc->parent_realize); 464 464 465 465 - mcc->parent_reset = cc->reset; 466 466 - cc->reset = riscv_cpu_reset; 465 465 + cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); 467 466 468 467 cc->class_by_name = riscv_cpu_class_by_name; 469 468 cc->has_work = riscv_cpu_has_work; ··· 493 492 #endif 494 493 /* For now, mark unmigratable: */ 495 494 cc->vmsd = &vmstate_riscv_cpu; 496 496 - dc->props = riscv_cpu_properties; 495 495 + device_class_set_props(dc, riscv_cpu_properties); 497 496 } 498 497 499 498 char *riscv_isa_string(RISCVCPU *cpu)

+2 -3

target/s390x/cpu.c

··· 453 453 454 454 device_class_set_parent_realize(dc, s390_cpu_realizefn, 455 455 &scc->parent_realize); 456 456 - dc->props = s390x_cpu_properties; 456 456 + device_class_set_props(dc, s390x_cpu_properties); 457 457 dc->user_creatable = true; 458 458 459 459 - scc->parent_reset = cc->reset; 459 459 + cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset); 460 460 #if !defined(CONFIG_USER_ONLY) 461 461 scc->load_normal = s390_cpu_load_normal; 462 462 #endif 463 463 scc->reset = s390_cpu_reset; 464 464 - cc->reset = s390_cpu_reset_full; 465 464 cc->class_by_name = s390_cpu_class_by_name, 466 465 cc->has_work = s390_cpu_has_work; 467 466 #ifdef CONFIG_TCG

+1 -2

target/sh4/cpu.c

··· 214 214 device_class_set_parent_realize(dc, superh_cpu_realizefn, 215 215 &scc->parent_realize); 216 216 217 217 - scc->parent_reset = cc->reset; 218 218 - cc->reset = superh_cpu_reset; 217 217 + cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); 219 218 220 219 cc->class_by_name = superh_cpu_class_by_name; 221 220 cc->has_work = superh_cpu_has_work;

+2 -3

target/sparc/cpu.c

··· 857 857 858 858 device_class_set_parent_realize(dc, sparc_cpu_realizefn, 859 859 &scc->parent_realize); 860 860 - dc->props = sparc_cpu_properties; 860 860 + device_class_set_props(dc, sparc_cpu_properties); 861 861 862 862 - scc->parent_reset = cc->reset; 863 863 - cc->reset = sparc_cpu_reset; 862 862 + cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); 864 863 865 864 cc->class_by_name = sparc_cpu_class_by_name; 866 865 cc->parse_features = sparc_cpu_parse_features;

+1 -2

target/tilegx/cpu.c

··· 142 142 device_class_set_parent_realize(dc, tilegx_cpu_realizefn, 143 143 &tcc->parent_realize); 144 144 145 145 - tcc->parent_reset = cc->reset; 146 146 - cc->reset = tilegx_cpu_reset; 145 145 + cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); 147 146 148 147 cc->class_by_name = tilegx_cpu_class_by_name; 149 148 cc->has_work = tilegx_cpu_has_work;

+1 -2

target/tricore/cpu.c

··· 153 153 device_class_set_parent_realize(dc, tricore_cpu_realizefn, 154 154 &mcc->parent_realize); 155 155 156 156 - mcc->parent_reset = cc->reset; 157 157 - cc->reset = tricore_cpu_reset; 156 156 + cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); 158 157 cc->class_by_name = tricore_cpu_class_by_name; 159 158 cc->has_work = tricore_cpu_has_work; 160 159

+1 -2

target/xtensa/cpu.c

··· 184 184 device_class_set_parent_realize(dc, xtensa_cpu_realizefn, 185 185 &xcc->parent_realize); 186 186 187 187 - xcc->parent_reset = cc->reset; 188 188 - cc->reset = xtensa_cpu_reset; 187 187 + cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); 189 188 190 189 cc->class_by_name = xtensa_cpu_class_by_name; 191 190 cc->has_work = xtensa_cpu_has_work;

+1 -1

tests/test-qdev-global-props.c

··· 55 55 DeviceClass *dc = DEVICE_CLASS(oc); 56 56 57 57 dc->realize = NULL; 58 58 - dc->props = static_props; 58 58 + device_class_set_props(dc, static_props); 59 59 } 60 60 61 61 static const TypeInfo static_prop_type = {

+13 -1

vl.c

··· 1468 1468 } 1469 1469 } 1470 1470 1471 1471 + void qemu_system_guest_crashloaded(GuestPanicInformation *info) 1472 1472 + { 1473 1473 + qemu_log_mask(LOG_GUEST_ERROR, "Guest crash loaded"); 1474 1474 + 1475 1475 + qapi_event_send_guest_crashloaded(GUEST_PANIC_ACTION_RUN, 1476 1476 + !!info, info); 1477 1477 + 1478 1478 + if (info) { 1479 1479 + qapi_free_GuestPanicInformation(info); 1480 1480 + } 1481 1481 + } 1482 1482 + 1471 1483 void qemu_system_reset_request(ShutdownCause reason) 1472 1484 { 1473 1485 if (no_reboot && reason != SHUTDOWN_CAUSE_SUBSYSTEM_RESET) { ··· 2817 2829 } 2818 2830 2819 2831 if (init_failed) { 2820 2820 - AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator); 2832 2832 + AccelClass *ac = ACCEL_GET_CLASS(current_accel()); 2821 2833 error_report("falling back to %s", ac->name); 2822 2834 } 2823 2835