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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' into staging

RISC-V Patches for the 5.0 Soft Freeze, Part 1

This patch set contains a handful of collected fixes that I'd like to target
for the 5.0 soft freeze (I know that's a long way away, I just don't know what
else to call these):

* A fix for a memory leak initializing the sifive_u board.
* Fixes to privilege mode emulation related to interrupts and fstatus.

Notably absent is the H extension implementation. That's pretty much reviewed,
but not quite ready to go yet and I didn't want to hold back these important
fixes. This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
and passes "make check".

# gpg: Signature made Tue 21 Jan 2020 22:55:28 GMT
# gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg: issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
# Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf1:
target/riscv: update mstatus.SD when FS is set dirty
target/riscv: fsd/fsw doesn't dirty FP state
target/riscv: Fix tb->flags FS status
riscv: Set xPIE to 1 after xRET
riscv/sifive_u: fix a memory leak in soc_realize()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Peter Maydell ba2ed84f a43efa34

+6 -11
+1
hw/riscv/sifive_u.c
··· 542 542 SIFIVE_U_PLIC_CONTEXT_BASE, 543 543 SIFIVE_U_PLIC_CONTEXT_STRIDE, 544 544 memmap[SIFIVE_U_PLIC].size); 545 + g_free(plic_hart_config); 545 546 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 546 547 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 547 548 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+1 -4
target/riscv/cpu.h
··· 293 293 #ifdef CONFIG_USER_ONLY 294 294 *flags = TB_FLAGS_MSTATUS_FS; 295 295 #else 296 - *flags = cpu_mmu_index(env, 0); 297 - if (riscv_cpu_fp_enabled(env)) { 298 - *flags |= TB_FLAGS_MSTATUS_FS; 299 - } 296 + *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); 300 297 #endif 301 298 } 302 299
+1 -2
target/riscv/csr.c
··· 341 341 342 342 mstatus = (mstatus & ~mask) | (val & mask); 343 343 344 - dirty = (riscv_cpu_fp_enabled(env) && 345 - ((mstatus & MSTATUS_FS) == MSTATUS_FS)) | 344 + dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 346 345 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 347 346 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 348 347 env->mstatus = mstatus;
-1
target/riscv/insn_trans/trans_rvd.inc.c
··· 43 43 44 44 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); 45 45 46 - mark_fs_dirty(ctx); 47 46 tcg_temp_free(t0); 48 47 return true; 49 48 }
-1
target/riscv/insn_trans/trans_rvf.inc.c
··· 52 52 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); 53 53 54 54 tcg_temp_free(t0); 55 - mark_fs_dirty(ctx); 56 55 return true; 57 56 } 58 57
+2 -2
target/riscv/op_helper.c
··· 93 93 env->priv_ver >= PRIV_VERSION_1_10_0 ? 94 94 MSTATUS_SIE : MSTATUS_UIE << prev_priv, 95 95 get_field(mstatus, MSTATUS_SPIE)); 96 - mstatus = set_field(mstatus, MSTATUS_SPIE, 0); 96 + mstatus = set_field(mstatus, MSTATUS_SPIE, 1); 97 97 mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); 98 98 riscv_cpu_set_mode(env, prev_priv); 99 99 env->mstatus = mstatus; ··· 118 118 env->priv_ver >= PRIV_VERSION_1_10_0 ? 119 119 MSTATUS_MIE : MSTATUS_UIE << prev_priv, 120 120 get_field(mstatus, MSTATUS_MPIE)); 121 - mstatus = set_field(mstatus, MSTATUS_MPIE, 0); 121 + mstatus = set_field(mstatus, MSTATUS_MPIE, 1); 122 122 mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); 123 123 riscv_cpu_set_mode(env, prev_priv); 124 124 env->mstatus = mstatus;
+1 -1
target/riscv/translate.c
··· 394 394 395 395 tmp = tcg_temp_new(); 396 396 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 397 - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 397 + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); 398 398 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 399 399 tcg_temp_free(tmp); 400 400 }