jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/microblaze: Add the div-zero-exception property
Add the div-zero-exception property to control if the core
traps divizions by zero.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+8
-2
+4
target/microblaze/cpu.c
+4
target/microblaze/cpu.c
···
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207
PVR2_DOPB_BUS_EXC_MASK : 0) |
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(cpu->cfg.iopb_bus_exception ?
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PVR2_IOPB_BUS_EXC_MASK : 0) |
210
+
(cpu->cfg.div_zero_exception ?
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+
PVR2_DIV_ZERO_EXC_MASK : 0) |
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(cpu->cfg.illegal_opcode_exception ?
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PVR2_ILL_OPCODE_EXC_MASK : 0) |
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(cpu->cfg.opcode_0_illegal ?
···
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282
cfg.iopb_bus_exception, false),
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DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
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cfg.illegal_opcode_exception, false),
285
+
DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
286
+
cfg.div_zero_exception, false),
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DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
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cfg.opcode_0_illegal, false),
285
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DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
+1
target/microblaze/cpu.h
+1
target/microblaze/cpu.h
+3
-2
target/microblaze/op_helper.c
+3
-2
target/microblaze/op_helper.c
···
132
132
133
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static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
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{
135
+
MicroBlazeCPU *cpu = env_archcpu(env);
136
+
135
137
if (b == 0) {
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env->sregs[SR_MSR] |= MSR_DZ;
137
139
138
-
if ((env->sregs[SR_MSR] & MSR_EE)
139
-
&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
140
+
if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
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env->sregs[SR_ESR] = ESR_EC_DIVZERO;
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helper_raise_exception(env, EXCP_HW_EXCP);
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}