jcs.org / qemu
qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Richard Henderson 4e027a71 a456394a

+8 -51
-2
target/arm/helper.h
··· 352 352 DEF_HELPER_2(neon_ceq_u16, i32, i32, i32) 353 353 DEF_HELPER_2(neon_ceq_u32, i32, i32, i32) 354 354 355 - DEF_HELPER_1(neon_abs_s8, i32, i32) 356 - DEF_HELPER_1(neon_abs_s16, i32, i32) 357 355 DEF_HELPER_1(neon_clz_u8, i32, i32) 358 356 DEF_HELPER_1(neon_clz_u16, i32, i32) 359 357 DEF_HELPER_1(neon_cls_s8, i32, i32)
-5
target/arm/neon_helper.c
··· 1228 1228 NEON_VOP(ceq_u32, neon_u32, 1) 1229 1229 #undef NEON_FN 1230 1230 1231 - #define NEON_FN(dest, src, dummy) dest = (src < 0) ? -src : src 1232 - NEON_VOP1(abs_s8, neon_s8, 4) 1233 - NEON_VOP1(abs_s16, neon_s16, 2) 1234 - #undef NEON_FN 1235 - 1236 1231 /* Count Leading Sign/Zero Bits. */ 1237 1232 static inline int do_clz8(uint8_t x) 1238 1233 {
+5 -36
target/arm/translate-a64.c
··· 9468 9468 if (u) { 9469 9469 tcg_gen_neg_i64(tcg_rd, tcg_rn); 9470 9470 } else { 9471 - TCGv_i64 tcg_zero = tcg_const_i64(0); 9472 - tcg_gen_neg_i64(tcg_rd, tcg_rn); 9473 - tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, 9474 - tcg_rn, tcg_rd); 9475 - tcg_temp_free_i64(tcg_zero); 9471 + tcg_gen_abs_i64(tcg_rd, tcg_rn); 9476 9472 } 9477 9473 break; 9478 9474 case 0x2f: /* FABS */ ··· 12366 12362 } 12367 12363 break; 12368 12364 case 0xb: 12369 - if (u) { /* NEG */ 12365 + if (u) { /* ABS, NEG */ 12370 12366 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); 12371 - return; 12367 + } else { 12368 + gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); 12372 12369 } 12373 - break; 12370 + return; 12374 12371 } 12375 12372 12376 12373 if (size == 3) { ··· 12436 12433 gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); 12437 12434 } else { 12438 12435 gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); 12439 - } 12440 - break; 12441 - case 0xb: /* ABS, NEG */ 12442 - if (u) { 12443 - tcg_gen_neg_i32(tcg_res, tcg_op); 12444 - } else { 12445 - TCGv_i32 tcg_zero = tcg_const_i32(0); 12446 - tcg_gen_neg_i32(tcg_res, tcg_op); 12447 - tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, 12448 - tcg_zero, tcg_op, tcg_res); 12449 - tcg_temp_free_i32(tcg_zero); 12450 12436 } 12451 12437 break; 12452 12438 case 0x2f: /* FABS */ ··· 12561 12547 tcg_temp_free_i32(tcg_zero); 12562 12548 break; 12563 12549 } 12564 - case 0xb: /* ABS, NEG */ 12565 - if (u) { 12566 - TCGv_i32 tcg_zero = tcg_const_i32(0); 12567 - if (size) { 12568 - gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op); 12569 - } else { 12570 - gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op); 12571 - } 12572 - tcg_temp_free_i32(tcg_zero); 12573 - } else { 12574 - if (size) { 12575 - gen_helper_neon_abs_s16(tcg_res, tcg_op); 12576 - } else { 12577 - gen_helper_neon_abs_s8(tcg_res, tcg_op); 12578 - } 12579 - } 12580 - break; 12581 12550 case 0x4: /* CLS, CLZ */ 12582 12551 if (u) { 12583 12552 if (size == 0) {
+3 -8
target/arm/translate.c
··· 8120 8120 case NEON_2RM_VNEG: 8121 8121 tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size); 8122 8122 break; 8123 + case NEON_2RM_VABS: 8124 + tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size); 8125 + break; 8123 8126 8124 8127 default: 8125 8128 elementwise: ··· 8224 8227 default: abort(); 8225 8228 } 8226 8229 tcg_temp_free_i32(tmp2); 8227 - break; 8228 - case NEON_2RM_VABS: 8229 - switch(size) { 8230 - case 0: gen_helper_neon_abs_s8(tmp, tmp); break; 8231 - case 1: gen_helper_neon_abs_s16(tmp, tmp); break; 8232 - case 2: tcg_gen_abs_i32(tmp, tmp); break; 8233 - default: abort(); 8234 - } 8235 8230 break; 8236 8231 case NEON_2RM_VCGT0_F: 8237 8232 {