jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging
# gpg: Signature made Tue 20 Mar 2018 09:07:55 GMT
# gpg: using RSA key F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg: aka "Laurent Vivier <laurent@vivier.eu>"
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-2.12-pull-request:
target/m68k: add a mechanism to automatically free TCGv
target/m68k: add DisasContext parameter to gen_extend()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+66
-36
+66
-36
target/m68k/translate.c
+66
-36
target/m68k/translate.c
···
123
123
int done_mac;
124
124
int writeback_mask;
125
125
TCGv writeback[8];
126
+
#define MAX_TO_RELEASE 8
127
+
int release_count;
128
+
TCGv release[MAX_TO_RELEASE];
126
129
} DisasContext;
130
+
131
+
static void init_release_array(DisasContext *s)
132
+
{
133
+
#ifdef CONFIG_DEBUG_TCG
134
+
memset(s->release, 0, sizeof(s->release));
135
+
#endif
136
+
s->release_count = 0;
137
+
}
138
+
139
+
static void do_release(DisasContext *s)
140
+
{
141
+
int i;
142
+
for (i = 0; i < s->release_count; i++) {
143
+
tcg_temp_free(s->release[i]);
144
+
}
145
+
init_release_array(s);
146
+
}
147
+
148
+
static TCGv mark_to_release(DisasContext *s, TCGv tmp)
149
+
{
150
+
g_assert(s->release_count < MAX_TO_RELEASE);
151
+
return s->release[s->release_count++] = tmp;
152
+
}
127
153
128
154
static TCGv get_areg(DisasContext *s, unsigned regno)
129
155
{
···
347
373
gen_store(s, opsize, addr, val, index);
348
374
return store_dummy;
349
375
} else {
350
-
return gen_load(s, opsize, addr, what == EA_LOADS, index);
376
+
return mark_to_release(s, gen_load(s, opsize, addr,
377
+
what == EA_LOADS, index));
351
378
}
352
379
}
353
380
···
439
466
} else {
440
467
bd = 0;
441
468
}
442
-
tmp = tcg_temp_new();
469
+
tmp = mark_to_release(s, tcg_temp_new());
443
470
if ((ext & 0x44) == 0) {
444
471
/* pre-index */
445
472
add = gen_addr_index(s, ext, tmp);
···
449
476
if ((ext & 0x80) == 0) {
450
477
/* base not suppressed */
451
478
if (IS_NULL_QREG(base)) {
452
-
base = tcg_const_i32(offset + bd);
479
+
base = mark_to_release(s, tcg_const_i32(offset + bd));
453
480
bd = 0;
454
481
}
455
482
if (!IS_NULL_QREG(add)) {
···
465
492
add = tmp;
466
493
}
467
494
} else {
468
-
add = tcg_const_i32(bd);
495
+
add = mark_to_release(s, tcg_const_i32(bd));
469
496
}
470
497
if ((ext & 3) != 0) {
471
498
/* memory indirect */
472
-
base = gen_load(s, OS_LONG, add, 0, IS_USER(s));
499
+
base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
473
500
if ((ext & 0x44) == 4) {
474
501
add = gen_addr_index(s, ext, tmp);
475
502
tcg_gen_add_i32(tmp, add, base);
···
494
521
}
495
522
} else {
496
523
/* brief extension word format */
497
-
tmp = tcg_temp_new();
524
+
tmp = mark_to_release(s, tcg_temp_new());
498
525
add = gen_addr_index(s, ext, tmp);
499
526
if (!IS_NULL_QREG(base)) {
500
527
tcg_gen_add_i32(tmp, add, base);
···
617
644
s->cc_op = CC_OP_FLAGS;
618
645
}
619
646
620
-
static inline TCGv gen_extend(TCGv val, int opsize, int sign)
647
+
static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
621
648
{
622
649
TCGv tmp;
623
650
624
651
if (opsize == OS_LONG) {
625
652
tmp = val;
626
653
} else {
627
-
tmp = tcg_temp_new();
654
+
tmp = mark_to_release(s, tcg_temp_new());
628
655
gen_ext(tmp, val, opsize, sign);
629
656
}
630
657
···
746
773
return NULL_QREG;
747
774
}
748
775
reg = get_areg(s, reg0);
749
-
tmp = tcg_temp_new();
776
+
tmp = mark_to_release(s, tcg_temp_new());
750
777
if (reg0 == 7 && opsize == OS_BYTE &&
751
778
m68k_feature(s->env, M68K_FEATURE_M68000)) {
752
779
tcg_gen_subi_i32(tmp, reg, 2);
···
756
783
return tmp;
757
784
case 5: /* Indirect displacement. */
758
785
reg = get_areg(s, reg0);
759
-
tmp = tcg_temp_new();
786
+
tmp = mark_to_release(s, tcg_temp_new());
760
787
ext = read_im16(env, s);
761
788
tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
762
789
return tmp;
···
767
794
switch (reg0) {
768
795
case 0: /* Absolute short. */
769
796
offset = (int16_t)read_im16(env, s);
770
-
return tcg_const_i32(offset);
797
+
return mark_to_release(s, tcg_const_i32(offset));
771
798
case 1: /* Absolute long. */
772
799
offset = read_im32(env, s);
773
-
return tcg_const_i32(offset);
800
+
return mark_to_release(s, tcg_const_i32(offset));
774
801
case 2: /* pc displacement */
775
802
offset = s->pc;
776
803
offset += (int16_t)read_im16(env, s);
777
-
return tcg_const_i32(offset);
804
+
return mark_to_release(s, tcg_const_i32(offset));
778
805
case 3: /* pc index+displacement. */
779
806
return gen_lea_indexed(env, s, NULL_QREG);
780
807
case 4: /* Immediate. */
···
811
838
gen_partset_reg(opsize, reg, val);
812
839
return store_dummy;
813
840
} else {
814
-
return gen_extend(reg, opsize, what == EA_LOADS);
841
+
return gen_extend(s, reg, opsize, what == EA_LOADS);
815
842
}
816
843
case 1: /* Address register direct. */
817
844
reg = get_areg(s, reg0);
···
819
846
tcg_gen_mov_i32(reg, val);
820
847
return store_dummy;
821
848
} else {
822
-
return gen_extend(reg, opsize, what == EA_LOADS);
849
+
return gen_extend(s, reg, opsize, what == EA_LOADS);
823
850
}
824
851
case 2: /* Indirect register */
825
852
reg = get_areg(s, reg0);
···
900
927
default:
901
928
g_assert_not_reached();
902
929
}
903
-
return tcg_const_i32(offset);
930
+
return mark_to_release(s, tcg_const_i32(offset));
904
931
default:
905
932
return NULL_QREG;
906
933
}
···
1759
1786
1760
1787
gen_flush_flags(s); /* !Z is sticky */
1761
1788
1762
-
src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1763
-
dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1789
+
src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1790
+
dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1764
1791
bcd_add(dest, src);
1765
1792
gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1766
1793
···
1794
1821
1795
1822
gen_flush_flags(s); /* !Z is sticky */
1796
1823
1797
-
src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1798
-
dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1824
+
src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1825
+
dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1799
1826
1800
1827
bcd_sub(dest, src);
1801
1828
···
1856
1883
1857
1884
add = (insn & 0x4000) != 0;
1858
1885
opsize = insn_opsize(insn);
1859
-
reg = gen_extend(DREG(insn, 9), opsize, 1);
1886
+
reg = gen_extend(s, DREG(insn, 9), opsize, 1);
1860
1887
dest = tcg_temp_new();
1861
1888
if (insn & 0x100) {
1862
1889
SRC_EA(env, tmp, opsize, 1, &addr);
···
2386
2413
return;
2387
2414
}
2388
2415
2389
-
cmp = gen_extend(DREG(ext, 0), opsize, 1);
2416
+
cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
2390
2417
2391
2418
/* if <EA> == Dc then
2392
2419
* <EA> = Du
···
3055
3082
int opsize;
3056
3083
3057
3084
opsize = insn_opsize(insn);
3058
-
reg = gen_extend(DREG(insn, 9), opsize, 0);
3085
+
reg = gen_extend(s, DREG(insn, 9), opsize, 0);
3059
3086
dest = tcg_temp_new();
3060
3087
if (insn & 0x100) {
3061
3088
SRC_EA(env, src, opsize, 0, &addr);
···
3120
3147
3121
3148
opsize = insn_opsize(insn);
3122
3149
3123
-
src = gen_extend(DREG(insn, 0), opsize, 1);
3124
-
dest = gen_extend(DREG(insn, 9), opsize, 1);
3150
+
src = gen_extend(s, DREG(insn, 0), opsize, 1);
3151
+
dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3125
3152
3126
3153
gen_subx(s, src, dest, opsize);
3127
3154
···
3176
3203
3177
3204
opsize = insn_opsize(insn);
3178
3205
SRC_EA(env, src, opsize, 1, NULL);
3179
-
reg = gen_extend(DREG(insn, 9), opsize, 1);
3206
+
reg = gen_extend(s, DREG(insn, 9), opsize, 1);
3180
3207
gen_update_cc_cmp(s, reg, src, opsize);
3181
3208
}
3182
3209
···
3329
3356
3330
3357
opsize = insn_opsize(insn);
3331
3358
3332
-
dest = gen_extend(DREG(insn, 9), opsize, 1);
3333
-
src = gen_extend(DREG(insn, 0), opsize, 1);
3359
+
dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3360
+
src = gen_extend(s, DREG(insn, 0), opsize, 1);
3334
3361
3335
3362
gen_addx(s, src, dest, opsize);
3336
3363
···
3369
3396
int logical = insn & 8;
3370
3397
int left = insn & 0x100;
3371
3398
int bits = opsize_bytes(opsize) * 8;
3372
-
TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3399
+
TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3373
3400
3374
3401
if (count == 0) {
3375
3402
count = 8;
···
3419
3446
int logical = insn & 8;
3420
3447
int left = insn & 0x100;
3421
3448
int bits = opsize_bytes(opsize) * 8;
3422
-
TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3449
+
TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3423
3450
TCGv s32;
3424
3451
TCGv_i64 t64, s64;
3425
3452
···
3556
3583
while M68000 sets if the most significant bit is changed at
3557
3584
any time during the shift operation */
3558
3585
if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3559
-
src = gen_extend(src, OS_WORD, 1);
3586
+
src = gen_extend(s, src, OS_WORD, 1);
3560
3587
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3561
3588
}
3562
3589
} else {
···
3789
3816
TCGv shift;
3790
3817
int tmp;
3791
3818
3792
-
reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3819
+
reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3793
3820
3794
3821
tmp = (insn >> 9) & 7;
3795
3822
if (tmp == 0) {
···
3816
3843
TCGv shift;
3817
3844
int tmp;
3818
3845
3819
-
reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3846
+
reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3820
3847
tmp = (insn >> 9) & 7;
3821
3848
if (tmp == 0) {
3822
3849
tmp = 8;
···
3876
3903
TCGv t0, t1;
3877
3904
int left = (insn & 0x100);
3878
3905
3879
-
reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3906
+
reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3880
3907
src = DREG(insn, 9);
3881
3908
/* shift in [0..63] */
3882
3909
t0 = tcg_temp_new_i32();
···
3911
3938
TCGv t0, t1;
3912
3939
int left = (insn & 0x100);
3913
3940
3914
-
reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3941
+
reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3915
3942
src = DREG(insn, 9);
3916
3943
/* shift in [0..63] */
3917
3944
t0 = tcg_temp_new_i32();
···
4353
4380
return;
4354
4381
}
4355
4382
SRC_EA(env, src, opsize, 1, NULL);
4356
-
reg = gen_extend(DREG(insn, 9), opsize, 1);
4383
+
reg = gen_extend(s, DREG(insn, 9), opsize, 1);
4357
4384
4358
4385
gen_flush_flags(s);
4359
4386
gen_helper_chk(cpu_env, reg, src);
···
6033
6060
uint16_t insn = read_im16(env, s);
6034
6061
opcode_table[insn](env, s, insn);
6035
6062
do_writebacks(s);
6063
+
do_release(s);
6036
6064
}
6037
6065
6038
6066
/* generate intermediate code for basic block 'tb'. */
···
6066
6094
if (max_insns > TCG_MAX_INSNS) {
6067
6095
max_insns = TCG_MAX_INSNS;
6068
6096
}
6097
+
6098
+
init_release_array(dc);
6069
6099
6070
6100
gen_tb_start(tb);
6071
6101
do {