+3 -1

bsd-user/main.c

··· 723 723 { 724 724 const char *filename; 725 725 const char *cpu_model; 726 726 + const char *cpu_type; 726 727 const char *log_file = NULL; 727 728 const char *log_mask = NULL; 728 729 struct target_pt_regs regs1, *regs = &regs1; ··· 900 901 tcg_exec_init(0); 901 902 /* NOTE: we need to init the CPU at this stage to get 902 903 qemu_host_page_size */ 903 903 - cpu = cpu_init(cpu_model); 904 904 + cpu_type = parse_cpu_model(cpu_model); 905 905 + cpu = cpu_create(cpu_type); 904 906 env = cpu->env_ptr; 905 907 #if defined(TARGET_SPARC) || defined(TARGET_PPC) 906 908 cpu_reset(cpu);

+23

exec.c

··· 817 817 #endif 818 818 } 819 819 820 820 + const char *parse_cpu_model(const char *cpu_model) 821 821 + { 822 822 + ObjectClass *oc; 823 823 + CPUClass *cc; 824 824 + gchar **model_pieces; 825 825 + const char *cpu_type; 826 826 + 827 827 + model_pieces = g_strsplit(cpu_model, ",", 2); 828 828 + 829 829 + oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]); 830 830 + if (oc == NULL) { 831 831 + error_report("unable to find CPU model '%s'", model_pieces[0]); 832 832 + g_strfreev(model_pieces); 833 833 + exit(EXIT_FAILURE); 834 834 + } 835 835 + 836 836 + cpu_type = object_class_get_name(oc); 837 837 + cc = CPU_CLASS(oc); 838 838 + cc->parse_features(cpu_type, model_pieces[1], &error_fatal); 839 839 + g_strfreev(model_pieces); 840 840 + return cpu_type; 841 841 + } 842 842 + 820 843 #if defined(CONFIG_USER_ONLY) 821 844 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) 822 845 {

+3 -3

hw/core/null-machine.c

··· 24 24 { 25 25 CPUState *cpu = NULL; 26 26 27 27 - /* Initialize CPU (if a model has been specified) */ 28 28 - if (mch->cpu_model) { 29 29 - cpu = cpu_init(mch->cpu_model); 27 27 + /* Initialize CPU (if user asked for it) */ 28 28 + if (mch->cpu_type) { 29 29 + cpu = cpu_create(mch->cpu_type); 30 30 if (!cpu) { 31 31 error_report("Unable to initialize CPU"); 32 32 exit(1);

+1 -1

hw/nios2/10m50_devboard.c

··· 75 75 phys_ram_alias); 76 76 77 77 /* Create CPU -- FIXME */ 78 78 - cpu = NIOS2_CPU(cpu_generic_init(TYPE_NIOS2_CPU, "nios2")); 78 78 + cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); 79 79 80 80 /* Register: CPU interrupt controller (PIC) */ 81 81 cpu_irq = nios2_cpu_pic_init(cpu);

-1

include/hw/boards.h

··· 252 252 char *kernel_filename; 253 253 char *kernel_cmdline; 254 254 char *initrd_filename; 255 255 - const char *cpu_model; 256 255 const char *cpu_type; 257 256 AccelState *accelerator; 258 257 CPUArchIdList *possible_cpus;

+2 -14

include/qom/cpu.h

··· 662 662 CPUState *cpu_create(const char *typename); 663 663 664 664 /** 665 665 - * cpu_parse_cpu_model: 666 666 - * @typename: The CPU base type or CPU type. 665 665 + * parse_cpu_model: 667 666 * @cpu_model: The model string including optional parameters. 668 667 * 669 668 * processes optional parameters and registers them as global properties ··· 671 670 * Returns: type of CPU to create or prints error and terminates process 672 671 * if an error occurred. 673 672 */ 674 674 - const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model); 675 675 - 676 676 - /** 677 677 - * cpu_generic_init: 678 678 - * @typename: The CPU base type. 679 679 - * @cpu_model: The model string including optional parameters. 680 680 - * 681 681 - * Instantiates a CPU, processes optional parameters and realizes the CPU. 682 682 - * 683 683 - * Returns: A #CPUState or %NULL if an error occurred. 684 684 - */ 685 685 - CPUState *cpu_generic_init(const char *typename, const char *cpu_model); 673 673 + const char *parse_cpu_model(const char *cpu_model); 686 674 687 675 /** 688 676 * cpu_has_work:

+6 -2

linux-user/main.c

··· 45 45 static int gdbstub_port; 46 46 static envlist_t *envlist; 47 47 static const char *cpu_model; 48 48 + static const char *cpu_type; 48 49 unsigned long mmap_min_addr; 49 50 unsigned long guest_base; 50 51 int have_guest_base; ··· 4114 4115 CPUArchState *cpu_copy(CPUArchState *env) 4115 4116 { 4116 4117 CPUState *cpu = ENV_GET_CPU(env); 4117 4117 - CPUState *new_cpu = cpu_init(cpu_model); 4118 4118 + CPUState *new_cpu = cpu_create(cpu_type); 4118 4119 CPUArchState *new_env = new_cpu->env_ptr; 4119 4120 CPUBreakpoint *bp; 4120 4121 CPUWatchpoint *wp; ··· 4597 4598 if (cpu_model == NULL) { 4598 4599 cpu_model = cpu_get_model(get_elf_eflags(execfd)); 4599 4600 } 4601 4601 + cpu_type = parse_cpu_model(cpu_model); 4602 4602 + 4600 4603 tcg_exec_init(0); 4601 4604 /* NOTE: we need to init the CPU at this stage to get 4602 4605 qemu_host_page_size */ 4603 4603 - cpu = cpu_init(cpu_model); 4606 4606 + 4607 4607 + cpu = cpu_create(cpu_type); 4604 4608 env = cpu->env_ptr; 4605 4609 cpu_reset(cpu); 4606 4610

+6 -55

qom/cpu.c

··· 67 67 return cpu; 68 68 } 69 69 70 70 - const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model) 71 71 - { 72 72 - ObjectClass *oc; 73 73 - CPUClass *cc; 74 74 - gchar **model_pieces; 75 75 - const char *cpu_type; 76 76 - 77 77 - model_pieces = g_strsplit(cpu_model, ",", 2); 78 78 - 79 79 - oc = cpu_class_by_name(typename, model_pieces[0]); 80 80 - if (oc == NULL) { 81 81 - error_report("unable to find CPU model '%s'", model_pieces[0]); 82 82 - g_strfreev(model_pieces); 83 83 - exit(EXIT_FAILURE); 84 84 - } 85 85 - 86 86 - cpu_type = object_class_get_name(oc); 87 87 - cc = CPU_CLASS(oc); 88 88 - cc->parse_features(cpu_type, model_pieces[1], &error_fatal); 89 89 - g_strfreev(model_pieces); 90 90 - return cpu_type; 91 91 - } 92 92 - 93 93 - CPUState *cpu_generic_init(const char *typename, const char *cpu_model) 94 94 - { 95 95 - /* TODO: all callers of cpu_generic_init() need to be converted to 96 96 - * call cpu_parse_features() only once, before calling cpu_generic_init(). 97 97 - */ 98 98 - return cpu_create(cpu_parse_cpu_model(typename, cpu_model)); 99 99 - } 100 100 - 101 70 bool cpu_paging_enabled(const CPUState *cpu) 102 71 { 103 72 CPUClass *cc = CPU_GET_CLASS(cpu); ··· 317 286 318 287 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) 319 288 { 320 320 - CPUClass *cc; 321 321 - 322 322 - if (!cpu_model) { 323 323 - return NULL; 324 324 - } 325 325 - cc = CPU_CLASS(object_class_by_name(typename)); 289 289 + CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); 326 290 291 291 + assert(cpu_model && cc->class_by_name); 327 292 return cc->class_by_name(cpu_model); 328 293 } 329 294 330 330 - static ObjectClass *cpu_common_class_by_name(const char *cpu_model) 331 331 - { 332 332 - return NULL; 333 333 - } 334 334 - 335 295 static void cpu_common_parse_features(const char *typename, char *features, 336 296 Error **errp) 337 297 { 338 338 - char *featurestr; /* Single "key=value" string being parsed */ 339 298 char *val; 340 299 static bool cpu_globals_initialized; 300 300 + /* Single "key=value" string being parsed */ 301 301 + char *featurestr = features ? strtok(features, ",") : NULL; 341 302 342 342 - /* TODO: all callers of ->parse_features() need to be changed to 343 343 - * call it only once, so we can remove this check (or change it 344 344 - * to assert(!cpu_globals_initialized). 345 345 - * Current callers of ->parse_features() are: 346 346 - * - cpu_generic_init() 347 347 - */ 348 348 - if (cpu_globals_initialized) { 349 349 - return; 350 350 - } 303 303 + /* should be called only once, catch invalid users */ 304 304 + assert(!cpu_globals_initialized); 351 305 cpu_globals_initialized = true; 352 352 - 353 353 - featurestr = features ? strtok(features, ",") : NULL; 354 306 355 307 while (featurestr) { 356 308 val = strchr(featurestr, '='); ··· 457 409 DeviceClass *dc = DEVICE_CLASS(klass); 458 410 CPUClass *k = CPU_CLASS(klass); 459 411 460 460 - k->class_by_name = cpu_common_class_by_name; 461 412 k->parse_features = cpu_common_parse_features; 462 413 k->reset = cpu_common_reset; 463 414 k->get_arch_id = cpu_common_get_arch_id;

+1 -2

target/alpha/cpu.h

··· 466 466 467 467 void alpha_translate_init(void); 468 468 469 469 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_ALPHA_CPU, cpu_model) 470 470 - 471 469 #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU 472 470 #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX 471 471 + #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU 473 472 474 473 void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf); 475 474 /* you can call this signal handler from your SIGBUS and SIGSEGV

+1 -2

target/arm/cpu.h

··· 2302 2302 return unmasked || pstate_unmasked; 2303 2303 } 2304 2304 2305 2305 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2306 2306 - 2307 2305 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2308 2306 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2307 2307 + #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2309 2308 2310 2309 #define cpu_signal_handler cpu_arm_signal_handler 2311 2310 #define cpu_list arm_cpu_list

+1 -2

target/cris/cpu.h

··· 267 267 #define TARGET_PHYS_ADDR_SPACE_BITS 32 268 268 #define TARGET_VIRT_ADDR_SPACE_BITS 32 269 269 270 270 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_CRIS_CPU, cpu_model) 271 271 - 272 270 #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU 273 271 #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) 272 272 + #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU 274 273 275 274 #define cpu_signal_handler cpu_cris_signal_handler 276 275

+1 -1

target/hppa/cpu.h

··· 266 266 267 267 void hppa_translate_init(void); 268 268 269 269 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_HPPA_CPU, cpu_model) 269 269 + #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 270 270 271 271 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); 272 272

+5 -8

target/i386/cpu.c

··· 195 195 * bit[02]: Support Single-Range Output scheme; 196 196 */ 197 197 #define INTEL_PT_MINIMAL_ECX 0x7 198 198 + /* generated packets which contain IP payloads have LIP values */ 199 199 + #define INTEL_PT_IP_LIP (1 << 31) 198 200 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 199 201 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 200 202 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ ··· 781 783 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 782 784 { 783 785 ObjectClass *oc; 784 784 - char *typename; 785 785 - 786 786 - if (cpu_model == NULL) { 787 787 - return NULL; 788 788 - } 789 789 - 790 790 - typename = x86_cpu_type_name(cpu_model); 786 786 + char *typename = x86_cpu_type_name(cpu_model); 791 787 oc = object_class_by_name(typename); 792 788 g_free(typename); 793 789 return oc; ··· 4173 4169 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 4174 4170 INTEL_PT_ADDR_RANGES_NUM) || 4175 4171 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 4176 4176 - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) { 4172 4172 + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 4173 4173 + (ecx_0 & INTEL_PT_IP_LIP)) { 4177 4174 /* 4178 4175 * Processor Trace capabilities aren't configurable, so if the 4179 4176 * host can't emulate the capabilities we report on

+1 -2

target/i386/cpu.h

··· 1589 1589 1590 1590 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) 1591 1591 1592 1592 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model) 1593 1593 - 1594 1592 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1595 1593 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1594 1594 + #define CPU_RESOLVING_TYPE TYPE_X86_CPU 1596 1595 1597 1596 #ifdef TARGET_X86_64 1598 1597 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")

+1 -2

target/lm32/cpu.h

··· 255 255 void lm32_watchpoint_remove(CPULM32State *env, int index); 256 256 bool lm32_cpu_do_semihosting(CPUState *cs); 257 257 258 258 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_LM32_CPU, cpu_model) 259 259 - 260 258 #define LM32_CPU_TYPE_SUFFIX "-" TYPE_LM32_CPU 261 259 #define LM32_CPU_TYPE_NAME(model) model LM32_CPU_TYPE_SUFFIX 260 260 + #define CPU_RESOLVING_TYPE TYPE_LM32_CPU 262 261 263 262 #define cpu_list lm32_cpu_list 264 263 #define cpu_signal_handler cpu_lm32_signal_handler

+1 -2

target/m68k/cpu.h

··· 527 527 #define TARGET_PHYS_ADDR_SPACE_BITS 32 528 528 #define TARGET_VIRT_ADDR_SPACE_BITS 32 529 529 530 530 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_M68K_CPU, cpu_model) 531 531 - 532 530 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 533 531 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 532 532 + #define CPU_RESOLVING_TYPE TYPE_M68K_CPU 534 533 535 534 #define cpu_signal_handler cpu_m68k_signal_handler 536 535 #define cpu_list m68k_cpu_list

+1 -1

target/microblaze/cpu.h

··· 343 343 #define TARGET_PHYS_ADDR_SPACE_BITS 32 344 344 #define TARGET_VIRT_ADDR_SPACE_BITS 32 345 345 346 346 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_MICROBLAZE_CPU, cpu_model) 346 346 + #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU 347 347 348 348 #define cpu_signal_handler cpu_mb_signal_handler 349 349

+1 -2

target/mips/cpu.h

··· 739 739 740 740 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 741 741 742 742 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model) 743 743 - 744 742 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 745 743 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 744 744 + #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 746 745 747 746 bool cpu_supports_cps_smp(const char *cpu_type); 748 747 bool cpu_supports_isa(const char *cpu_type, unsigned int isa);

+1 -2

target/moxie/cpu.h

··· 119 119 int cpu_moxie_signal_handler(int host_signum, void *pinfo, 120 120 void *puc); 121 121 122 122 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_MOXIE_CPU, cpu_model) 123 123 - 124 122 #define MOXIE_CPU_TYPE_SUFFIX "-" TYPE_MOXIE_CPU 125 123 #define MOXIE_CPU_TYPE_NAME(model) model MOXIE_CPU_TYPE_SUFFIX 124 124 + #define CPU_RESOLVING_TYPE TYPE_MOXIE_CPU 126 125 127 126 #define cpu_signal_handler cpu_moxie_signal_handler 128 127

+1 -1

target/nios2/cpu.h

··· 230 230 # define TARGET_VIRT_ADDR_SPACE_BITS 32 231 231 #endif 232 232 233 233 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_NIOS2_CPU, cpu_model) 233 233 + #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU 234 234 235 235 #define cpu_gen_code cpu_nios2_gen_code 236 236 #define cpu_signal_handler cpu_nios2_signal_handler

+1 -2

target/openrisc/cpu.h

··· 389 389 int *prot, target_ulong address, int rw); 390 390 #endif 391 391 392 392 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model) 393 393 - 394 392 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU 395 393 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX 394 394 + #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 396 395 397 396 #include "exec/cpu-all.h" 398 397

+1 -2

target/ppc/cpu.h

··· 1375 1375 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); 1376 1376 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); 1377 1377 1378 1378 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_POWERPC_CPU, cpu_model) 1379 1379 - 1380 1378 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU 1381 1379 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX 1380 1380 + #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU 1382 1381 1383 1382 #define cpu_signal_handler cpu_ppc_signal_handler 1384 1383 #define cpu_list ppc_cpu_list

+1

target/riscv/cpu.h

··· 46 46 47 47 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 48 48 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 49 49 + #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 49 50 50 51 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 51 52 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")

+1 -2

target/s390x/cpu.h

··· 719 719 720 720 721 721 /* helper.c */ 722 722 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model) 723 723 - 724 722 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 725 723 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 724 724 + #define CPU_RESOLVING_TYPE TYPE_S390_CPU 726 725 727 726 /* you can call this signal handler from your SIGBUS and SIGSEGV 728 727 signal handlers to inform the virtual CPU of exceptions. non zero

+1 -2

target/sh4/cpu.h

··· 272 272 273 273 void cpu_load_tlb(CPUSH4State * env); 274 274 275 275 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_SUPERH_CPU, cpu_model) 276 276 - 277 275 #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU 278 276 #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX 277 277 + #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU 279 278 280 279 #define cpu_signal_handler cpu_sh4_signal_handler 281 280 #define cpu_list sh4_cpu_list

+1 -4

target/sparc/cpu.h

··· 652 652 #endif 653 653 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); 654 654 655 655 - #ifndef NO_CPU_IO_DEFS 656 656 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_SPARC_CPU, cpu_model) 657 657 - #endif 658 658 - 659 655 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU 660 656 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX 657 657 + #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 661 658 662 659 #define cpu_signal_handler cpu_sparc_signal_handler 663 660 #define cpu_list sparc_cpu_list

+1 -1

target/tilegx/cpu.h

··· 164 164 void tilegx_tcg_init(void); 165 165 int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc); 166 166 167 167 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_TILEGX_CPU, cpu_model) 167 167 + #define CPU_RESOLVING_TYPE TYPE_TILEGX_CPU 168 168 169 169 #define cpu_signal_handler cpu_tilegx_signal_handler 170 170

+1 -2

target/tricore/cpu.h

··· 413 413 *flags = 0; 414 414 } 415 415 416 416 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_TRICORE_CPU, cpu_model) 417 417 - 418 416 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU 419 417 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX 418 418 + #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU 420 419 421 420 /* helpers.c */ 422 421 int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,

+1 -2

target/unicore32/cpu.h

··· 164 164 165 165 #include "exec/cpu-all.h" 166 166 167 167 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model) 168 168 - 169 167 #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU 170 168 #define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX 169 169 + #define CPU_RESOLVING_TYPE TYPE_UNICORE32_CPU 171 170 172 171 static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc, 173 172 target_ulong *cs_base, uint32_t *flags)

+1 -2

target/xtensa/cpu.h

··· 513 513 514 514 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU 515 515 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX 516 516 + #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU 516 517 517 518 #ifdef TARGET_WORDS_BIGENDIAN 518 519 #define XTENSA_DEFAULT_CPU_MODEL "fsf" ··· 525 526 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) 526 527 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 527 528 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 528 528 - 529 529 - #define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model) 530 529 531 530 void xtensa_translate_init(void); 532 531 void xtensa_breakpoint_handler(CPUState *cs);

+2

tests/Makefile.include

··· 400 400 check-qtest-s390x-y += tests/virtio-serial-test$(EXESUF) 401 401 check-qtest-s390x-y += tests/cpu-plug-test$(EXESUF) 402 402 403 403 + check-qtest-generic-y += tests/machine-none-test$(EXESUF) 403 404 check-qtest-generic-y += tests/qom-test$(EXESUF) 404 405 check-qtest-generic-y += tests/test-hmp$(EXESUF) 405 406 ··· 797 798 tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o 798 799 tests/qom-test$(EXESUF): tests/qom-test.o 799 800 tests/test-hmp$(EXESUF): tests/test-hmp.o 801 801 + tests/machine-none-test$(EXESUF): tests/machine-none-test.o 800 802 tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-virtio-obj-y) 801 803 tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y) 802 804 tests/nvme-test$(EXESUF): tests/nvme-test.o

+103

tests/machine-none-test.c

··· 1 1 + /* 2 2 + * Machine 'none' tests. 3 3 + * 4 4 + * Copyright (c) 2018 Red Hat Inc. 5 5 + * 6 6 + * Authors: 7 7 + * Igor Mammedov <imammedo@redhat.com>, 8 8 + * 9 9 + * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 10 + * See the COPYING file in the top-level directory. 11 11 + */ 12 12 + 13 13 + #include "qemu/osdep.h" 14 14 + 15 15 + #include "qemu-common.h" 16 16 + #include "qemu/cutils.h" 17 17 + #include "libqtest.h" 18 18 + #include "qapi/qmp/qdict.h" 19 19 + 20 20 + 21 21 + struct arch2cpu { 22 22 + const char *arch; 23 23 + const char *cpu_model; 24 24 + }; 25 25 + 26 26 + static struct arch2cpu cpus_map[] = { 27 27 + /* tested targets list */ 28 28 + { "arm", "cortex-a15" }, 29 29 + { "aarch64", "cortex-a57" }, 30 30 + { "x86_64", "qemu64,apic-id=0" }, 31 31 + { "i386", "qemu32,apic-id=0" }, 32 32 + { "alpha", "ev67" }, 33 33 + { "cris", "crisv32" }, 34 34 + { "lm32", "lm32-full" }, 35 35 + { "m68k", "m5206" }, 36 36 + /* FIXME: { "microblaze", "any" }, doesn't work with -M none -cpu any */ 37 37 + /* FIXME: { "microblazeel", "any" }, doesn't work with -M none -cpu any */ 38 38 + { "mips", "4Kc" }, 39 39 + { "mipsel", "4Kc" }, 40 40 + { "mips64", "20Kc" }, 41 41 + { "mips64el", "20Kc" }, 42 42 + { "moxie", "MoxieLite" }, 43 43 + { "nios2", "FIXME" }, 44 44 + { "or1k", "or1200" }, 45 45 + { "ppc", "604" }, 46 46 + { "ppc64", "power8e_v2.1" }, 47 47 + { "ppcemb", "440epb" }, 48 48 + { "s390x", "qemu" }, 49 49 + { "sh4", "sh7750r" }, 50 50 + { "sh4eb", "sh7751r" }, 51 51 + { "sparc", "LEON2" }, 52 52 + { "sparc64", "Fujitsu Sparc64" }, 53 53 + { "tricore", "tc1796" }, 54 54 + { "unicore32", "UniCore-II" }, 55 55 + { "xtensa", "dc233c" }, 56 56 + { "xtensaeb", "fsf" }, 57 57 + { "hppa", "hppa" }, 58 58 + { "riscv64", "rv64gcsu-v1.10.0" }, 59 59 + { "riscv32", "rv32gcsu-v1.9.1" }, 60 60 + }; 61 61 + 62 62 + static const char *get_cpu_model_by_arch(const char *arch) 63 63 + { 64 64 + int i; 65 65 + 66 66 + for (i = 0; i < ARRAY_SIZE(cpus_map); i++) { 67 67 + if (!strcmp(arch, cpus_map[i].arch)) { 68 68 + return cpus_map[i].cpu_model; 69 69 + } 70 70 + } 71 71 + return NULL; 72 72 + } 73 73 + 74 74 + static void test_machine_cpu_cli(void) 75 75 + { 76 76 + QDict *response; 77 77 + const char *arch = qtest_get_arch(); 78 78 + const char *cpu_model = get_cpu_model_by_arch(arch); 79 79 + 80 80 + if (!cpu_model) { 81 81 + if (!(!strcmp(arch, "microblaze") || !strcmp(arch, "microblazeel"))) { 82 82 + fprintf(stderr, "WARNING: cpu name for target '%s' isn't defined," 83 83 + " add it to cpus_map\n", arch); 84 84 + } 85 85 + return; /* TODO: die here to force all targets have a test */ 86 86 + } 87 87 + global_qtest = qtest_startf("-machine none -cpu '%s'", cpu_model); 88 88 + 89 89 + response = qmp("{ 'execute': 'quit' }"); 90 90 + g_assert(qdict_haskey(response, "return")); 91 91 + QDECREF(response); 92 92 + 93 93 + qtest_quit(global_qtest); 94 94 + } 95 95 + 96 96 + int main(int argc, char **argv) 97 97 + { 98 98 + g_test_init(&argc, &argv, NULL); 99 99 + 100 100 + qtest_add_func("machine/none/cpu_option", test_machine_cpu_cli); 101 101 + 102 102 + return g_test_run(); 103 103 + }

+3 -7

vl.c

··· 4589 4589 current_machine->maxram_size = maxram_size; 4590 4590 current_machine->ram_slots = ram_slots; 4591 4591 current_machine->boot_order = boot_order; 4592 4592 - current_machine->cpu_model = cpu_model; 4593 4592 4594 4593 /* parse features once if machine provides default cpu_type */ 4595 4595 - if (machine_class->default_cpu_type) { 4596 4596 - current_machine->cpu_type = machine_class->default_cpu_type; 4597 4597 - if (cpu_model) { 4598 4598 - current_machine->cpu_type = 4599 4599 - cpu_parse_cpu_model(machine_class->default_cpu_type, cpu_model); 4600 4600 - } 4594 4594 + current_machine->cpu_type = machine_class->default_cpu_type; 4595 4595 + if (cpu_model) { 4596 4596 + current_machine->cpu_type = parse_cpu_model(cpu_model); 4601 4597 } 4602 4598 parse_numa_opts(current_machine); 4603 4599