target/openrisc: Implement l.adrp · jcs.org/qemu@3e0e41e

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

target/openrisc: Implement l.adrp

This was added to the 1.3 spec.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Richard Henderson 6 years ago 3e0e41ef a465772e

+16

3 changed files

expand all

target

openrisc

disas.c

insns.decode

translate.c

target/openrisc/disas.c

··· 98 98 INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) 99 99 INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) 100 100 INSN(nop, "") 101 + INSN(adrp, "r%d, %d", a->d, a->i) 101 102 INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) 102 103 INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) 103 104 INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i)

target/openrisc/insns.decode

··· 102 102 l_movhi 000110 d:5 ----0 k:16 103 103 l_macrc 000110 d:5 ----1 00000000 00000000 104 104 105 + l_adrp 000010 d:5 i:s21 106 + 105 107 #### 106 108 # Arithmetic Instructions 107 109 ####

+13

target/openrisc/translate.c

··· 799 799 return true; 800 800 } 801 801 802 + static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) 803 + { 804 + if (!check_v1_3(dc)) { 805 + return false; 806 + } 807 + check_r0_write(dc, a->d); 808 + 809 + tcg_gen_movi_i32(cpu_R(dc, a->d), 810 + (dc->base.pc_next & TARGET_PAGE_MASK) + 811 + ((target_long)a->i << TARGET_PAGE_BITS)); 812 + return true; 813 + } 814 + 802 815 static bool trans_l_addi(DisasContext *dc, arg_rri *a) 803 816 { 804 817 TCGv t0;