jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/openrisc: Implement move to/from FPCSR
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+38
-5
+1
target/openrisc/cpu.c
+1
target/openrisc/cpu.c
+2
target/openrisc/cpu.h
+2
target/openrisc/cpu.h
+13
target/openrisc/fpu_helper.c
+13
target/openrisc/fpu_helper.c
···
61
61
}
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}
63
63
64
+
void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
65
+
{
66
+
static const int rm_to_sf[] = {
67
+
float_round_nearest_even,
68
+
float_round_to_zero,
69
+
float_round_up,
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+
float_round_down
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+
};
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+
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+
env->fpcsr = val & 0x7ff;
74
+
set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status);
75
+
}
76
+
64
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uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
65
78
{
66
79
return int64_to_float64(val, &env->fp_status);
+11
target/openrisc/machine.c
+11
target/openrisc/machine.c
···
121
121
}
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};
123
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124
+
static int cpu_post_load(void *opaque, int version_id)
125
+
{
126
+
OpenRISCCPU *cpu = opaque;
127
+
CPUOpenRISCState *env = &cpu->env;
128
+
129
+
/* Update env->fp_status to match env->fpcsr. */
130
+
cpu_set_fpcsr(env, env->fpcsr);
131
+
return 0;
132
+
}
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+
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const VMStateDescription vmstate_openrisc_cpu = {
125
135
.name = "cpu",
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.version_id = 1,
127
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.minimum_version_id = 1,
138
+
.post_load = cpu_post_load,
128
139
.fields = (VMStateField[]) {
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140
VMSTATE_CPU(),
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VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
+11
-5
target/openrisc/sys_helper.c
+11
-5
target/openrisc/sys_helper.c
···
37
37
CPUState *cs = env_cpu(env);
38
38
target_ulong mr;
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int idx;
40
+
#endif
40
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switch (spr) {
43
+
#ifndef CONFIG_USER_ONLY
42
44
case TO_SPR(0, 11): /* EVBAR */
43
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env->evbar = rb;
44
46
break;
···
179
181
}
180
182
cpu_openrisc_timer_update(cpu);
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183
break;
182
-
default:
184
+
#endif
185
+
186
+
case TO_SPR(0, 20): /* FPCSR */
187
+
cpu_set_fpcsr(env, rb);
183
188
break;
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189
}
185
-
#endif
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190
}
187
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target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
···
193
197
OpenRISCCPU *cpu = env_archcpu(env);
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198
CPUState *cs = env_cpu(env);
195
199
int idx;
200
+
#endif
196
201
197
202
switch (spr) {
203
+
#ifndef CONFIG_USER_ONLY
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case TO_SPR(0, 0): /* VR */
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return env->vr;
200
206
···
303
309
case TO_SPR(10, 1): /* TTCR */
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cpu_openrisc_count_update(cpu);
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return cpu_openrisc_count_get(cpu);
312
+
#endif
306
313
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-
default:
308
-
break;
314
+
case TO_SPR(0, 20): /* FPCSR */
315
+
return env->fpcsr;
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316
}
310
-
#endif
311
317
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/* for rd is passed in, if rd unchanged, just keep it back. */
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return rd;