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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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aspeed: Link SCU to the watchdog

The ast2500 uses the watchdog to reset the SDRAM controller. This
operation is usually performed by u-boot's memory training procedure,
and it is enabled by setting a bit in the SCU and then causing the
watchdog to expire. Therefore, we need the watchdog to be able to
access the SCU's register space.

This causes the watchdog to not perform a system reset when the bit is
set. In the future it could perform a reset of the SDMC model.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190621065242.32535-1-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

authored by

Joel Stanley and committed by
Peter Maydell 3059c2f5 ebd205c0

+23
+2
hw/arm/aspeed_soc.c
··· 235 235 sizeof(s->wdt[i]), TYPE_ASPEED_WDT); 236 236 qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", 237 237 sc->info->silicon_rev); 238 + object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", 239 + OBJECT(&s->scu), &error_abort); 238 240 } 239 241 240 242 for (i = 0; i < ASPEED_MACS_NUM; i++) {
+20
hw/watchdog/wdt_aspeed.c
··· 44 44 45 45 #define WDT_RESTART_MAGIC 0x4755 46 46 47 + #define SCU_RESET_CONTROL1 (0x04 / 4) 48 + #define SCU_RESET_SDRAM BIT(0) 49 + 47 50 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) 48 51 { 49 52 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; ··· 222 225 { 223 226 AspeedWDTState *s = ASPEED_WDT(dev); 224 227 228 + /* Do not reset on SDRAM controller reset */ 229 + if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) { 230 + timer_del(s->timer); 231 + s->regs[WDT_CTRL] = 0; 232 + return; 233 + } 234 + 225 235 qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); 226 236 watchdog_perform_action(); 227 237 timer_del(s->timer); ··· 233 243 { 234 244 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 235 245 AspeedWDTState *s = ASPEED_WDT(dev); 246 + Error *err = NULL; 247 + Object *obj; 248 + 249 + obj = object_property_get_link(OBJECT(dev), "scu", &err); 250 + if (!obj) { 251 + error_propagate(errp, err); 252 + error_prepend(errp, "required link 'scu' not found: "); 253 + return; 254 + } 255 + s->scu = ASPEED_SCU(obj); 236 256 237 257 if (!is_supported_silicon_rev(s->silicon_rev)) { 238 258 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
+1
include/hw/watchdog/wdt_aspeed.h
··· 27 27 MemoryRegion iomem; 28 28 uint32_t regs[ASPEED_WDT_REGS_MAX]; 29 29 30 + AspeedSCUState *scu; 30 31 uint32_t pclk_freq; 31 32 uint32_t silicon_rev; 32 33 uint32_t ext_pulse_width_mask;