jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
aspeed: vic: Add support for legacy register interface
The legacy interface only supported up to 32 IRQs, which became
restrictive around the AST2400 generation. QEMU support for the SoCs
started with the AST2400 along with an effort to reimplement and
upstream drivers for Linux, so up until this point the consumers of the
QEMU ASPEED support only required the 64 IRQ register interface.
In an effort to support older BMC firmware, add support for the 32 IRQ
interface.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-22-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Andrew Jeffery
and committed by
Peter Maydell
ebd205c0
118c82e7
+63
-42
+63
-42
hw/intc/aspeed_vic.c
+63
-42
hw/intc/aspeed_vic.c
···
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static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedVICState *s = (AspeedVICState *)opaque;
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hwaddr n_offset;
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uint64_t val;
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-
const bool high = !!(offset & 0x4);
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hwaddr n_offset = (offset & ~0x4);
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AspeedVICState *s = (AspeedVICState *)opaque;
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bool high;
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if (offset < AVIC_NEW_BASE_OFFSET) {
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qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers "
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"at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, size);
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return 0;
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high = false;
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n_offset = offset;
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} else {
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high = !!(offset & 0x4);
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n_offset = (offset & ~0x4);
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}
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n_offset -= AVIC_NEW_BASE_OFFSET;
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-
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switch (n_offset) {
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case 0x0: /* IRQ Status */
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case 0x80: /* IRQ Status */
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case 0x00:
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val = s->raw & ~s->select & s->enable;
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break;
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-
case 0x08: /* FIQ Status */
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case 0x88: /* FIQ Status */
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case 0x04:
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val = s->raw & s->select & s->enable;
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break;
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-
case 0x10: /* Raw Interrupt Status */
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case 0x90: /* Raw Interrupt Status */
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case 0x08:
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val = s->raw;
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break;
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-
case 0x18: /* Interrupt Selection */
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case 0x98: /* Interrupt Selection */
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case 0x0c:
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val = s->select;
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break;
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-
case 0x20: /* Interrupt Enable */
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case 0xa0: /* Interrupt Enable */
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case 0x10:
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val = s->enable;
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break;
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-
case 0x30: /* Software Interrupt */
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case 0xb0: /* Software Interrupt */
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case 0x18:
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val = s->trigger;
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break;
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-
case 0x40: /* Interrupt Sensitivity */
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case 0xc0: /* Interrupt Sensitivity */
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case 0x24:
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val = s->sense;
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break;
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-
case 0x48: /* Interrupt Both Edge Trigger Control */
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case 0xc8: /* Interrupt Both Edge Trigger Control */
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case 0x28:
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val = s->dual_edge;
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break;
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-
case 0x50: /* Interrupt Event */
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case 0xd0: /* Interrupt Event */
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case 0x2c:
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val = s->event;
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break;
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-
case 0x60: /* Edge Triggered Interrupt Status */
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case 0xe0: /* Edge Triggered Interrupt Status */
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val = s->raw & ~s->sense;
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break;
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/* Illegal */
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-
case 0x28: /* Interrupt Enable Clear */
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-
case 0x38: /* Software Interrupt Clear */
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-
case 0x58: /* Edge Triggered Interrupt Clear */
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case 0xa8: /* Interrupt Enable Clear */
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case 0xb8: /* Software Interrupt Clear */
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case 0xd8: /* Edge Triggered Interrupt Clear */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Read of write-only register with offset 0x%"
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HWADDR_PRIx "\n", __func__, offset);
···
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}
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if (high) {
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val = extract64(val, 32, 19);
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} else {
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val = extract64(val, 0, 32);
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}
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trace_aspeed_vic_read(offset, size, val);
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return val;
···
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static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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-
const bool high = !!(offset & 0x4);
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hwaddr n_offset = (offset & ~0x4);
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AspeedVICState *s = (AspeedVICState *)opaque;
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hwaddr n_offset;
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bool high;
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if (offset < AVIC_NEW_BASE_OFFSET) {
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qemu_log_mask(LOG_UNIMP,
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"%s: Ignoring write to legacy registers at 0x%"
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HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, offset,
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size, data);
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return;
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high = false;
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n_offset = offset;
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} else {
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high = !!(offset & 0x4);
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n_offset = (offset & ~0x4);
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}
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n_offset -= AVIC_NEW_BASE_OFFSET;
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trace_aspeed_vic_write(offset, size, data);
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/* Given we have members using separate enable/clear registers, deposit64()
···
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}
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switch (n_offset) {
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-
case 0x18: /* Interrupt Selection */
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case 0x98: /* Interrupt Selection */
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case 0x0c:
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/* Register has deposit64() semantics - overwrite requested 32 bits */
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if (high) {
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s->select &= AVIC_L_MASK;
···
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}
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s->select |= data;
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break;
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-
case 0x20: /* Interrupt Enable */
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case 0xa0: /* Interrupt Enable */
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case 0x10:
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s->enable |= data;
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break;
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-
case 0x28: /* Interrupt Enable Clear */
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case 0xa8: /* Interrupt Enable Clear */
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case 0x14:
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s->enable &= ~data;
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break;
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-
case 0x30: /* Software Interrupt */
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case 0xb0: /* Software Interrupt */
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case 0x18:
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qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
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"IRQs requested: 0x%016" PRIx64 "\n", __func__, data);
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break;
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-
case 0x38: /* Software Interrupt Clear */
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case 0xb8: /* Software Interrupt Clear */
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case 0x1c:
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qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
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"IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, data);
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break;
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-
case 0x50: /* Interrupt Event */
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case 0xd0: /* Interrupt Event */
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/* Register has deposit64() semantics - overwrite the top four valid
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* IRQ bits, as only the top four IRQs (GPIOs) can change their event
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* type */
···
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"Ignoring invalid write to interrupt event register");
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}
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break;
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-
case 0x58: /* Edge Triggered Interrupt Clear */
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case 0xd8: /* Edge Triggered Interrupt Clear */
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case 0x38:
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s->raw &= ~(data & ~s->sense);
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break;
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-
case 0x00: /* IRQ Status */
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-
case 0x08: /* FIQ Status */
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case 0x10: /* Raw Interrupt Status */
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-
case 0x40: /* Interrupt Sensitivity */
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-
case 0x48: /* Interrupt Both Edge Trigger Control */
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-
case 0x60: /* Edge Triggered Interrupt Status */
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+
case 0x80: /* IRQ Status */
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+
case 0x00:
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+
case 0x88: /* FIQ Status */
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+
case 0x04:
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+
case 0x90: /* Raw Interrupt Status */
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+
case 0x08:
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+
case 0xc0: /* Interrupt Sensitivity */
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+
case 0x24:
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+
case 0xc8: /* Interrupt Both Edge Trigger Control */
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+
case 0x28:
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+
case 0xe0: /* Edge Triggered Interrupt Status */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Write of read-only register with offset 0x%"
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HWADDR_PRIx "\n", __func__, offset);