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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/microblaze: gdb: Fix incorrect SReg reporting

SRegs used to be reported to GDB by iterating over the SRegs array,
however we do not store them in an order that allows them to be
reported to GDB in that way.

To fix this, a simple map is used to map the register GDB wants to its
location in the SRegs array.

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <1589393329-223076-3-git-send-email-komlodi@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

authored by

Joe Komlodi and committed by
Edgar E. Iglesias 201dd7d3 a44e82db

+49 -10
+49 -10
target/microblaze/gdbstub.c
··· 25 25 { 26 26 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 27 27 CPUMBState *env = &cpu->env; 28 + /* 29 + * GDB expects SREGs in the following order: 30 + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. 31 + * They aren't stored in this order, so make a map. 32 + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't 33 + * map them to anything and return a value of 0 instead. 34 + */ 35 + static const uint8_t sreg_map[6] = { 36 + SR_PC, 37 + SR_MSR, 38 + SR_EAR, 39 + SR_ESR, 40 + SR_FSR, 41 + SR_BTR 42 + }; 28 43 29 44 /* 30 45 * GDB expects registers to be reported in this order: ··· 40 55 n -= 32; 41 56 switch (n) { 42 57 case 0 ... 5: 43 - return gdb_get_reg32(mem_buf, env->sregs[n]); 58 + return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]); 44 59 /* PVR12 is intentionally skipped */ 45 60 case 6 ... 17: 46 61 n -= 6; 47 62 return gdb_get_reg32(mem_buf, env->pvr.regs[n]); 48 - case 18 ... 24: 49 - /* Add an offset of 6 to resume where we left off with SRegs */ 50 - n = n - 18 + 6; 51 - return gdb_get_reg32(mem_buf, env->sregs[n]); 63 + case 18: 64 + return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]); 65 + /* Other SRegs aren't modeled, so report a value of 0 */ 66 + case 19 ... 24: 67 + return gdb_get_reg32(mem_buf, 0); 52 68 case 25: 53 69 return gdb_get_reg32(mem_buf, env->slr); 54 70 case 26: ··· 66 82 CPUMBState *env = &cpu->env; 67 83 uint32_t tmp; 68 84 85 + /* 86 + * GDB expects SREGs in the following order: 87 + * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. 88 + * They aren't stored in this order, so make a map. 89 + * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't 90 + * map them to anything. 91 + */ 92 + static const uint8_t sreg_map[6] = { 93 + SR_PC, 94 + SR_MSR, 95 + SR_EAR, 96 + SR_ESR, 97 + SR_FSR, 98 + SR_BTR 99 + }; 100 + 69 101 if (n > cc->gdb_num_core_regs) { 70 102 return 0; 71 103 } 72 104 73 105 tmp = ldl_p(mem_buf); 74 106 107 + /* 108 + * GDB expects registers to be reported in this order: 109 + * R0-R31 110 + * PC-BTR 111 + * PVR0-PVR11 112 + * EDR-TLBHI 113 + * SLR-SHR 114 + */ 75 115 if (n < 32) { 76 116 env->regs[n] = tmp; 77 117 } else { 78 118 n -= 32; 79 119 switch (n) { 80 120 case 0 ... 5: 81 - env->sregs[n] = tmp; 121 + env->sregs[sreg_map[n]] = tmp; 82 122 break; 83 123 /* PVR12 is intentionally skipped */ 84 124 case 6 ... 17: 85 125 n -= 6; 86 126 env->pvr.regs[n] = tmp; 87 127 break; 88 - case 18 ... 24: 89 - /* Add an offset of 6 to resume where we left off with SRegs */ 90 - n = n - 18 + 6; 91 - env->sregs[n] = tmp; 128 + /* Only EDR is modeled in these indeces, so ignore the rest */ 129 + case 18: 130 + env->sregs[SR_EDR] = tmp; 92 131 break; 93 132 case 25: 94 133 env->slr = tmp;