jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/timer/imx_gpt.c: Switch to transaction-based ptimer API
Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191008171740.9679-19-peter.maydell@linaro.org
+17
-4
+17
-4
hw/timer/imx_gpt.c
+17
-4
hw/timer/imx_gpt.c
···
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#include "hw/irq.h"
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#include "hw/timer/imx_gpt.h"
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#include "migration/vmstate.h"
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-
#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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21
···
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CLK_NONE, /* 111 not defined */
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};
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+
/* Must be called from within ptimer_transaction_begin/commit block */
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static void imx_gpt_set_freq(IMXGPTState *s)
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{
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uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
···
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return timeout;
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}
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+
/* Must be called from within ptimer_transaction_begin/commit block */
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static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
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{
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uint32_t timeout = GPT_TIMER_MAX;
···
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static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset)
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{
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+
ptimer_transaction_begin(s->timer);
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/* stop timer */
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ptimer_stop(s->timer);
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···
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if (s->freq && (s->cr & GPT_CR_EN)) {
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ptimer_run(s->timer, 1);
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}
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+
ptimer_transaction_commit(s->timer);
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}
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static void imx_gpt_soft_reset(DeviceState *dev)
···
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imx_gpt_soft_reset(DEVICE(s));
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} else {
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/* set our freq, as the source might have changed */
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+
ptimer_transaction_begin(s->timer);
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imx_gpt_set_freq(s);
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if ((oldreg ^ s->cr) & GPT_CR_EN) {
···
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ptimer_stop(s->timer);
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}
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}
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+
ptimer_transaction_commit(s->timer);
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}
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break;
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case 1: /* Prescaler */
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s->pr = value & 0xfff;
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+
ptimer_transaction_begin(s->timer);
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imx_gpt_set_freq(s);
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+
ptimer_transaction_commit(s->timer);
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break;
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case 2: /* SR */
···
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s->ir = value & 0x3f;
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imx_gpt_update_int(s);
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+
ptimer_transaction_begin(s->timer);
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imx_gpt_compute_next_timeout(s, false);
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+
ptimer_transaction_commit(s->timer);
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break;
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case 4: /* OCR1 -- output compare register */
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s->ocr1 = value;
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+
ptimer_transaction_begin(s->timer);
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/* In non-freerun mode, reset count when this register is written */
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if (!(s->cr & GPT_CR_FRR)) {
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s->next_timeout = GPT_TIMER_MAX;
···
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/* compute the new timeout */
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imx_gpt_compute_next_timeout(s, false);
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+
ptimer_transaction_commit(s->timer);
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break;
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···
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s->ocr2 = value;
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/* compute the new timeout */
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+
ptimer_transaction_begin(s->timer);
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imx_gpt_compute_next_timeout(s, false);
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ptimer_transaction_commit(s->timer);
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break;
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···
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s->ocr3 = value;
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/* compute the new timeout */
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+
ptimer_transaction_begin(s->timer);
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imx_gpt_compute_next_timeout(s, false);
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+
ptimer_transaction_commit(s->timer);
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break;
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···
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{
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IMXGPTState *s = IMX_GPT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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QEMUBH *bh;
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
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0x00001000);
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sysbus_init_mmio(sbd, &s->iomem);
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-
bh = qemu_bh_new(imx_gpt_timeout, s);
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-
s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
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+
s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT);
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}
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static void imx_gpt_class_init(ObjectClass *klass, void *data)