jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/timer/imx_epit.c: Switch to transaction-based ptimer API
Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191008171740.9679-18-peter.maydell@linaro.org
+27
-5
+27
-5
hw/timer/imx_epit.c
+27
-5
hw/timer/imx_epit.c
···
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17
#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/misc/imx_ccm.h"
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-
#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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···
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}
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}
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+
/*
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* Must be called from within a ptimer_transaction_begin/commit block
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* for both s->timer_cmp and s->timer_reload.
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*/
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static void imx_epit_set_freq(IMXEPITState *s)
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{
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uint32_t clksrc;
···
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s->lr = EPIT_TIMER_MAX;
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s->cmp = 0;
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s->cnt = 0;
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+
ptimer_transaction_begin(s->timer_cmp);
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+
ptimer_transaction_begin(s->timer_reload);
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/* stop both timers */
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ptimer_stop(s->timer_cmp);
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ptimer_stop(s->timer_reload);
···
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/* if the timer is still enabled, restart it */
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ptimer_run(s->timer_reload, 0);
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}
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ptimer_transaction_commit(s->timer_cmp);
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ptimer_transaction_commit(s->timer_reload);
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}
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static uint32_t imx_epit_update_count(IMXEPITState *s)
···
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return reg_value;
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}
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+
/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
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static void imx_epit_reload_compare_timer(IMXEPITState *s)
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{
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if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
···
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switch (offset >> 2) {
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case 0: /* CR */
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+
ptimer_transaction_begin(s->timer_cmp);
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+
ptimer_transaction_begin(s->timer_reload);
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oldcr = s->cr;
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s->cr = value & 0x03ffffff;
···
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} else {
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ptimer_stop(s->timer_cmp);
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}
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+
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+
ptimer_transaction_commit(s->timer_cmp);
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+
ptimer_transaction_commit(s->timer_reload);
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break;
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case 1: /* SR - ACK*/
···
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case 2: /* LR - set ticks */
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s->lr = value;
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+
ptimer_transaction_begin(s->timer_cmp);
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+
ptimer_transaction_begin(s->timer_reload);
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if (s->cr & CR_RLD) {
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/* Also set the limit if the LRD bit is set */
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/* If IOVW bit is set then set the timer value */
···
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}
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imx_epit_reload_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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ptimer_transaction_commit(s->timer_reload);
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break;
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case 3: /* CMP */
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s->cmp = value;
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+
ptimer_transaction_begin(s->timer_cmp);
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imx_epit_reload_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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break;
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···
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imx_epit_update_int(s);
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}
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+
static void imx_epit_reload(void *opaque)
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{
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/* No action required on rollover of timer_reload */
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}
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+
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static const MemoryRegionOps imx_epit_ops = {
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.read = imx_epit_read,
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.write = imx_epit_write,
···
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{
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IMXEPITState *s = IMX_EPIT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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QEMUBH *bh;
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DPRINTF("\n");
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···
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0x00001000);
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sysbus_init_mmio(sbd, &s->iomem);
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-
s->timer_reload = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT);
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+
s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_DEFAULT);
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-
bh = qemu_bh_new(imx_epit_cmp, s);
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-
s->timer_cmp = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT);
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+
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_DEFAULT);
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}
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static void imx_epit_class_init(ObjectClass *klass, void *data)