jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/riscv: vector floating-point classify instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-41-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
authored by
LIU Zhiwei
and committed by
Alistair Francis
121ddbb3
2a68e9e5
+107
-30
+3
-30
target/riscv/fpu_helper.c
+3
-30
target/riscv/fpu_helper.c
···
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "fpu/softfloat.h"
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#include "internals.h"
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target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
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{
···
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target_ulong helper_fclass_s(uint64_t frs1)
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{
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float32 f = frs1;
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bool sign = float32_is_neg(f);
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if (float32_is_infinity(f)) {
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return sign ? 1 << 0 : 1 << 7;
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} else if (float32_is_zero(f)) {
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return sign ? 1 << 3 : 1 << 4;
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} else if (float32_is_zero_or_denormal(f)) {
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return sign ? 1 << 2 : 1 << 5;
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} else if (float32_is_any_nan(f)) {
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float_status s = { }; /* for snan_bit_is_one */
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return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
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} else {
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return sign ? 1 << 1 : 1 << 6;
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}
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return fclass_s(frs1);
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}
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uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
···
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target_ulong helper_fclass_d(uint64_t frs1)
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{
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float64 f = frs1;
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bool sign = float64_is_neg(f);
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if (float64_is_infinity(f)) {
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return sign ? 1 << 0 : 1 << 7;
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} else if (float64_is_zero(f)) {
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return sign ? 1 << 3 : 1 << 4;
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} else if (float64_is_zero_or_denormal(f)) {
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return sign ? 1 << 2 : 1 << 5;
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} else if (float64_is_any_nan(f)) {
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float_status s = { }; /* for snan_bit_is_one */
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return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
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} else {
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return sign ? 1 << 1 : 1 << 6;
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}
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return fclass_d(frs1);
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}
+4
target/riscv/helper.h
+4
target/riscv/helper.h
···
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DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
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DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
+1
target/riscv/insn32.decode
+1
target/riscv/insn32.decode
···
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vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
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vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
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vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
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vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+3
target/riscv/insn_trans/trans_rvv.inc.c
+3
target/riscv/insn_trans/trans_rvv.inc.c
+5
target/riscv/internals.h
+5
target/riscv/internals.h
+91
target/riscv/vector_helper.c
+91
target/riscv/vector_helper.c
···
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GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
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GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
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GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
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/* Vector Floating-Point Classify Instruction */
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#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
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static void do_##NAME(void *vd, void *vs2, int i) \
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{ \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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*((TD *)vd + HD(i)) = OP(s2); \
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}
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#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \
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void HELPER(NAME)(void *vd, void *v0, void *vs2, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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uint32_t vlmax = vext_maxsz(desc) / ESZ; \
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uint32_t mlen = vext_mlen(desc); \
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uint32_t vm = vext_vm(desc); \
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uint32_t vl = env->vl; \
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uint32_t i; \
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\
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for (i = 0; i < vl; i++) { \
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if (!vm && !vext_elem_mask(v0, mlen, i)) { \
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continue; \
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} \
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do_##NAME(vd, vs2, i); \
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} \
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CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
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}
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target_ulong fclass_h(uint64_t frs1)
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{
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float16 f = frs1;
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bool sign = float16_is_neg(f);
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if (float16_is_infinity(f)) {
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return sign ? 1 << 0 : 1 << 7;
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} else if (float16_is_zero(f)) {
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return sign ? 1 << 3 : 1 << 4;
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} else if (float16_is_zero_or_denormal(f)) {
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return sign ? 1 << 2 : 1 << 5;
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} else if (float16_is_any_nan(f)) {
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float_status s = { }; /* for snan_bit_is_one */
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return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
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} else {
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return sign ? 1 << 1 : 1 << 6;
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}
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}
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target_ulong fclass_s(uint64_t frs1)
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{
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float32 f = frs1;
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bool sign = float32_is_neg(f);
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if (float32_is_infinity(f)) {
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return sign ? 1 << 0 : 1 << 7;
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} else if (float32_is_zero(f)) {
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return sign ? 1 << 3 : 1 << 4;
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} else if (float32_is_zero_or_denormal(f)) {
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return sign ? 1 << 2 : 1 << 5;
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} else if (float32_is_any_nan(f)) {
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float_status s = { }; /* for snan_bit_is_one */
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return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
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} else {
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return sign ? 1 << 1 : 1 << 6;
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}
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}
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target_ulong fclass_d(uint64_t frs1)
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{
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float64 f = frs1;
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bool sign = float64_is_neg(f);
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if (float64_is_infinity(f)) {
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return sign ? 1 << 0 : 1 << 7;
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} else if (float64_is_zero(f)) {
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return sign ? 1 << 3 : 1 << 4;
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} else if (float64_is_zero_or_denormal(f)) {
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return sign ? 1 << 2 : 1 << 5;
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} else if (float64_is_any_nan(f)) {
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float_status s = { }; /* for snan_bit_is_one */
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return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
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} else {
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return sign ? 1 << 1 : 1 << 6;
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}
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}
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RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
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RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
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RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
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GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
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GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
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GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)