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target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-40-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

authored by

LIU Zhiwei and committed by
Alistair Francis 2a68e9e5 1d426b81

+258
+37
target/riscv/helper.h
··· 959 959 DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32) 960 960 DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32) 961 961 DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32) 962 + 963 + DEF_HELPER_6(vmfeq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) 964 + DEF_HELPER_6(vmfeq_vv_w, void, ptr, ptr, ptr, ptr, env, i32) 965 + DEF_HELPER_6(vmfeq_vv_d, void, ptr, ptr, ptr, ptr, env, i32) 966 + DEF_HELPER_6(vmfne_vv_h, void, ptr, ptr, ptr, ptr, env, i32) 967 + DEF_HELPER_6(vmfne_vv_w, void, ptr, ptr, ptr, ptr, env, i32) 968 + DEF_HELPER_6(vmfne_vv_d, void, ptr, ptr, ptr, ptr, env, i32) 969 + DEF_HELPER_6(vmflt_vv_h, void, ptr, ptr, ptr, ptr, env, i32) 970 + DEF_HELPER_6(vmflt_vv_w, void, ptr, ptr, ptr, ptr, env, i32) 971 + DEF_HELPER_6(vmflt_vv_d, void, ptr, ptr, ptr, ptr, env, i32) 972 + DEF_HELPER_6(vmfle_vv_h, void, ptr, ptr, ptr, ptr, env, i32) 973 + DEF_HELPER_6(vmfle_vv_w, void, ptr, ptr, ptr, ptr, env, i32) 974 + DEF_HELPER_6(vmfle_vv_d, void, ptr, ptr, ptr, ptr, env, i32) 975 + DEF_HELPER_6(vmfeq_vf_h, void, ptr, ptr, i64, ptr, env, i32) 976 + DEF_HELPER_6(vmfeq_vf_w, void, ptr, ptr, i64, ptr, env, i32) 977 + DEF_HELPER_6(vmfeq_vf_d, void, ptr, ptr, i64, ptr, env, i32) 978 + DEF_HELPER_6(vmfne_vf_h, void, ptr, ptr, i64, ptr, env, i32) 979 + DEF_HELPER_6(vmfne_vf_w, void, ptr, ptr, i64, ptr, env, i32) 980 + DEF_HELPER_6(vmfne_vf_d, void, ptr, ptr, i64, ptr, env, i32) 981 + DEF_HELPER_6(vmflt_vf_h, void, ptr, ptr, i64, ptr, env, i32) 982 + DEF_HELPER_6(vmflt_vf_w, void, ptr, ptr, i64, ptr, env, i32) 983 + DEF_HELPER_6(vmflt_vf_d, void, ptr, ptr, i64, ptr, env, i32) 984 + DEF_HELPER_6(vmfle_vf_h, void, ptr, ptr, i64, ptr, env, i32) 985 + DEF_HELPER_6(vmfle_vf_w, void, ptr, ptr, i64, ptr, env, i32) 986 + DEF_HELPER_6(vmfle_vf_d, void, ptr, ptr, i64, ptr, env, i32) 987 + DEF_HELPER_6(vmfgt_vf_h, void, ptr, ptr, i64, ptr, env, i32) 988 + DEF_HELPER_6(vmfgt_vf_w, void, ptr, ptr, i64, ptr, env, i32) 989 + DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32) 990 + DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32) 991 + DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32) 992 + DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32) 993 + DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32) 994 + DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32) 995 + DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) 996 + DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) 997 + DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) 998 + DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+12
target/riscv/insn32.decode
··· 502 502 vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm 503 503 vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm 504 504 vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm 505 + vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm 506 + vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm 507 + vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm 508 + vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm 509 + vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm 510 + vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm 511 + vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm 512 + vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm 513 + vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm 514 + vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm 515 + vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm 516 + vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm 505 517 506 518 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 507 519 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+35
target/riscv/insn_trans/trans_rvv.inc.c
··· 2146 2146 GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check) 2147 2147 GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check) 2148 2148 GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) 2149 + 2150 + /* Vector Floating-Point Compare Instructions */ 2151 + static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) 2152 + { 2153 + return (vext_check_isa_ill(s) && 2154 + vext_check_reg(s, a->rs2, false) && 2155 + vext_check_reg(s, a->rs1, false) && 2156 + (s->sew != 0) && 2157 + ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && 2158 + vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || 2159 + (s->lmul == 0))); 2160 + } 2161 + 2162 + GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) 2163 + GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) 2164 + GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) 2165 + GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) 2166 + GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) 2167 + 2168 + static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) 2169 + { 2170 + return (vext_check_isa_ill(s) && 2171 + vext_check_reg(s, a->rs2, false) && 2172 + (s->sew != 0) && 2173 + (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || 2174 + (s->lmul == 0))); 2175 + } 2176 + 2177 + GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) 2178 + GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check) 2179 + GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) 2180 + GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) 2181 + GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) 2182 + GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) 2183 + GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
+174
target/riscv/vector_helper.c
··· 3929 3929 GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2, clearh) 3930 3930 GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl) 3931 3931 GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) 3932 + 3933 + /* Vector Floating-Point Compare Instructions */ 3934 + #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ 3935 + void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 3936 + CPURISCVState *env, uint32_t desc) \ 3937 + { \ 3938 + uint32_t mlen = vext_mlen(desc); \ 3939 + uint32_t vm = vext_vm(desc); \ 3940 + uint32_t vl = env->vl; \ 3941 + uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 3942 + uint32_t i; \ 3943 + \ 3944 + for (i = 0; i < vl; i++) { \ 3945 + ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 3946 + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 3947 + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ 3948 + continue; \ 3949 + } \ 3950 + vext_set_elem_mask(vd, mlen, i, \ 3951 + DO_OP(s2, s1, &env->fp_status)); \ 3952 + } \ 3953 + for (; i < vlmax; i++) { \ 3954 + vext_set_elem_mask(vd, mlen, i, 0); \ 3955 + } \ 3956 + } 3957 + 3958 + static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) 3959 + { 3960 + FloatRelation compare = float16_compare_quiet(a, b, s); 3961 + return compare == float_relation_equal; 3962 + } 3963 + 3964 + GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) 3965 + GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) 3966 + GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) 3967 + 3968 + #define GEN_VEXT_CMP_VF(NAME, ETYPE, H, DO_OP) \ 3969 + void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ 3970 + CPURISCVState *env, uint32_t desc) \ 3971 + { \ 3972 + uint32_t mlen = vext_mlen(desc); \ 3973 + uint32_t vm = vext_vm(desc); \ 3974 + uint32_t vl = env->vl; \ 3975 + uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 3976 + uint32_t i; \ 3977 + \ 3978 + for (i = 0; i < vl; i++) { \ 3979 + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 3980 + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ 3981 + continue; \ 3982 + } \ 3983 + vext_set_elem_mask(vd, mlen, i, \ 3984 + DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ 3985 + } \ 3986 + for (; i < vlmax; i++) { \ 3987 + vext_set_elem_mask(vd, mlen, i, 0); \ 3988 + } \ 3989 + } 3990 + 3991 + GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet) 3992 + GEN_VEXT_CMP_VF(vmfeq_vf_w, uint32_t, H4, float32_eq_quiet) 3993 + GEN_VEXT_CMP_VF(vmfeq_vf_d, uint64_t, H8, float64_eq_quiet) 3994 + 3995 + static bool vmfne16(uint16_t a, uint16_t b, float_status *s) 3996 + { 3997 + FloatRelation compare = float16_compare_quiet(a, b, s); 3998 + return compare != float_relation_equal; 3999 + } 4000 + 4001 + static bool vmfne32(uint32_t a, uint32_t b, float_status *s) 4002 + { 4003 + FloatRelation compare = float32_compare_quiet(a, b, s); 4004 + return compare != float_relation_equal; 4005 + } 4006 + 4007 + static bool vmfne64(uint64_t a, uint64_t b, float_status *s) 4008 + { 4009 + FloatRelation compare = float64_compare_quiet(a, b, s); 4010 + return compare != float_relation_equal; 4011 + } 4012 + 4013 + GEN_VEXT_CMP_VV_ENV(vmfne_vv_h, uint16_t, H2, vmfne16) 4014 + GEN_VEXT_CMP_VV_ENV(vmfne_vv_w, uint32_t, H4, vmfne32) 4015 + GEN_VEXT_CMP_VV_ENV(vmfne_vv_d, uint64_t, H8, vmfne64) 4016 + GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) 4017 + GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) 4018 + GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) 4019 + 4020 + static bool float16_lt(uint16_t a, uint16_t b, float_status *s) 4021 + { 4022 + FloatRelation compare = float16_compare(a, b, s); 4023 + return compare == float_relation_less; 4024 + } 4025 + 4026 + GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) 4027 + GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) 4028 + GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) 4029 + GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) 4030 + GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) 4031 + GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) 4032 + 4033 + static bool float16_le(uint16_t a, uint16_t b, float_status *s) 4034 + { 4035 + FloatRelation compare = float16_compare(a, b, s); 4036 + return compare == float_relation_less || 4037 + compare == float_relation_equal; 4038 + } 4039 + 4040 + GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) 4041 + GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) 4042 + GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) 4043 + GEN_VEXT_CMP_VF(vmfle_vf_h, uint16_t, H2, float16_le) 4044 + GEN_VEXT_CMP_VF(vmfle_vf_w, uint32_t, H4, float32_le) 4045 + GEN_VEXT_CMP_VF(vmfle_vf_d, uint64_t, H8, float64_le) 4046 + 4047 + static bool vmfgt16(uint16_t a, uint16_t b, float_status *s) 4048 + { 4049 + FloatRelation compare = float16_compare(a, b, s); 4050 + return compare == float_relation_greater; 4051 + } 4052 + 4053 + static bool vmfgt32(uint32_t a, uint32_t b, float_status *s) 4054 + { 4055 + FloatRelation compare = float32_compare(a, b, s); 4056 + return compare == float_relation_greater; 4057 + } 4058 + 4059 + static bool vmfgt64(uint64_t a, uint64_t b, float_status *s) 4060 + { 4061 + FloatRelation compare = float64_compare(a, b, s); 4062 + return compare == float_relation_greater; 4063 + } 4064 + 4065 + GEN_VEXT_CMP_VF(vmfgt_vf_h, uint16_t, H2, vmfgt16) 4066 + GEN_VEXT_CMP_VF(vmfgt_vf_w, uint32_t, H4, vmfgt32) 4067 + GEN_VEXT_CMP_VF(vmfgt_vf_d, uint64_t, H8, vmfgt64) 4068 + 4069 + static bool vmfge16(uint16_t a, uint16_t b, float_status *s) 4070 + { 4071 + FloatRelation compare = float16_compare(a, b, s); 4072 + return compare == float_relation_greater || 4073 + compare == float_relation_equal; 4074 + } 4075 + 4076 + static bool vmfge32(uint32_t a, uint32_t b, float_status *s) 4077 + { 4078 + FloatRelation compare = float32_compare(a, b, s); 4079 + return compare == float_relation_greater || 4080 + compare == float_relation_equal; 4081 + } 4082 + 4083 + static bool vmfge64(uint64_t a, uint64_t b, float_status *s) 4084 + { 4085 + FloatRelation compare = float64_compare(a, b, s); 4086 + return compare == float_relation_greater || 4087 + compare == float_relation_equal; 4088 + } 4089 + 4090 + GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) 4091 + GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) 4092 + GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) 4093 + 4094 + static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s) 4095 + { 4096 + FloatRelation compare = float16_compare_quiet(a, b, s); 4097 + return compare == float_relation_unordered; 4098 + } 4099 + 4100 + GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) 4101 + GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) 4102 + GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) 4103 + GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) 4104 + GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) 4105 + GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)