+1 -1

firmware/SOURCES

··· 1369 1369 1370 1370 #ifdef CPU_S5L870X 1371 1371 target/arm/s5l8700/system-s5l8700.c 1372 1372 - target/arm/s5l8700/mmu-s5l8700.S 1372 1372 + target/arm/mmu-arm.S 1373 1373 #ifndef SIMULATOR 1374 1374 #ifndef BOOTLOADER 1375 1375 target/arm/s5l8700/timer-s5l8700.c

+2

firmware/export/as3525.h

··· 20 20 #ifndef __AS3525_H__ 21 21 #define __AS3525_H__ 22 22 23 23 + #define CACHEALIGN_BITS (5) 24 24 + 23 25 #define UART_CHANNELS 1 24 26 25 27

+2

firmware/export/s3c2440.h

··· 21 21 #ifndef __S3C2440_H__ 22 22 #define __S3C2440_H__ 23 23 24 24 + #define CACHEALIGN_BITS (5) 25 25 + 24 26 #define LCD_BUFFER_SIZE (320*240*2) 25 27 #define TTB_SIZE (0x4000) 26 28 /* must be 16Kb (0x4000) aligned */

+26 -12

firmware/target/arm/mmu-arm.S

··· 22 22 #include "cpu.h" 23 23 24 24 /* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */ 25 25 - /* WARNING : assume size of a data cache line == 32 bytes */ 26 25 27 26 #if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260 28 27 /* MMU present but unused */ ··· 40 39 #define USE_MMU 41 40 #define CACHE_SIZE 16 42 41 42 42 + #elif CONFIG_CPU == S5L8701 43 43 + /* MMU not present */ 44 44 + #define CACHE_SIZE 4 45 45 + 43 46 #else 44 47 #error Cache settings unknown for this CPU ! 45 48 46 49 #endif /* CPU specific configuration */ 47 50 48 51 @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ 49 49 - @ assume 64-way set associative separate I/D caches, 32B (2^5) cache line size 52 52 + @ assume 64-way set associative separate I/D caches 50 53 @ CACHE_SIZE = N (kB) = N*2^10 B 51 51 - @ number of lines = N*2^(10-5) = N*2^(5) 54 54 + @ number of lines = N*2^(10-CACHEALIGN_BITS) 52 55 @ Index bits = 6 53 53 - @ Segment loops = N*2^(5-6) = N*2^(-1) = N/2 56 56 + @ Segment loops = N*2^(10-CACHEALIGN_BITS-6) = N*2^(4-CACHEALIGN_BITS) 57 57 + @ Segment loops = N/2^(CACHEALIGN_BITS - 4) 58 58 + @ Segment loops = N/(1<<(CACHEALIGN_BITS - 4)) 54 59 60 60 + #ifdef CACHE_SIZE 61 61 + 62 62 + #if CACHEALIGN_BITS == 4 63 63 + #define INDEX_STEPS CACHE_SIZE 64 64 + #elif CACHEALIGN_BITS == 5 55 65 #define INDEX_STEPS (CACHE_SIZE/2) 66 66 + #endif /* CACHEALIGN_BITS */ 67 67 + 68 68 + @ assume 64-way set associative separate I/D caches (log2(64) == 6) 69 69 + @ Index format: 31:26 = index, M:N = segment, remainder = SBZ 70 70 + @ Segment bits = log2(cache size in bytes / cache line size in byte) - Index bits (== 6) 71 71 + @ N = CACHEALIGN_BITS 72 72 + 73 73 + #endif /* CACHE_SIZE */ 56 74 57 75 58 76 #ifdef USE_MMU ··· 318 336 bne clean_dcache 319 337 mov r1, #0 320 338 #else 321 321 - @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches 322 322 - @ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */ 323 339 mov r1, #0x00000000 @ 324 340 1: @ clean_start @ 325 341 mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index 326 326 - add r0, r1, #0x00000020 @ 342 342 + add r0, r1, #(1<<CACHEALIGN_BITS) 327 343 mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index 328 344 .rept INDEX_STEPS - 2 /* 2 steps already executed */ 329 329 - add r0, r0, #0x00000020 @ 345 345 + add r0, r0, #(1<<CACHEALIGN_BITS) 330 346 mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index 331 347 .endr 332 348 adds r1, r1, #0x04000000 @ will wrap to zero at loop end ··· 351 367 bne invalidate_dcache 352 368 mov r1, #0 353 369 #else 354 354 - @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches 355 355 - @ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */ 356 370 mov r1, #0x00000000 @ 357 371 1: @ inv_start @ 358 372 mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index 359 359 - add r0, r1, #0x00000020 @ 373 373 + add r0, r1, #(1<<CACHEALIGN_BITS) 360 374 mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index 361 375 .rept INDEX_STEPS - 2 /* 2 steps already executed */ 362 362 - add r0, r0, #0x00000020 @ 376 376 + add r0, r0, #(1<<CACHEALIGN_BITS) 363 377 mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index 364 378 .endr 365 379 adds r1, r1, #0x04000000 @ will wrap to zero at loop end

-95

firmware/target/arm/s5l8700/mmu-s5l8700.S

··· 1 1 - /*************************************************************************** 2 2 - * __________ __ ___. 3 3 - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 - * \/ \/ \/ \/ \/ 8 8 - * $Id$ 9 9 - * 10 10 - * Copyright (C) 2006,2007 by Greg White 11 11 - * 12 12 - * This program is free software; you can redistribute it and/or 13 13 - * modify it under the terms of the GNU General Public License 14 14 - * as published by the Free Software Foundation; either version 2 15 15 - * of the License, or (at your option) any later version. 16 16 - * 17 17 - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 - * KIND, either express or implied. 19 19 - * 20 20 - ****************************************************************************/ 21 21 - #include "config.h" 22 22 - #include "cpu.h" 23 23 - 24 24 - /** Cache coherency **/ 25 25 - 26 26 - /* 27 27 - * Cleans entire DCache 28 28 - * void clean_dcache(void); 29 29 - */ 30 30 - .section .icode, "ax", %progbits 31 31 - .align 2 32 32 - .global clean_dcache 33 33 - .type clean_dcache, %function 34 34 - .global cpucache_flush @ Alias 35 35 - clean_dcache: 36 36 - cpucache_flush: 37 37 - @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ 38 38 - mov r1, #0x00000000 @ 39 39 - 1: @ clean_start @ 40 40 - mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index 41 41 - add r0, r1, #0x00000010 @ 42 42 - mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index 43 43 - add r0, r0, #0x00000010 @ 44 44 - mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index 45 45 - add r0, r0, #0x00000010 @ 46 46 - mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index 47 47 - adds r1, r1, #0x04000000 @ will wrap to zero at loop end 48 48 - bne 1b @ clean_start @ 49 49 - mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer 50 50 - bx lr @ 51 51 - .size clean_dcache, .-clean_dcache 52 52 - 53 53 - /* 54 54 - * Invalidate entire DCache 55 55 - * will do writeback 56 56 - * void invalidate_dcache(void); 57 57 - */ 58 58 - .section .icode, "ax", %progbits 59 59 - .align 2 60 60 - .global invalidate_dcache 61 61 - .type invalidate_dcache, %function 62 62 - invalidate_dcache: 63 63 - @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ 64 64 - mov r1, #0x00000000 @ 65 65 - 1: @ inv_start @ 66 66 - mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index 67 67 - add r0, r1, #0x00000010 @ 68 68 - mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index 69 69 - add r0, r0, #0x00000010 @ 70 70 - mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index 71 71 - add r0, r0, #0x00000010 @ 72 72 - mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index 73 73 - adds r1, r1, #0x04000000 @ will wrap to zero at loop end 74 74 - bne 1b @ inv_start @ 75 75 - mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer 76 76 - bx lr @ 77 77 - .size invalidate_dcache, .-invalidate_dcache 78 78 - 79 79 - /* 80 80 - * Invalidate entire ICache and DCache 81 81 - * will do writeback 82 82 - * void invalidate_idcache(void); 83 83 - */ 84 84 - .section .icode, "ax", %progbits 85 85 - .align 2 86 86 - .global invalidate_idcache 87 87 - .type invalidate_idcache, %function 88 88 - .global cpucache_invalidate @ Alias 89 89 - invalidate_idcache: 90 90 - cpucache_invalidate: 91 91 - mov r2, lr @ save lr to r2, call uses r0 and r1 only 92 92 - bl invalidate_dcache @ Clean and invalidate entire DCache 93 93 - mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) 94 94 - mov pc, r2 @ 95 95 - .size invalidate_idcache, .-invalidate_idcache

-43

firmware/target/arm/s5l8700/mmu-target.h

··· 1 1 - /*************************************************************************** 2 2 - * __________ __ ___. 3 3 - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 - * \/ \/ \/ \/ \/ 8 8 - * $Id$ 9 9 - * 10 10 - * Copyright (C) 2006,2007 by Greg White 11 11 - * 12 12 - * This program is free software; you can redistribute it and/or 13 13 - * modify it under the terms of the GNU General Public License 14 14 - * as published by the Free Software Foundation; either version 2 15 15 - * of the License, or (at your option) any later version. 16 16 - * 17 17 - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 - * KIND, either express or implied. 19 19 - * 20 20 - ****************************************************************************/ 21 21 - 22 22 - /* This file MUST be included in your system-target.h file if you want arm 23 23 - * cache coherence functions to be called (I.E. during codec load, etc). 24 24 - */ 25 25 - 26 26 - #ifndef MMU_S5L8700_H 27 27 - #define MMU_S5L8700_H 28 28 - 29 29 - /* Cleans entire DCache */ 30 30 - void clean_dcache(void) ICODE_ATTR; 31 31 - 32 32 - /* Invalidate entire DCache */ 33 33 - /* will do writeback */ 34 34 - void invalidate_dcache(void) ICODE_ATTR; 35 35 - 36 36 - /* Invalidate entire ICache and DCache */ 37 37 - /* will do writeback */ 38 38 - void invalidate_idcache(void) ICODE_ATTR; 39 39 - 40 40 - #define HAVE_CPUCACHE_INVALIDATE 41 41 - #define HAVE_CPUCACHE_FLUSH 42 42 - 43 43 - #endif /* MMU_S5L8700_H */