+5

apps/main.c

··· 36 36 #include "panic.h" 37 37 #include "menu.h" 38 38 #include "usb.h" 39 39 + #include "wifi.h" 39 40 #include "powermgmt.h" 40 41 #if !defined(DX50) && !defined(DX90) 41 42 #include "adc.h" ··· 635 636 audio_init(); 636 637 CHART("<audio_init"); 637 638 talk_announce_voice_invalid(); /* notify user w/ voice prompt if voice file invalid */ 639 639 + 640 640 + #ifdef HAVE_WIFI 641 641 + wifi_init(); 642 642 + #endif 638 643 639 644 /* runtime database has to be initialized after audio_init() */ 640 645 cpu_boost(false);

+10

firmware/SOURCES

··· 536 536 537 537 #endif /* !defined(BOOTLOADER) */ 538 538 539 539 + /* WiFi */ 540 540 + #if !defined(BOOTLOADER) 541 541 + #if (CONFIG_PLATFORM & PLATFORM_NATIVE) 542 542 + #if defined(HAVE_W8686_SPI) 543 543 + drivers/libertas/if_spi.c 544 544 + #endif 545 545 + #endif /* (CONFIG_PLATFORM & PLATFORM_NATIVE) */ 546 546 + #endif /* !defined(BOOTLOADER) */ 547 547 + 539 548 /* CPU Specific - By class then particular chip if applicable */ 540 549 #if defined(CPU_COLDFIRE) 541 550 ··· 1266 1275 target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c 1267 1276 target/arm/tms320dm320/sansa-connect/backlight-sansaconnect.c 1268 1277 target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c 1278 1278 + target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c 1269 1279 target/arm/tms320dm320/dma-dm320.c 1270 1280 #endif /* SANSA_CONNECT */ 1271 1281

+22

firmware/drivers/libertas/firmware/LICENCE.Marvell

··· 1 1 + Copyright © 2019. Marvell International Ltd. All rights reserved. 2 2 + 3 3 + Redistribution and use in binary form is permitted provided that the following 4 4 + conditions are met: 5 5 + 6 6 + 1. Redistributions must reproduce the above copyright notice, this list of 7 7 + conditions and the following disclaimer in the documentation and/or other 8 8 + materials provided with the distribution. 9 9 + 10 10 + 2. Redistribution and use shall be used only with Marvell silicon products. 11 11 + Any other use, reproduction, modification, translation, or compilation of the 12 12 + Software is prohibited. 13 13 + 14 14 + 3. No reverse engineering, decompilation, or disassembly is permitted. 15 15 + 16 16 + TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, THIS SOFTWARE IS PROVIDED 17 17 + “AS IS” WITHOUT WARRANTY OF ANY KIND, INCLUDING, WITHOUT LIMITATION, ANY EXPRESS 18 18 + OR IMPLIED WARRANTIES OF MERCHANTABILITY, ACCURACY, FITNESS OR SUFFICIENCY FOR A 19 19 + PARTICULAR PURPOSE, SATISFACTORY QUALITY, CORRESPONDENCE WITH DESCRIPTION, QUIET 20 20 + ENJOYMENT OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 21 21 + MARVELL, ITS AFFILIATES AND THEIR SUPPLIERS DISCLAIM ANY WARRANTY THAT THE 22 22 + DELIVERABLES WILL OPERATE WITHOUT INTERRUPTION OR BE ERROR-FREE.

firmware/drivers/libertas/firmware/gspi8686_v9.bin

This is a binary file and will not be displayed.

firmware/drivers/libertas/firmware/gspi8686_v9_helper.bin

This is a binary file and will not be displayed.

+674

firmware/drivers/libertas/if_spi.c

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2021 by Tomasz Moń 11 11 + * Ported from Linux libertas driver 12 12 + * Copyright 2008 Analog Devices Inc. 13 13 + * Authors: 14 14 + * Andrey Yurovsky <andrey@cozybit.com> 15 15 + * Colin McCabe <colin@cozybit.com> 16 16 + * Inspired by if_sdio.c, Copyright 2007-2008 Pierre Ossman 17 17 + * 18 18 + * This program is free software; you can redistribute it and/or 19 19 + * modify it under the terms of the GNU General Public License 20 20 + * as published by the Free Software Foundation; either version 2 21 21 + * of the License, or (at your option) any later version. 22 22 + * 23 23 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 24 24 + * KIND, either express or implied. 25 25 + * 26 26 + ****************************************************************************/ 27 27 + 28 28 + #include "config.h" 29 29 + /*#define LOGF_ENABLE*/ 30 30 + #include "logf.h" 31 31 + #include "errno.h" 32 32 + #include "file.h" 33 33 + #include "panic.h" 34 34 + #include "system.h" 35 35 + #include "tick.h" 36 36 + #include <stddef.h> 37 37 + #include "if_spi.h" 38 38 + #include "if_spi_drv.h" 39 39 + 40 40 + #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 41 41 + #define DIV_ROUND_UP(n,d) (((n) + (d) - 1)/(d)) 42 42 + 43 43 + struct if_spi_card 44 44 + { 45 45 + /* The card ID and card revision, as reported by the hardware. */ 46 46 + uint16_t card_id; 47 47 + uint8_t card_rev; 48 48 + 49 49 + unsigned long spu_port_delay; 50 50 + unsigned long spu_reg_delay; 51 51 + 52 52 + uint8_t cmd_buffer[IF_SPI_CMD_BUF_SIZE]; 53 53 + }; 54 54 + 55 55 + #define MODEL_8686 0x0b 56 56 + 57 57 + static const struct 58 58 + { 59 59 + uint16_t model; 60 60 + const char *helper; 61 61 + const char *main; 62 62 + } 63 63 + fw_table[] = 64 64 + { 65 65 + { MODEL_8686, ROCKBOX_DIR"/libertas/gspi8686_v9_helper.bin", ROCKBOX_DIR"/libertas/gspi8686_v9.bin" }, 66 66 + { 0, NULL, NULL } 67 67 + }; 68 68 + 69 69 + 70 70 + /* 71 71 + * SPI Interface Unit Routines 72 72 + * 73 73 + * The SPU sits between the host and the WLAN module. 74 74 + * All communication with the firmware is through SPU transactions. 75 75 + * 76 76 + * First we have to put a SPU register name on the bus. Then we can 77 77 + * either read from or write to that register. 78 78 + * 79 79 + */ 80 80 + 81 81 + static void spu_transaction_init(struct if_spi_card *card) 82 82 + { 83 83 + (void)card; 84 84 + /* Linux delays 400 ns if spu_transaction_finish() was called 85 85 + * within the same jiffy. As we don't have jiffy counter nor 86 86 + * nanosecond delays, simply delay for 1 us. This currently 87 87 + * does not really matter as this driver simply loads firmware. 88 88 + */ 89 89 + udelay(1); 90 90 + libertas_spi_cs(0); /* assert CS */ 91 91 + } 92 92 + 93 93 + static void spu_transaction_finish(struct if_spi_card *card) 94 94 + { 95 95 + (void)card; 96 96 + libertas_spi_cs(1); /* drop CS */ 97 97 + } 98 98 + 99 99 + /* 100 100 + * Write out a byte buffer to an SPI register, 101 101 + * using a series of 16-bit transfers. 102 102 + */ 103 103 + static int spu_write(struct if_spi_card *card, uint16_t reg, const uint8_t *buf, int len) 104 104 + { 105 105 + int err = 0; 106 106 + uint8_t reg_out[2]; 107 107 + 108 108 + /* You must give an even number of bytes to the SPU, even if it 109 109 + * doesn't care about the last one. */ 110 110 + if (len & 0x1) 111 111 + panicf("Odd length in spu_write()"); 112 112 + 113 113 + reg |= IF_SPI_WRITE_OPERATION_MASK; 114 114 + reg_out[0] = (reg & 0x00FF); 115 115 + reg_out[1] = (reg & 0xFF00) >> 8; 116 116 + 117 117 + spu_transaction_init(card); 118 118 + libertas_spi_tx(reg_out, sizeof(reg_out)); 119 119 + libertas_spi_tx(buf, len); 120 120 + spu_transaction_finish(card); 121 121 + return err; 122 122 + } 123 123 + 124 124 + static inline int spu_write_u16(struct if_spi_card *card, uint16_t reg, uint16_t val) 125 125 + { 126 126 + uint8_t buf[2]; 127 127 + buf[0] = (val & 0x00FF); 128 128 + buf[1] = (val & 0xFF00) >> 8; 129 129 + return spu_write(card, reg, buf, sizeof(buf)); 130 130 + } 131 131 + 132 132 + static inline int spu_reg_is_port_reg(uint16_t reg) 133 133 + { 134 134 + switch (reg) 135 135 + { 136 136 + case IF_SPI_IO_RDWRPORT_REG: 137 137 + case IF_SPI_CMD_RDWRPORT_REG: 138 138 + case IF_SPI_DATA_RDWRPORT_REG: 139 139 + return 1; 140 140 + default: 141 141 + return 0; 142 142 + } 143 143 + } 144 144 + 145 145 + static int spu_read(struct if_spi_card *card, uint16_t reg, uint8_t *buf, int len) 146 146 + { 147 147 + unsigned int delay; 148 148 + int err = 0; 149 149 + uint8_t reg_out[2]; 150 150 + 151 151 + /* 152 152 + * You must take an even number of bytes from the SPU, even if you 153 153 + * don't care about the last one. 154 154 + */ 155 155 + if (len & 0x1) 156 156 + panicf("Odd length in spu_read()"); 157 157 + 158 158 + reg |= IF_SPI_READ_OPERATION_MASK; 159 159 + reg_out[0] = (reg & 0x00FF); 160 160 + reg_out[1] = (reg & 0xFF00) >> 8; 161 161 + 162 162 + spu_transaction_init(card); 163 163 + libertas_spi_tx(reg_out, sizeof(reg_out)); 164 164 + 165 165 + delay = spu_reg_is_port_reg(reg) ? card->spu_port_delay : card->spu_reg_delay; 166 166 + /* Busy-wait while the SPU fills the FIFO */ 167 167 + delay = DIV_ROUND_UP((100 + (delay * 10)), 1000); 168 168 + if (delay < 1000) 169 169 + udelay(delay); 170 170 + else 171 171 + mdelay(DIV_ROUND_UP(delay, 1000)); 172 172 + 173 173 + libertas_spi_rx(buf, len); 174 174 + spu_transaction_finish(card); 175 175 + return err; 176 176 + } 177 177 + 178 178 + /* Read 16 bits from an SPI register */ 179 179 + static inline int spu_read_u16(struct if_spi_card *card, uint16_t reg, uint16_t *val) 180 180 + { 181 181 + uint8_t buf[2]; 182 182 + int ret; 183 183 + 184 184 + ret = spu_read(card, reg, buf, sizeof(buf)); 185 185 + if (ret == 0) 186 186 + *val = buf[0] | (buf[1] << 8); 187 187 + 188 188 + return ret; 189 189 + } 190 190 + 191 191 + /* 192 192 + * Read 32 bits from an SPI register. 193 193 + * The low 16 bits are read first. 194 194 + */ 195 195 + static int spu_read_u32(struct if_spi_card *card, uint16_t reg, uint32_t *val) 196 196 + { 197 197 + uint8_t buf[4]; 198 198 + int err; 199 199 + 200 200 + err = spu_read(card, reg, buf, sizeof(buf)); 201 201 + if (!err) 202 202 + *val = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); 203 203 + return err; 204 204 + } 205 205 + 206 206 + /* 207 207 + * Keep reading 16 bits from an SPI register until you get the correct result. 208 208 + * 209 209 + * If mask = 0, the correct result is any non-zero number. 210 210 + * If mask != 0, the correct result is any number where 211 211 + * number & target_mask == target 212 212 + * 213 213 + * Returns -ETIMEDOUT if a five seconds passes without the correct result. 214 214 + */ 215 215 + static int spu_wait_for_u16(struct if_spi_card *card, uint16_t reg, 216 216 + uint16_t target_mask, uint16_t target) 217 217 + { 218 218 + int err; 219 219 + unsigned long timeout = current_tick + 5*HZ; 220 220 + while (1) 221 221 + { 222 222 + uint16_t val; 223 223 + err = spu_read_u16(card, reg, &val); 224 224 + if (err) 225 225 + return err; 226 226 + if (target_mask) 227 227 + { 228 228 + if ((val & target_mask) == target) 229 229 + return 0; 230 230 + } 231 231 + else 232 232 + { 233 233 + if (val) 234 234 + return 0; 235 235 + } 236 236 + udelay(100); 237 237 + if (TIME_AFTER(current_tick, timeout)) 238 238 + { 239 239 + logf("%s: timeout with val=%02x, target_mask=%02x, target=%02x", 240 240 + __func__, val, target_mask, target); 241 241 + return -ETIMEDOUT; 242 242 + } 243 243 + } 244 244 + } 245 245 + 246 246 + /* 247 247 + * Read 16 bits from an SPI register until you receive a specific value. 248 248 + * Returns -ETIMEDOUT if a 4 tries pass without success. 249 249 + */ 250 250 + static int spu_wait_for_u32(struct if_spi_card *card, uint32_t reg, uint32_t target) 251 251 + { 252 252 + int err, try; 253 253 + for (try = 0; try < 4; ++try) 254 254 + { 255 255 + uint32_t val = 0; 256 256 + err = spu_read_u32(card, reg, &val); 257 257 + if (err) 258 258 + return err; 259 259 + if (val == target) 260 260 + return 0; 261 261 + mdelay(100); 262 262 + } 263 263 + return -ETIMEDOUT; 264 264 + } 265 265 + 266 266 + static int spu_set_interrupt_mode(struct if_spi_card *card, 267 267 + int suppress_host_int, 268 268 + int auto_int) 269 269 + { 270 270 + int err = 0; 271 271 + 272 272 + /* 273 273 + * We can suppress a host interrupt by clearing the appropriate 274 274 + * bit in the "host interrupt status mask" register 275 275 + */ 276 276 + if (suppress_host_int) { 277 277 + err = spu_write_u16(card, IF_SPI_HOST_INT_STATUS_MASK_REG, 0); 278 278 + if (err) 279 279 + return err; 280 280 + } else { 281 281 + err = spu_write_u16(card, IF_SPI_HOST_INT_STATUS_MASK_REG, 282 282 + IF_SPI_HISM_TX_DOWNLOAD_RDY | 283 283 + IF_SPI_HISM_RX_UPLOAD_RDY | 284 284 + IF_SPI_HISM_CMD_DOWNLOAD_RDY | 285 285 + IF_SPI_HISM_CARDEVENT | 286 286 + IF_SPI_HISM_CMD_UPLOAD_RDY); 287 287 + if (err) 288 288 + return err; 289 289 + } 290 290 + 291 291 + /* 292 292 + * If auto-interrupts are on, the completion of certain transactions 293 293 + * will trigger an interrupt automatically. If auto-interrupts 294 294 + * are off, we need to set the "Card Interrupt Cause" register to 295 295 + * trigger a card interrupt. 296 296 + */ 297 297 + if (auto_int) { 298 298 + err = spu_write_u16(card, IF_SPI_HOST_INT_CTRL_REG, 299 299 + IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO | 300 300 + IF_SPI_HICT_RX_UPLOAD_OVER_AUTO | 301 301 + IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO | 302 302 + IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO); 303 303 + if (err) 304 304 + return err; 305 305 + } else { 306 306 + err = spu_write_u16(card, IF_SPI_HOST_INT_STATUS_MASK_REG, 0); 307 307 + if (err) 308 308 + return err; 309 309 + } 310 310 + return err; 311 311 + } 312 312 + 313 313 + static int spu_get_chip_revision(struct if_spi_card *card, 314 314 + uint16_t *card_id, uint8_t *card_rev) 315 315 + { 316 316 + int err = 0; 317 317 + uint32_t dev_ctrl; 318 318 + err = spu_read_u32(card, IF_SPI_DEVICEID_CTRL_REG, &dev_ctrl); 319 319 + if (err) 320 320 + return err; 321 321 + *card_id = IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dev_ctrl); 322 322 + *card_rev = IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dev_ctrl); 323 323 + return err; 324 324 + } 325 325 + 326 326 + static int spu_set_bus_mode(struct if_spi_card *card, uint16_t mode) 327 327 + { 328 328 + int err = 0; 329 329 + uint16_t rval; 330 330 + /* set bus mode */ 331 331 + err = spu_write_u16(card, IF_SPI_SPU_BUS_MODE_REG, mode); 332 332 + if (err) 333 333 + return err; 334 334 + /* Check that we were able to read back what we just wrote. */ 335 335 + err = spu_read_u16(card, IF_SPI_SPU_BUS_MODE_REG, &rval); 336 336 + if (err) 337 337 + return err; 338 338 + if ((rval & 0xF) != mode) 339 339 + { 340 340 + logf("Can't read bus mode register"); 341 341 + return -EIO; 342 342 + } 343 343 + return 0; 344 344 + } 345 345 + 346 346 + static int spu_init(struct if_spi_card *card) 347 347 + { 348 348 + int err = 0; 349 349 + uint32_t delay; 350 350 + 351 351 + err = spu_set_bus_mode(card, 352 352 + IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING | 353 353 + IF_SPI_BUS_MODE_DELAY_METHOD_TIMED | 354 354 + IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA); 355 355 + if (err) 356 356 + return err; 357 357 + card->spu_port_delay = 1000; 358 358 + card->spu_reg_delay = 1000; 359 359 + err = spu_read_u32(card, IF_SPI_DELAY_READ_REG, &delay); 360 360 + if (err) 361 361 + return err; 362 362 + card->spu_port_delay = delay & 0x0000ffff; 363 363 + card->spu_reg_delay = (delay & 0xffff0000) >> 16; 364 364 + 365 365 + logf("Initialized SPU unit. " 366 366 + "spu_port_delay=0x%04lx, spu_reg_delay=0x%04lx", 367 367 + card->spu_port_delay, card->spu_reg_delay); 368 368 + return err; 369 369 + } 370 370 + 371 371 + 372 372 + /* 373 373 + * Firmware Loading 374 374 + */ 375 375 + 376 376 + static int if_spi_prog_helper_firmware(struct if_spi_card *card, int fd) 377 377 + { 378 378 + int err = 0; 379 379 + int bytes_read; 380 380 + uint8_t *temp = card->cmd_buffer; 381 381 + 382 382 + err = spu_set_interrupt_mode(card, 1, 0); 383 383 + if (err) 384 384 + goto out; 385 385 + 386 386 + /* Load helper firmware image */ 387 387 + while ((bytes_read = read(fd, temp, HELPER_FW_LOAD_CHUNK_SZ)) > 0) 388 388 + { 389 389 + /* 390 390 + * Scratch pad 1 should contain the number of bytes we 391 391 + * want to download to the firmware 392 392 + */ 393 393 + err = spu_write_u16(card, IF_SPI_SCRATCH_1_REG, 394 394 + HELPER_FW_LOAD_CHUNK_SZ); 395 395 + if (err) 396 396 + goto out; 397 397 + 398 398 + err = spu_wait_for_u16(card, IF_SPI_HOST_INT_STATUS_REG, 399 399 + IF_SPI_HIST_CMD_DOWNLOAD_RDY, 400 400 + IF_SPI_HIST_CMD_DOWNLOAD_RDY); 401 401 + if (err) 402 402 + goto out; 403 403 + 404 404 + /* 405 405 + * Feed the data into the command read/write port reg 406 406 + * in chunks of 64 bytes 407 407 + */ 408 408 + memset(temp + bytes_read, 0, HELPER_FW_LOAD_CHUNK_SZ - bytes_read); 409 409 + mdelay(10); 410 410 + err = spu_write(card, IF_SPI_CMD_RDWRPORT_REG, 411 411 + temp, HELPER_FW_LOAD_CHUNK_SZ); 412 412 + if (err) 413 413 + goto out; 414 414 + 415 415 + /* Interrupt the boot code */ 416 416 + err = spu_write_u16(card, IF_SPI_HOST_INT_STATUS_REG, 0); 417 417 + if (err) 418 418 + goto out; 419 419 + err = spu_write_u16(card, IF_SPI_CARD_INT_CAUSE_REG, 420 420 + IF_SPI_CIC_CMD_DOWNLOAD_OVER); 421 421 + if (err) 422 422 + goto out; 423 423 + } 424 424 + 425 425 + /* 426 426 + * Once the helper / single stage firmware download is complete, 427 427 + * write 0 to scratch pad 1 and interrupt the 428 428 + * bootloader. This completes the helper download. 429 429 + */ 430 430 + err = spu_write_u16(card, IF_SPI_SCRATCH_1_REG, FIRMWARE_DNLD_OK); 431 431 + if (err) 432 432 + goto out; 433 433 + err = spu_write_u16(card, IF_SPI_HOST_INT_STATUS_REG, 0); 434 434 + if (err) 435 435 + goto out; 436 436 + err = spu_write_u16(card, IF_SPI_CARD_INT_CAUSE_REG, 437 437 + IF_SPI_CIC_CMD_DOWNLOAD_OVER); 438 438 + out: 439 439 + if (err) 440 440 + logf("failed to load helper firmware (err=%d)", err); 441 441 + 442 442 + return err; 443 443 + } 444 444 + 445 445 + /* 446 446 + * Returns the length of the next packet the firmware expects us to send. 447 447 + * Sets crc_err if the previous transfer had a CRC error. 448 448 + */ 449 449 + static int if_spi_prog_main_firmware_check_len(struct if_spi_card *card, 450 450 + int *crc_err) 451 451 + { 452 452 + uint16_t len; 453 453 + int err = 0; 454 454 + 455 455 + /* 456 456 + * wait until the host interrupt status register indicates 457 457 + * that we are ready to download 458 458 + */ 459 459 + err = spu_wait_for_u16(card, IF_SPI_HOST_INT_STATUS_REG, 460 460 + IF_SPI_HIST_CMD_DOWNLOAD_RDY, 461 461 + IF_SPI_HIST_CMD_DOWNLOAD_RDY); 462 462 + if (err) 463 463 + { 464 464 + logf("timed out waiting for host_int_status"); 465 465 + return err; 466 466 + } 467 467 + 468 468 + /* Ask the device how many bytes of firmware it wants. */ 469 469 + err = spu_read_u16(card, IF_SPI_SCRATCH_1_REG, &len); 470 470 + if (err) 471 471 + return err; 472 472 + 473 473 + if (len > IF_SPI_CMD_BUF_SIZE) 474 474 + { 475 475 + logf("firmware load device requested a larger transfer than we are prepared to handle (len = %d)", 476 476 + len); 477 477 + return -EIO; 478 478 + } 479 479 + if (len & 0x1) { 480 480 + logf("%s: crc error", __func__); 481 481 + len &= ~0x1; 482 482 + *crc_err = 1; 483 483 + } else 484 484 + *crc_err = 0; 485 485 + 486 486 + return len; 487 487 + } 488 488 + 489 489 + static int if_spi_prog_main_firmware(struct if_spi_card *card, int fd) 490 490 + { 491 491 + int len; 492 492 + int bytes_read = 0, crc_err = 0, err = 0; 493 493 + uint16_t num_crc_errs; 494 494 + 495 495 + err = spu_set_interrupt_mode(card, 1, 0); 496 496 + if (err) 497 497 + goto out; 498 498 + 499 499 + err = spu_wait_for_u16(card, IF_SPI_SCRATCH_1_REG, 0, 0); 500 500 + if (err) 501 501 + { 502 502 + logf("%s: timed out waiting for initial scratch reg = 0", __func__); 503 503 + goto out; 504 504 + } 505 505 + 506 506 + num_crc_errs = 0; 507 507 + while ((len = if_spi_prog_main_firmware_check_len(card, &crc_err))) 508 508 + { 509 509 + if (len < 0) 510 510 + { 511 511 + err = len; 512 512 + goto out; 513 513 + } 514 514 + if (crc_err) 515 515 + { 516 516 + /* Previous transfer failed. */ 517 517 + if (++num_crc_errs > MAX_MAIN_FW_LOAD_CRC_ERR) 518 518 + { 519 519 + logf("Too many CRC errors encountered in firmware load."); 520 520 + err = -EIO; 521 521 + goto out; 522 522 + } 523 523 + 524 524 + /* Rewind so we read back the data from previous transfer */ 525 525 + lseek(fd, -bytes_read, SEEK_CUR); 526 526 + } 527 527 + 528 528 + bytes_read = read(fd, card->cmd_buffer, len); 529 529 + if (bytes_read < 0) 530 530 + { 531 531 + /* 532 532 + * If there are no more bytes left, we would normally 533 533 + * expect to have terminated with len = 0 534 534 + */ 535 535 + logf("Firmware load wants more bytes than we have to offer."); 536 536 + break; 537 537 + } 538 538 + else if (bytes_read < len) 539 539 + { 540 540 + memset(card->cmd_buffer + bytes_read, 0, len - bytes_read); 541 541 + } 542 542 + 543 543 + err = spu_write_u16(card, IF_SPI_HOST_INT_STATUS_REG, 0); 544 544 + if (err) 545 545 + goto out; 546 546 + err = spu_write(card, IF_SPI_CMD_RDWRPORT_REG, card->cmd_buffer, len); 547 547 + if (err) 548 548 + goto out; 549 549 + err = spu_write_u16(card, IF_SPI_CARD_INT_CAUSE_REG, 550 550 + IF_SPI_CIC_CMD_DOWNLOAD_OVER); 551 551 + if (err) 552 552 + goto out; 553 553 + } 554 554 + if (read(fd, card->cmd_buffer, IF_SPI_CMD_BUF_SIZE) > 0) 555 555 + { 556 556 + logf("firmware load wants fewer bytes than we have to offer"); 557 557 + } 558 558 + 559 559 + /* Confirm firmware download */ 560 560 + err = spu_wait_for_u32(card, IF_SPI_SCRATCH_4_REG, 561 561 + SUCCESSFUL_FW_DOWNLOAD_MAGIC); 562 562 + if (err) 563 563 + { 564 564 + logf("failed to confirm the firmware download"); 565 565 + goto out; 566 566 + } 567 567 + 568 568 + out: 569 569 + if (err) 570 570 + logf("failed to load firmware (err=%d)", err); 571 571 + 572 572 + return err; 573 573 + } 574 574 + 575 575 + static int if_spi_init_card(struct if_spi_card *card) 576 576 + { 577 577 + int err; 578 578 + size_t i; 579 579 + uint32_t scratch; 580 580 + int fd; 581 581 + 582 582 + err = spu_init(card); 583 583 + if (err) 584 584 + goto out; 585 585 + err = spu_get_chip_revision(card, &card->card_id, &card->card_rev); 586 586 + if (err) 587 587 + goto out; 588 588 + 589 589 + err = spu_read_u32(card, IF_SPI_SCRATCH_4_REG, &scratch); 590 590 + if (err) 591 591 + goto out; 592 592 + if (scratch == SUCCESSFUL_FW_DOWNLOAD_MAGIC) 593 593 + logf("Firmware is already loaded for Marvell WLAN 802.11 adapter"); 594 594 + else { 595 595 + /* Check if we support this card */ 596 596 + for (i = 0; i < ARRAY_SIZE(fw_table); i++) { 597 597 + if (card->card_id == fw_table[i].model) 598 598 + break; 599 599 + } 600 600 + if (i == ARRAY_SIZE(fw_table)) { 601 601 + logf("Unsupported chip_id: 0x%02x", card->card_id); 602 602 + err = -ENODEV; 603 603 + goto out; 604 604 + } 605 605 + 606 606 + logf("Initializing FW for Marvell WLAN 802.11 adapter " 607 607 + "(chip_id = 0x%04x, chip_rev = 0x%02x)", 608 608 + card->card_id, card->card_rev); 609 609 + 610 610 + fd = open(fw_table[i].helper, O_RDONLY); 611 611 + if (fd >= 0) 612 612 + { 613 613 + err = if_spi_prog_helper_firmware(card, fd); 614 614 + close(fd); 615 615 + if (err) 616 616 + goto out; 617 617 + } 618 618 + else 619 619 + { 620 620 + logf("failed to find firmware helper (%s)", fw_table[i].helper); 621 621 + err = -ENOENT; 622 622 + goto out; 623 623 + } 624 624 + 625 625 + fd = open(fw_table[i].main, O_RDONLY); 626 626 + if (fd >= 0) 627 627 + { 628 628 + err = if_spi_prog_main_firmware(card, fd); 629 629 + close(fd); 630 630 + if (err) 631 631 + goto out; 632 632 + } 633 633 + else 634 634 + { 635 635 + logf("failed to find firmware (%s)", fw_table[i].main); 636 636 + err = -ENOENT; 637 637 + goto out; 638 638 + } 639 639 + 640 640 + logf("loaded FW for Marvell WLAN 802.11 adapter"); 641 641 + } 642 642 + 643 643 + err = spu_set_interrupt_mode(card, 0, 1); 644 644 + if (err) 645 645 + goto out; 646 646 + 647 647 + out: 648 648 + return err; 649 649 + } 650 650 + 651 651 + void wifi_init(void) INIT_ATTR 652 652 + { 653 653 + #if 0 654 654 + static struct if_spi_card card; 655 655 + libertas_spi_init(); 656 656 + libertas_spi_pd(1); 657 657 + libertas_spi_reset(1); 658 658 + mdelay(100); 659 659 + if (!if_spi_init_card(&card)) 660 660 + { 661 661 + /* TODO: Configure card and enter deep sleep */ 662 662 + } 663 663 + else 664 664 + #else 665 665 + libertas_spi_init(); 666 666 + (void)if_spi_init_card; 667 667 + #endif 668 668 + { 669 669 + /* Keep the lines in lowest power configuration */ 670 670 + libertas_spi_pd(0); 671 671 + libertas_spi_reset(1); 672 672 + libertas_spi_cs(1); 673 673 + } 674 674 + }

+215

firmware/drivers/libertas/if_spi.h

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2021 by Tomasz Moń 11 11 + * Ported from Linux libertas driver 12 12 + * Copyright 2008 Analog Devices Inc. 13 13 + * Authors: 14 14 + * Andrey Yurovsky <andrey@cozybit.com> 15 15 + * Colin McCabe <colin@cozybit.com> 16 16 + * 17 17 + * This program is free software; you can redistribute it and/or 18 18 + * modify it under the terms of the GNU General Public License 19 19 + * as published by the Free Software Foundation; either version 2 20 20 + * of the License, or (at your option) any later version. 21 21 + * 22 22 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 23 23 + * KIND, either express or implied. 24 24 + * 25 25 + ****************************************************************************/ 26 26 + 27 27 + #ifndef _LBS_IF_SPI_H_ 28 28 + #define _LBS_IF_SPI_H_ 29 29 + 30 30 + #define IPFIELD_ALIGN_OFFSET 2 31 31 + #define IF_SPI_CMD_BUF_SIZE 2400 32 32 + 33 33 + /***************** Firmware *****************/ 34 34 + 35 35 + #define IF_SPI_FW_NAME_MAX 30 36 36 + 37 37 + #define MAX_MAIN_FW_LOAD_CRC_ERR 10 38 38 + 39 39 + /* Chunk size when loading the helper firmware */ 40 40 + #define HELPER_FW_LOAD_CHUNK_SZ 64 41 41 + 42 42 + /* Value to write to indicate end of helper firmware dnld */ 43 43 + #define FIRMWARE_DNLD_OK 0x0000 44 44 + 45 45 + /* Value to check once the main firmware is downloaded */ 46 46 + #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888 47 47 + 48 48 + /***************** SPI Interface Unit *****************/ 49 49 + /* Masks used in SPI register read/write operations */ 50 50 + #define IF_SPI_READ_OPERATION_MASK 0x0 51 51 + #define IF_SPI_WRITE_OPERATION_MASK 0x8000 52 52 + 53 53 + /* SPI register offsets. 4-byte aligned. */ 54 54 + #define IF_SPI_DEVICEID_CTRL_REG 0x00 /* DeviceID controller reg */ 55 55 + #define IF_SPI_IO_READBASE_REG 0x04 /* Read I/O base reg */ 56 56 + #define IF_SPI_IO_WRITEBASE_REG 0x08 /* Write I/O base reg */ 57 57 + #define IF_SPI_IO_RDWRPORT_REG 0x0C /* Read/Write I/O port reg */ 58 58 + 59 59 + #define IF_SPI_CMD_READBASE_REG 0x10 /* Read command base reg */ 60 60 + #define IF_SPI_CMD_WRITEBASE_REG 0x14 /* Write command base reg */ 61 61 + #define IF_SPI_CMD_RDWRPORT_REG 0x18 /* Read/Write command port reg */ 62 62 + 63 63 + #define IF_SPI_DATA_READBASE_REG 0x1C /* Read data base reg */ 64 64 + #define IF_SPI_DATA_WRITEBASE_REG 0x20 /* Write data base reg */ 65 65 + #define IF_SPI_DATA_RDWRPORT_REG 0x24 /* Read/Write data port reg */ 66 66 + 67 67 + #define IF_SPI_SCRATCH_1_REG 0x28 /* Scratch reg 1 */ 68 68 + #define IF_SPI_SCRATCH_2_REG 0x2C /* Scratch reg 2 */ 69 69 + #define IF_SPI_SCRATCH_3_REG 0x30 /* Scratch reg 3 */ 70 70 + #define IF_SPI_SCRATCH_4_REG 0x34 /* Scratch reg 4 */ 71 71 + 72 72 + #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */ 73 73 + #define IF_SPI_TX_FRAME_STATUS_REG 0x3C /* Tx frame status reg */ 74 74 + 75 75 + #define IF_SPI_HOST_INT_CTRL_REG 0x40 /* Host interrupt controller reg */ 76 76 + 77 77 + #define IF_SPI_CARD_INT_CAUSE_REG 0x44 /* Card interrupt cause reg */ 78 78 + #define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interrupt status reg */ 79 79 + #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */ 80 80 + #define IF_SPI_CARD_INT_STATUS_MASK_REG 0x50 /* Card interrupt status mask */ 81 81 + 82 82 + #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */ 83 83 + 84 84 + #define IF_SPI_HOST_INT_CAUSE_REG 0x58 /* Host interrupt cause reg */ 85 85 + #define IF_SPI_HOST_INT_STATUS_REG 0x5C /* Host interrupt status reg */ 86 86 + #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */ 87 87 + #define IF_SPI_HOST_INT_STATUS_MASK_REG 0x64 /* Host interrupt status mask */ 88 88 + #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */ 89 89 + 90 90 + #define IF_SPI_DELAY_READ_REG 0x6C /* Delay read reg */ 91 91 + #define IF_SPI_SPU_BUS_MODE_REG 0x70 /* SPU BUS mode reg */ 92 92 + 93 93 + /***************** IF_SPI_DEVICEID_CTRL_REG *****************/ 94 94 + #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16) 95 95 + #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff) 96 96 + 97 97 + /***************** IF_SPI_HOST_INT_CTRL_REG *****************/ 98 98 + /* Host Interrupt Control bit : Wake up */ 99 99 + #define IF_SPI_HICT_WAKE_UP (1<<0) 100 100 + /* Host Interrupt Control bit : WLAN ready */ 101 101 + #define IF_SPI_HICT_WLAN_READY (1<<1) 102 102 + /*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY (1<<2) */ 103 103 + /*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY (1<<3) */ 104 104 + /*#define IF_SPI_HICT_IRQSRC_WLAN (1<<4) */ 105 105 + /* Host Interrupt Control bit : Tx auto download */ 106 106 + #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO (1<<5) 107 107 + /* Host Interrupt Control bit : Rx auto upload */ 108 108 + #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO (1<<6) 109 109 + /* Host Interrupt Control bit : Command auto download */ 110 110 + #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO (1<<7) 111 111 + /* Host Interrupt Control bit : Command auto upload */ 112 112 + #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO (1<<8) 113 113 + 114 114 + /***************** IF_SPI_CARD_INT_CAUSE_REG *****************/ 115 115 + /* Card Interrupt Case bit : Tx download over */ 116 116 + #define IF_SPI_CIC_TX_DOWNLOAD_OVER (1<<0) 117 117 + /* Card Interrupt Case bit : Rx upload over */ 118 118 + #define IF_SPI_CIC_RX_UPLOAD_OVER (1<<1) 119 119 + /* Card Interrupt Case bit : Command download over */ 120 120 + #define IF_SPI_CIC_CMD_DOWNLOAD_OVER (1<<2) 121 121 + /* Card Interrupt Case bit : Host event */ 122 122 + #define IF_SPI_CIC_HOST_EVENT (1<<3) 123 123 + /* Card Interrupt Case bit : Command upload over */ 124 124 + #define IF_SPI_CIC_CMD_UPLOAD_OVER (1<<4) 125 125 + /* Card Interrupt Case bit : Power down */ 126 126 + #define IF_SPI_CIC_POWER_DOWN (1<<5) 127 127 + 128 128 + /***************** IF_SPI_CARD_INT_STATUS_REG *****************/ 129 129 + #define IF_SPI_CIS_TX_DOWNLOAD_OVER (1<<0) 130 130 + #define IF_SPI_CIS_RX_UPLOAD_OVER (1<<1) 131 131 + #define IF_SPI_CIS_CMD_DOWNLOAD_OVER (1<<2) 132 132 + #define IF_SPI_CIS_HOST_EVENT (1<<3) 133 133 + #define IF_SPI_CIS_CMD_UPLOAD_OVER (1<<4) 134 134 + #define IF_SPI_CIS_POWER_DOWN (1<<5) 135 135 + 136 136 + /***************** IF_SPI_HOST_INT_CAUSE_REG *****************/ 137 137 + #define IF_SPI_HICU_TX_DOWNLOAD_RDY (1<<0) 138 138 + #define IF_SPI_HICU_RX_UPLOAD_RDY (1<<1) 139 139 + #define IF_SPI_HICU_CMD_DOWNLOAD_RDY (1<<2) 140 140 + #define IF_SPI_HICU_CARD_EVENT (1<<3) 141 141 + #define IF_SPI_HICU_CMD_UPLOAD_RDY (1<<4) 142 142 + #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW (1<<5) 143 143 + #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW (1<<6) 144 144 + #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW (1<<7) 145 145 + #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW (1<<8) 146 146 + #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW (1<<9) 147 147 + #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW (1<<10) 148 148 + 149 149 + /***************** IF_SPI_HOST_INT_STATUS_REG *****************/ 150 150 + /* Host Interrupt Status bit : Tx download ready */ 151 151 + #define IF_SPI_HIST_TX_DOWNLOAD_RDY (1<<0) 152 152 + /* Host Interrupt Status bit : Rx upload ready */ 153 153 + #define IF_SPI_HIST_RX_UPLOAD_RDY (1<<1) 154 154 + /* Host Interrupt Status bit : Command download ready */ 155 155 + #define IF_SPI_HIST_CMD_DOWNLOAD_RDY (1<<2) 156 156 + /* Host Interrupt Status bit : Card event */ 157 157 + #define IF_SPI_HIST_CARD_EVENT (1<<3) 158 158 + /* Host Interrupt Status bit : Command upload ready */ 159 159 + #define IF_SPI_HIST_CMD_UPLOAD_RDY (1<<4) 160 160 + /* Host Interrupt Status bit : I/O write FIFO overflow */ 161 161 + #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW (1<<5) 162 162 + /* Host Interrupt Status bit : I/O read FIFO underflow */ 163 163 + #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW (1<<6) 164 164 + /* Host Interrupt Status bit : Data write FIFO overflow */ 165 165 + #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW (1<<7) 166 166 + /* Host Interrupt Status bit : Data read FIFO underflow */ 167 167 + #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW (1<<8) 168 168 + /* Host Interrupt Status bit : Command write FIFO overflow */ 169 169 + #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW (1<<9) 170 170 + /* Host Interrupt Status bit : Command read FIFO underflow */ 171 171 + #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW (1<<10) 172 172 + 173 173 + /***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/ 174 174 + /* Host Interrupt Status Mask bit : Tx download ready */ 175 175 + #define IF_SPI_HISM_TX_DOWNLOAD_RDY (1<<0) 176 176 + /* Host Interrupt Status Mask bit : Rx upload ready */ 177 177 + #define IF_SPI_HISM_RX_UPLOAD_RDY (1<<1) 178 178 + /* Host Interrupt Status Mask bit : Command download ready */ 179 179 + #define IF_SPI_HISM_CMD_DOWNLOAD_RDY (1<<2) 180 180 + /* Host Interrupt Status Mask bit : Card event */ 181 181 + #define IF_SPI_HISM_CARDEVENT (1<<3) 182 182 + /* Host Interrupt Status Mask bit : Command upload ready */ 183 183 + #define IF_SPI_HISM_CMD_UPLOAD_RDY (1<<4) 184 184 + /* Host Interrupt Status Mask bit : I/O write FIFO overflow */ 185 185 + #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW (1<<5) 186 186 + /* Host Interrupt Status Mask bit : I/O read FIFO underflow */ 187 187 + #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW (1<<6) 188 188 + /* Host Interrupt Status Mask bit : Data write FIFO overflow */ 189 189 + #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW (1<<7) 190 190 + /* Host Interrupt Status Mask bit : Data write FIFO underflow */ 191 191 + #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW (1<<8) 192 192 + /* Host Interrupt Status Mask bit : Command write FIFO overflow */ 193 193 + #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW (1<<9) 194 194 + /* Host Interrupt Status Mask bit : Command write FIFO underflow */ 195 195 + #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW (1<<10) 196 196 + 197 197 + /***************** IF_SPI_SPU_BUS_MODE_REG *****************/ 198 198 + /* SCK edge on which the WLAN module outputs data on MISO */ 199 199 + #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8 200 200 + #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0 201 201 + 202 202 + /* In a SPU read operation, there is a delay between writing the SPU 203 203 + * register name and getting back data from the WLAN module. 204 204 + * This can be specified in terms of nanoseconds or in terms of dummy 205 205 + * clock cycles which the master must output before receiving a response. */ 206 206 + #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4 207 207 + #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0 208 208 + 209 209 + /* Some different modes of SPI operation */ 210 210 + #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00 211 211 + #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01 212 212 + #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02 213 213 + #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03 214 214 + 215 215 + #endif

+34

firmware/drivers/libertas/if_spi_drv.h

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2021 by Tomasz Moń 11 11 + * 12 12 + * This program is free software; you can redistribute it and/or 13 13 + * modify it under the terms of the GNU General Public License 14 14 + * as published by the Free Software Foundation; either version 2 15 15 + * of the License, or (at your option) any later version. 16 16 + * 17 17 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 + * KIND, either express or implied. 19 19 + * 20 20 + ****************************************************************************/ 21 21 + 22 22 + #ifndef LIBERTAS_IF_SPI_DRV 23 23 + #define LIBERTAS_IF_SPI_DRV 24 24 + 25 25 + #include <stdint.h> 26 26 + 27 27 + void libertas_spi_init(void); 28 28 + void libertas_spi_reset(int high); 29 29 + void libertas_spi_pd(int high); 30 30 + void libertas_spi_cs(int high); 31 31 + void libertas_spi_tx(const uint8_t *buf, int len); 32 32 + void libertas_spi_rx(uint8_t *buf, int len); 33 33 + 34 34 + #endif

+6

firmware/export/config/sansaconnect.h

··· 135 135 /* Define this if you have a software controlled poweroff */ 136 136 #define HAVE_SW_POWEROFF 137 137 138 138 + #ifndef BOOTLOADER 139 139 + #define HAVE_WIFI 140 140 + /* define this if the target has Marvell 88W8686 interfaced over SPI */ 141 141 + #define HAVE_W8686_SPI 142 142 + #endif 143 143 + 138 144 /* The number of bytes reserved for loadable codecs */ 139 145 #define CODEC_SIZE 0x100000 140 146

+29

firmware/export/wifi.h

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2021 by Tomasz Moń 11 11 + * 12 12 + * This program is free software; you can redistribute it and/or 13 13 + * modify it under the terms of the GNU General Public License 14 14 + * as published by the Free Software Foundation; either version 2 15 15 + * of the License, or (at your option) any later version. 16 16 + * 17 17 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 + * KIND, either express or implied. 19 19 + * 20 20 + ****************************************************************************/ 21 21 + 22 22 + #ifndef WIFI_H 23 23 + #define WIFI_H 24 24 + 25 25 + #include "config.h" 26 26 + 27 27 + void wifi_init(void) INIT_ATTR; 28 28 + 29 29 + #endif

+8 -2

firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c

··· 75 75 #define CMD_WHEEL_EN 0xD0 76 76 #define CMD_SET_INTCHRG 0xD1 77 77 #define CMD_GET_INTCHRG 0xD2 78 78 - #define CMD_UNKNOWN_D3 0xD3 78 78 + #define CMD_WIFI_PD 0xD3 79 79 #define CMD_UNKNOWN_D4 0xD4 80 80 #define CMD_UNKNOWN_D5 0xD5 81 81 #define CMD_UNKNOWN_D6 0xD6 ··· 315 315 case CMD_WHEEL_EN: return 1; 316 316 case CMD_SET_INTCHRG: return 1; 317 317 case CMD_GET_INTCHRG: return 1; 318 318 - case CMD_UNKNOWN_D3: return 1; 318 318 + case CMD_WIFI_PD: return 1; 319 319 case CMD_UNKNOWN_D4: return 1; 320 320 case CMD_UNKNOWN_D5: return 2; 321 321 case CMD_UNKNOWN_D6: return 2; ··· 534 534 { 535 535 uint8_t enable = 0x01; 536 536 avr_execute_command(CMD_SET_INTCHRG, &enable, sizeof(enable)); 537 537 + } 538 538 + 539 539 + void avr_hid_wifi_pd(int high) 540 540 + { 541 541 + uint8_t state = high ? 0x01 : 0x00; 542 542 + avr_execute_command(CMD_WIFI_PD, &state, sizeof(state)); 537 543 } 538 544 539 545 static void avr_hid_lcm_power(uint8_t parameter)

+2

firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.h

··· 28 28 29 29 void avr_hid_enable_charger(void); 30 30 31 31 + void avr_hid_wifi_pd(int high); 32 32 + 31 33 void avr_hid_lcm_sleep(void); 32 34 void avr_hid_lcm_wake(void); 33 35 void avr_hid_lcm_power_on(void);

+130

firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2021 by Tomasz Moń 11 11 + * 12 12 + * This program is free software; you can redistribute it and/or 13 13 + * modify it under the terms of the GNU General Public License 14 14 + * as published by the Free Software Foundation; either version 2 15 15 + * of the License, or (at your option) any later version. 16 16 + * 17 17 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 + * KIND, either express or implied. 19 19 + * 20 20 + ****************************************************************************/ 21 21 + 22 22 + #include "kernel.h" 23 23 + #include "system.h" 24 24 + #include "spi.h" 25 25 + #include "avr-sansaconnect.h" 26 26 + #include "libertas/if_spi_drv.h" 27 27 + 28 28 + #define IO_SERIAL0_XMIT (0x100) 29 29 + 30 30 + void libertas_spi_init(void) 31 31 + { 32 32 + IO_GIO_DIR0 &= ~((1 << 4) /* CS */ | (1 << 3) /* reset */); 33 33 + libertas_spi_reset(1); 34 34 + libertas_spi_cs(1); 35 35 + 36 36 + /* Enable the clock */ 37 37 + bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0); 38 38 + 39 39 + /* Disable transmitter */ 40 40 + IO_SERIAL0_TX_ENABLE = 0x0001; 41 41 + 42 42 + /* SELSDEN = 0, SLVEN = 0, SIOCLR = 0, SCLKM = 1, MSB = 1, MSSEL = 0, 43 43 + * RATE = 2 -> 15MHz 44 44 + */ 45 45 + IO_SERIAL0_MODE = 0x0601; 46 46 + 47 47 + /* Disable the clock */ 48 48 + bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0); 49 49 + 50 50 + /* Make sure the SPI clock is not inverted */ 51 51 + bitclr16(&IO_CLK_INV, CLK_INV_SIF0); 52 52 + } 53 53 + 54 54 + void libertas_spi_reset(int high) 55 55 + { 56 56 + if (high) 57 57 + { 58 58 + IO_GIO_BITSET0 = (1 << 3); 59 59 + } 60 60 + else 61 61 + { 62 62 + IO_GIO_BITCLR0 = (1 << 3); 63 63 + } 64 64 + } 65 65 + 66 66 + void libertas_spi_pd(int high) 67 67 + { 68 68 + avr_hid_wifi_pd(high); 69 69 + } 70 70 + 71 71 + void libertas_spi_cs(int high) 72 72 + { 73 73 + if (high) 74 74 + { 75 75 + IO_GIO_BITSET0 = (1 << 4); 76 76 + } 77 77 + else 78 78 + { 79 79 + IO_GIO_BITCLR0 = (1 << 4); 80 80 + } 81 81 + } 82 82 + 83 83 + void libertas_spi_tx(const uint8_t *buf, int len) 84 84 + { 85 85 + /* Enable the clock */ 86 86 + bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0); 87 87 + IO_SERIAL0_TX_ENABLE = 0x0001; 88 88 + 89 89 + while (len > 0) 90 90 + { 91 91 + IO_SERIAL0_TX_DATA = *(buf + 1); 92 92 + while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT) {}; 93 93 + IO_SERIAL0_TX_DATA = *buf; 94 94 + while (IO_SERIAL0_RX_DATA & IO_SERIAL0_XMIT) {}; 95 95 + 96 96 + buf += 2; 97 97 + len -= 2; 98 98 + } 99 99 + 100 100 + IO_SERIAL0_TX_ENABLE = 0x0000; 101 101 + 102 102 + /* Disable the clock */ 103 103 + bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0); 104 104 + } 105 105 + 106 106 + void libertas_spi_rx(uint8_t *buf, int len) 107 107 + { 108 108 + /* Enable the clock */ 109 109 + bitset16(&IO_CLK_MOD2, CLK_MOD2_SIF0); 110 110 + IO_SERIAL0_TX_ENABLE = 0x0001; 111 111 + 112 112 + while (len > 0) 113 113 + { 114 114 + uint16_t data; 115 115 + IO_SERIAL0_TX_DATA = 0; 116 116 + while ((data = IO_SERIAL0_RX_DATA) & IO_SERIAL0_XMIT) {}; 117 117 + *(buf + 1) = data & 0xFF; 118 118 + IO_SERIAL0_TX_DATA = 0; 119 119 + while ((data = IO_SERIAL0_RX_DATA) & IO_SERIAL0_XMIT) {}; 120 120 + *buf = data & 0xFF; 121 121 + 122 122 + buf += 2; 123 123 + len -= 2; 124 124 + } 125 125 + 126 126 + IO_SERIAL0_TX_ENABLE = 0x0000; 127 127 + 128 128 + /* Disable the clock */ 129 129 + bitclr16(&IO_CLK_MOD2, CLK_MOD2_SIF0); 130 130 + }

+2

firmware/target/arm/tms320dm320/system-dm320.c

··· 369 369 #endif 370 370 371 371 #ifdef SANSA_CONNECT 372 372 + #ifndef HAVE_WIFI 372 373 /* keep WIFI CS and reset high to save power */ 373 374 IO_GIO_DIR0 &= ~((1 << 4) /* CS */ | (1 << 3) /* reset */); 374 375 IO_GIO_BITSET0 = (1 << 4) | (1 << 3); 376 376 + #endif 375 377 376 378 i2c_init(); 377 379 avr_hid_init();

+5

tools/buildzip.pl

··· 387 387 open(NOMEDIA, ">$temp_dir/.nomedia") || die "can't open .nomedia"; 388 388 close(NOMEDIA); 389 389 } 390 390 + # copy wifi firmware 391 391 + if ($modelname =~ /sansaconnect/) { 392 392 + glob_mkdir("$temp_dir/libertas"); 393 393 + glob_copy("$ROOT/firmware/drivers/libertas/firmware/*", "$temp_dir/libertas/"); 394 394 + } 390 395 391 396 glob_mkdir("$temp_dir/langs"); 392 397 glob_mkdir("$temp_dir/rocks");