tsiry-sandratraina.com
A modern Music Player Daemon based on Rockbox open source high quality audio player
libadwaita
audio
rust
zig
deno
mpris
rockbox
mpd
Remove the TIMER_* macros and declare target-specific functions in timer.h
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21559 a1c6a512-1295-4272-9138-f99709370657
+44
-208
+6
firmware/export/timer.h
+6
firmware/export/timer.h
···
40
40
#warning "TIMER_FREQ not defined"
41
41
#define TIMER_FREQ CPU_FREQ
42
42
#endif
43
+
43
44
bool timer_register(int reg_prio, void (*unregister_callback)(void),
44
45
long cycles, void (*timer_callback)(void)
45
46
IF_COP(,int core));
···
48
49
void timers_adjust_prescale(int multiplier, bool enable_irq);
49
50
#endif
50
51
void timer_unregister(void);
52
+
53
+
/* target-specific interface */
54
+
bool timer_set(long cycles, bool start);
55
+
bool timer_start(IF_COP_VOID(int core));
56
+
void timer_stop(void);
51
57
52
58
/* For target-specific interface use */
53
59
extern void (*pfn_timer)(void);
+3
-3
firmware/target/arm/as3525/timer-as3525.c
+3
-3
firmware/target/arm/as3525/timer-as3525.c
···
31
31
TIMER1_INTCLR = 0; /* clear interrupt */
32
32
}
33
33
34
-
bool __timer_set(long cycles, bool start)
34
+
bool timer_set(long cycles, bool start)
35
35
{
36
36
if (start)
37
37
{
···
53
53
return true;
54
54
}
55
55
56
-
bool __timer_start(void)
56
+
bool timer_start(void)
57
57
{
58
58
CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */
59
59
VIC_INT_ENABLE |= INTERRUPT_TIMER1;
60
60
return true;
61
61
}
62
62
63
-
void __timer_stop(void)
63
+
void timer_stop(void)
64
64
{
65
65
TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */
66
66
VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */
-13
firmware/target/arm/as3525/timer-target.h
-13
firmware/target/arm/as3525/timer-target.h
···
21
21
#ifndef TIMER_TARGET_H
22
22
#define TIMER_TARGET_H
23
23
24
-
bool __timer_set(long cycles, bool set);
25
-
bool __timer_start(void);
26
-
void __timer_stop(void);
27
-
28
24
#define TIMER_FREQ (24000000 / 16)
29
-
30
-
#define __TIMER_SET(cycles, set) \
31
-
__timer_set(cycles, set)
32
-
33
-
#define __TIMER_START() \
34
-
__timer_start()
35
-
36
-
#define __TIMER_STOP(...) \
37
-
__timer_stop()
38
25
39
26
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
+3
-3
firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
···
48
48
}
49
49
}
50
50
51
-
bool __timer_set(long cycles, bool start)
51
+
bool timer_set(long cycles, bool start)
52
52
{
53
53
if (cycles < 1000) /* Max value on PITC?? */
54
54
{
···
67
67
return false;
68
68
}
69
69
70
-
bool __timer_start(void)
70
+
bool timer_start(void)
71
71
{
72
72
bool retval = true;
73
73
volatile unsigned long pimr = 0;
···
101
101
return retval;
102
102
}
103
103
104
-
void __timer_stop(void)
104
+
void timer_stop(void)
105
105
{
106
106
volatile unsigned long pimr = 0;
107
107
-13
firmware/target/arm/at91sam/lyre_proto1/timer-target.h
-13
firmware/target/arm/at91sam/lyre_proto1/timer-target.h
···
25
25
/* timer is based on PCLK and minimum division is 2 */
26
26
#define TIMER_FREQ (49156800/2)
27
27
28
-
bool __timer_set(long cycles, bool set);
29
-
bool __timer_start(void);
30
-
void __timer_stop(void);
31
-
32
-
#define __TIMER_SET(cycles, set) \
33
-
__timer_set(cycles, set)
34
-
35
-
#define __TIMER_START() \
36
-
__timer_start()
37
-
38
-
#define __TIMER_STOP(...) \
39
-
__timer_stop()
40
-
41
28
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
+3
-3
firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
···
52
52
}
53
53
}
54
54
55
-
bool _timer_set(long cycles, bool start)
55
+
bool timer_set(long cycles, bool start)
56
56
{
57
57
/* Maximum cycle count expressible in the cycles parameter is 2^31-1
58
58
* and the modulus counter is capable of 2^32-1 and as a result there is
···
86
86
return true;
87
87
}
88
88
89
-
bool _timer_start(void)
89
+
bool timer_start(void)
90
90
{
91
91
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
92
92
···
104
104
return true;
105
105
}
106
106
107
-
void _timer_stop(void)
107
+
void timer_stop(void)
108
108
{
109
109
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
110
110
/* Halt timer if running - stop module clock */
-13
firmware/target/arm/imx31/gigabeat-s/timer-target.h
-13
firmware/target/arm/imx31/gigabeat-s/timer-target.h
···
24
24
/* timer is based on ipg_clk */
25
25
#define TIMER_FREQ (66000000)
26
26
27
-
bool _timer_set(long cycles, bool set);
28
-
bool _timer_start(void);
29
-
void _timer_stop(void);
30
-
31
-
#define __TIMER_SET(cycles, set) \
32
-
_timer_set(cycles, set)
33
-
34
-
#define __TIMER_START() \
35
-
_timer_start()
36
-
37
-
#define __TIMER_STOP(...) \
38
-
_timer_stop()
39
-
40
27
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/pnx0101/timer-pnx0101.c
+3
-3
firmware/target/arm/pnx0101/timer-pnx0101.c
···
43
43
TIMER1.clr = 1; /* clear the interrupt */
44
44
}
45
45
46
-
bool __timer_set(long cycles, bool start)
46
+
bool timer_set(long cycles, bool start)
47
47
{
48
48
if (start)
49
49
{
···
68
68
return true;
69
69
}
70
70
71
-
bool __timer_start(void)
71
+
bool timer_start(void)
72
72
{
73
73
irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
74
74
irq_enable_int(IRQ_TIMER1);
75
75
return true;
76
76
}
77
77
78
-
void __timer_stop(void)
78
+
void timer_stop(void)
79
79
{
80
80
TIMER1.ctrl &= ~0x80; /* disable timer 1 */
81
81
irq_disable_int(IRQ_TIMER1);
-13
firmware/target/arm/pnx0101/timer-target.h
-13
firmware/target/arm/pnx0101/timer-target.h
···
21
21
#ifndef TIMER_TARGET_H
22
22
#define TIMER_TARGET_H
23
23
24
-
bool __timer_set(long cycles, bool start);
25
-
bool __timer_start(void);
26
-
void __timer_stop(void);
27
-
28
24
#define TIMER_FREQ 3000000
29
-
30
-
#define __TIMER_SET(cycles, set) \
31
-
__timer_set(cycles, set)
32
-
33
-
#define __TIMER_START() \
34
-
__timer_start()
35
-
36
-
#define __TIMER_STOP(...) \
37
-
__timer_stop()
38
25
39
26
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c
+3
-3
firmware/target/arm/s3c2440/gigabeat-fx/timer-meg-fx.c
···
48
48
INTPND = TIMER0_MASK;
49
49
}
50
50
51
-
bool __timer_set(long cycles, bool start)
51
+
bool timer_set(long cycles, bool start)
52
52
{
53
53
bool retval = false;
54
54
···
87
87
return retval;
88
88
}
89
89
90
-
bool __timer_start(void)
90
+
bool timer_start(void)
91
91
{
92
92
bool retval = true;
93
93
···
122
122
return retval;
123
123
}
124
124
125
-
void __timer_stop(void)
125
+
void timer_stop(void)
126
126
{
127
127
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
128
128
stop_timer();
-13
firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
-13
firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
···
25
25
#define TIMER_FREQ (49156800/2)
26
26
#define TIMER234_PRESCALE 21
27
27
28
-
bool __timer_set(long cycles, bool set);
29
-
bool __timer_start(void);
30
-
void __timer_stop(void);
31
-
32
-
#define __TIMER_SET(cycles, set) \
33
-
__timer_set(cycles, set)
34
-
35
-
#define __TIMER_START() \
36
-
__timer_start()
37
-
38
-
#define __TIMER_STOP(...) \
39
-
__timer_stop()
40
-
41
28
#endif /* TIMER_TARGET_H */
-13
firmware/target/arm/tcc77x/timer-target.h
-13
firmware/target/arm/tcc77x/timer-target.h
···
24
24
/* timers are based on XIN (12Mhz) */
25
25
#define TIMER_FREQ (12000000)
26
26
27
-
bool __timer_set(long cycles, bool set);
28
-
bool __timer_start(void);
29
-
void __timer_stop(void);
30
-
31
-
#define __TIMER_SET(cycles, set) \
32
-
__timer_set(cycles, set)
33
-
34
-
#define __TIMER_START() \
35
-
__timer_start()
36
-
37
-
#define __TIMER_STOP(...) \
38
-
__timer_stop()
39
-
40
27
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/tcc77x/timer-tcc77x.c
+3
-3
firmware/target/arm/tcc77x/timer-tcc77x.c
···
28
28
/* Use the TC32 counter [sourced by Xin:12Mhz] for this timer, as it's the
29
29
only one that allows a 32-bit counter (Timer0-5 are 16/20 bit only). */
30
30
31
-
bool __timer_set(long cycles, bool start)
31
+
bool timer_set(long cycles, bool start)
32
32
{
33
33
#warning function not implemented
34
34
···
37
37
return false;
38
38
}
39
39
40
-
bool __timer_start(void)
40
+
bool timer_start(void)
41
41
{
42
42
#warning function not implemented
43
43
44
44
return false;
45
45
}
46
46
47
-
void __timer_stop(void)
47
+
void timer_stop(void)
48
48
{
49
49
#warning function not implemented
50
50
}
-13
firmware/target/arm/tcc780x/timer-target.h
-13
firmware/target/arm/tcc780x/timer-target.h
···
24
24
/* Timer is based on PCK_TCT (set to 2Mhz in system.c) */
25
25
#define TIMER_FREQ (2000000)
26
26
27
-
bool __timer_set(long cycles, bool set);
28
-
bool __timer_start(void);
29
-
void __timer_stop(void);
30
-
31
-
#define __TIMER_SET(cycles, set) \
32
-
__timer_set(cycles, set)
33
-
34
-
#define __TIMER_START() \
35
-
__timer_start()
36
-
37
-
#define __TIMER_STOP(...) \
38
-
__timer_stop()
39
-
40
27
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/tcc780x/timer-tcc780x.c
+3
-3
firmware/target/arm/tcc780x/timer-tcc780x.c
···
27
27
28
28
static const int prescale_shifts[] = {1, 2, 3, 4, 5, 10, 12};
29
29
30
-
bool __timer_set(long cycles, bool start)
30
+
bool timer_set(long cycles, bool start)
31
31
{
32
32
bool found = false;
33
33
···
62
62
return true;
63
63
}
64
64
65
-
bool __timer_start(void)
65
+
bool timer_start(void)
66
66
{
67
67
int oldstatus = disable_interrupt_save(IRQ_STATUS);
68
68
···
73
73
return true;
74
74
}
75
75
76
-
void __timer_stop(void)
76
+
void timer_stop(void)
77
77
{
78
78
int oldstatus = disable_interrupt_save(IRQ_STATUS);
79
79
+3
-3
firmware/target/arm/timer-pp.c
+3
-3
firmware/target/arm/timer-pp.c
···
44
44
}
45
45
}
46
46
47
-
bool __timer_set(long cycles, bool start)
47
+
bool timer_set(long cycles, bool start)
48
48
{
49
49
if (cycles > 0x20000000 || cycles < 2)
50
50
return false;
···
67
67
return true;
68
68
}
69
69
70
-
bool __timer_start(IF_COP_VOID(int core))
70
+
bool timer_start(IF_COP_VOID(int core))
71
71
{
72
72
/* unmask interrupt source */
73
73
#if NUM_CORES > 1
···
79
79
return true;
80
80
}
81
81
82
-
void __timer_stop(void)
82
+
void timer_stop(void)
83
83
{
84
84
TIMER2_CFG = 0; /* stop timer 2 */
85
85
CPU_INT_DIS = TIMER2_MASK;
-18
firmware/target/arm/timer-target.h
-18
firmware/target/arm/timer-target.h
···
28
28
#error "PP specific header"
29
29
#endif
30
30
31
-
bool __timer_set(long cycles, bool start);
32
-
bool __timer_start(IF_COP_VOID(int core));
33
-
void __timer_stop(void);
34
-
35
31
/* Portalplayer chips use a microsecond timer. */
36
32
#define TIMER_FREQ 1000000
37
-
38
-
#define __TIMER_SET(cycles, set) \
39
-
__timer_set(cycles, set)
40
-
41
-
#if NUM_CORES > 1
42
-
#define __TIMER_START(core) \
43
-
__timer_start(core)
44
-
#else
45
-
#define __TIMER_START() \
46
-
__timer_start()
47
-
#endif
48
-
49
-
#define __TIMER_STOP(...) \
50
-
__timer_stop()
51
33
52
34
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/arm/tms320dm320/timer-dm320.c
+3
-3
firmware/target/arm/tms320dm320/timer-dm320.c
···
34
34
pfn_timer();
35
35
}
36
36
37
-
bool __timer_set(long cycles, bool start)
37
+
bool timer_set(long cycles, bool start)
38
38
{
39
39
int oldlevel;
40
40
unsigned int divider=cycles, prescaler=0;
···
82
82
IO_CLK_MOD2 &= ~CLK_MOD2_TMR0; //disable TIMER0 clock
83
83
}
84
84
85
-
bool __timer_start(void)
85
+
bool timer_start(void)
86
86
{
87
87
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
88
88
···
100
100
return true;
101
101
}
102
102
103
-
void __timer_stop(void)
103
+
void timer_stop(void)
104
104
{
105
105
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
106
106
stop_timer();
-13
firmware/target/arm/tms320dm320/timer-target.h
-13
firmware/target/arm/tms320dm320/timer-target.h
···
24
24
/* timer is based on PCLK and minimum division is 2 */
25
25
#define TIMER_FREQ (27000000)
26
26
27
-
bool __timer_set(long cycles, bool set);
28
-
bool __timer_start(void);
29
-
void __timer_stop(void);
30
-
31
-
#define __TIMER_SET(cycles, set) \
32
-
__timer_set(cycles, set)
33
-
34
-
#define __TIMER_START() \
35
-
__timer_start()
36
-
37
-
#define __TIMER_STOP(...) \
38
-
__timer_stop()
39
-
40
27
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/coldfire/timer-coldfire.c
+3
-3
firmware/target/coldfire/timer-coldfire.c
···
37
37
TER1 = 0xff; /* clear all events */
38
38
}
39
39
40
-
bool __timer_set(long cycles, bool start)
40
+
bool timer_set(long cycles, bool start)
41
41
{
42
42
int phi = 0; /* bits for the prescaler */
43
43
int prescale = 1;
···
87
87
return true;
88
88
}
89
89
90
-
bool __timer_start(void)
90
+
bool timer_start(void)
91
91
{
92
92
ICR2 = 0x90; /* interrupt on level 4.0 */
93
93
and_l(~(1<<10), &IMR);
···
95
95
return true;
96
96
}
97
97
98
-
void __timer_stop(void)
98
+
void timer_stop(void)
99
99
{
100
100
TMR1 = 0; /* disable timer 1 */
101
101
or_l((1<<10), &IMR); /* disable interrupt */
-13
firmware/target/coldfire/timer-target.h
-13
firmware/target/coldfire/timer-target.h
···
21
21
#ifndef TIMER_TARGET_H
22
22
#define TIMER_TARGET_H
23
23
24
-
bool __timer_set(long cycles, bool start);
25
-
bool __timer_start(void);
26
-
void __timer_stop(void);
27
-
28
24
/* timer is based on busclk == cpuclk/2 */
29
25
#define TIMER_FREQ (CPU_FREQ/2)
30
-
31
-
#define __TIMER_SET(cycles, set) \
32
-
__timer_set(cycles, set)
33
-
34
-
#define __TIMER_START() \
35
-
__timer_start()
36
-
37
-
#define __TIMER_STOP(...) \
38
-
__timer_stop()
39
26
40
27
#endif /* TIMER_TARGET_H */
+3
-3
firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
+3
-3
firmware/target/mips/ingenic_jz47xx/timer-jz4740.c
···
33
33
pfn_timer();
34
34
}
35
35
36
-
bool __timer_set(long cycles, bool start)
36
+
bool timer_set(long cycles, bool start)
37
37
{
38
38
unsigned int divider = cycles, prescaler_bit = 0, prescaler = 1, old_irq;
39
39
···
79
79
return true;
80
80
}
81
81
82
-
bool __timer_start(void)
82
+
bool timer_start(void)
83
83
{
84
84
__tcu_start_counter(1);
85
85
86
86
return true;
87
87
}
88
88
89
-
void __timer_stop(void)
89
+
void timer_stop(void)
90
90
{
91
91
unsigned int old_irq = disable_irq_save();
92
92
__tcu_stop_counter(1);
-13
firmware/target/mips/ingenic_jz47xx/timer-target.h
-13
firmware/target/mips/ingenic_jz47xx/timer-target.h
···
26
26
27
27
#define TIMER_FREQ (CFG_EXTAL) /* For full precision! */
28
28
29
-
bool __timer_set(long cycles, bool set);
30
-
bool __timer_start(void);
31
-
void __timer_stop(void);
32
-
33
-
#define __TIMER_SET(cycles, set) \
34
-
__timer_set(cycles, set)
35
-
36
-
#define __TIMER_START() \
37
-
__timer_start()
38
-
39
-
#define __TIMER_STOP(...) \
40
-
__timer_stop()
41
-
42
29
#endif /* __TIMER_H_ */
+3
-3
firmware/target/sh/archos/timer-archos.c
+3
-3
firmware/target/sh/archos/timer-archos.c
···
32
32
and_b(~0x01, &TSR4); /* clear the interrupt */
33
33
}
34
34
35
-
bool __timer_set(long cycles, bool start)
35
+
bool timer_set(long cycles, bool start)
36
36
{
37
37
int phi = 0; /* bits for the prescaler */
38
38
int prescale = 1;
···
71
71
return true;
72
72
}
73
73
74
-
bool __timer_start(void)
74
+
bool timer_start(void)
75
75
{
76
76
IPRD = (IPRD & 0xFF0F) | 1 << 4; /* interrupt priority */
77
77
or_b(0x10, &TSTR); /* start timer 4 */
78
78
return true;
79
79
}
80
80
81
-
void __timer_stop(void)
81
+
void timer_stop(void)
82
82
{
83
83
and_b(~0x10, &TSTR); /* stop the timer 4 */
84
84
IPRD = (IPRD & 0xFF0F); /* disable interrupt */
-13
firmware/target/sh/archos/timer-target.h
-13
firmware/target/sh/archos/timer-target.h
···
23
23
24
24
#include "config.h"
25
25
26
-
bool __timer_set(long cycles, bool start);
27
-
bool __timer_start(void);
28
-
void __timer_stop(void);
29
-
30
26
#define TIMER_FREQ CPU_FREQ
31
-
32
-
#define __TIMER_SET(cycles, set) \
33
-
__timer_set(cycles, set)
34
-
35
-
#define __TIMER_START() \
36
-
__timer_start()
37
-
38
-
#define __TIMER_STOP(...) \
39
-
__timer_stop()
40
27
41
28
#endif /* TIMER_TARGET_H */
+2
-11
firmware/timer.c
+2
-11
firmware/timer.c
···
30
30
void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL; /* timer callback */
31
31
void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
32
32
33
-
static bool timer_set(long cycles, bool start)
34
-
{
35
-
return __TIMER_SET(cycles, start);
36
-
}
37
-
38
33
/* Register a user timer, called every <cycles> TIMER_FREQ cycles */
39
34
bool timer_register(int reg_prio, void (*unregister_callback)(void),
40
35
long cycles, void (*timer_callback)(void)
···
50
45
pfn_unregister = unregister_callback;
51
46
timer_prio = reg_prio;
52
47
53
-
#if NUM_CORES > 1
54
-
return __TIMER_START(core);
55
-
#else
56
-
return __TIMER_START();
57
-
#endif
48
+
return timer_start(IF_COP(core));
58
49
}
59
50
60
51
bool timer_set_period(long cycles)
···
64
55
65
56
void timer_unregister(void)
66
57
{
67
-
__TIMER_STOP();
58
+
timer_stop();
68
59
69
60
pfn_timer = NULL;
70
61
pfn_unregister = NULL;