oscillatory.net
signal generator for an stm32f446re nucleo board
WIP: 100 Hz sine wave
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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Core/Src/main.c
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Core/Src/main.c
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#include "main.h"
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void)
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{
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/* Infinite loop */
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while (1)
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{
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}
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}
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/**
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* @brief This function is executed in case of error occurrence.
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* @retval None
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*/
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void Error_Handler(void)
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{
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/* USER CODE BEGIN Error_Handler_Debug */
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/* User can add his own implementation to report the HAL error return state */
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__disable_irq();
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while (1)
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{
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}
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/* USER CODE END Error_Handler_Debug */
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}
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#ifdef USE_FULL_ASSERT
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/**
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* @brief Reports the name of the source file and the source line number
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* where the assert_param error has occurred.
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* @param file: pointer to the source file name
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* @param line: assert_param error line source number
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* @retval None
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*/
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void assert_failed(uint8_t *file, uint32_t line)
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{
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/* USER CODE BEGIN 6 */
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/* User can add his own implementation to report the file name and line number,
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ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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/* USER CODE END 6 */
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}
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#endif /* USE_FULL_ASSERT */
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#include "main.h"
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#include <math.h>
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#define SINE_SAMPLES 256
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static uint16_t sine_table[SINE_SAMPLES];
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/* --------------------------------------------------------------------------
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* clock_init
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*
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* HSI (16 MHz) -> PLL -> 84 MHz SYSCLK
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* PLL: M=16, N=336, P=4 => 16/16 * 336 / 4 = 84 MHz
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* APB1 = 84/2 = 42 MHz (DAC, TIM6, USART2)
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* APB2 = 84/1 = 84 MHz
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* APB1 timer clock = 84 MHz (doubled because APB1 prescaler > 1)
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* -------------------------------------------------------------------------- */
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static void clock_init(void)
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{
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/* Voltage scale 3 (supports up to 120 MHz, fine for 84 MHz).
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PWR clock must be enabled before touching PWR registers. */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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PWR->CR = (PWR->CR & ~PWR_CR_VOS) | (1UL << PWR_CR_VOS_Pos);
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/* 2 wait states required for 84 MHz. Must be set before speeding up. */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY_2WS;
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/* Enable HSI and wait for it to be ready */
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY)) {}
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/* Configure PLL (still off at this point) */
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RCC->PLLCFGR = (16 << RCC_PLLCFGR_PLLM_Pos) | /* M: divide HSI down to 1 MHz */
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(336 << RCC_PLLCFGR_PLLN_Pos) | /* N: multiply to 336 MHz VCO */
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(1 << RCC_PLLCFGR_PLLP_Pos) | /* P=4 (01): 336/4 = 84 MHz */
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(2 << RCC_PLLCFGR_PLLQ_Pos) | /* Q: USB etc, unused here */
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(2 << RCC_PLLCFGR_PLLR_Pos); /* R: I2S etc, unused here */
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/* PLLSRC bit = 0 => HSI source (default) */
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* APB1 prescaler /2 so APB1 peripherals run at 42 MHz.
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Timers on APB1 still get 84 MHz (hardware doubles it when prescaler > 1). */
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RCC->CFGR = RCC_CFGR_PPRE1_DIV2;
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/* Switch SYSCLK to PLL */
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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SystemCoreClock = 84000000;
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}
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/* --------------------------------------------------------------------------
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* dac_dma_init
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*
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* TIM6 fires at 256 kHz => DMA copies one sample per tick =>
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* 256-sample table plays back at 256000/256 = 1000 Hz
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* -------------------------------------------------------------------------- */
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static void dac_dma_init(void)
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{
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/* Enable clocks for everything we touch */
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_DMA1EN;
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RCC->APB1ENR |= RCC_APB1ENR_DACEN | RCC_APB1ENR_TIM6EN;
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/* PA4 = DAC_OUT1: set to analog mode (MODER = 0b11) so the DAC
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drives the pin directly without the GPIO output stage interfering */
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GPIOA->MODER |= (3U << (4 * 2));
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/* TIM6 ---------------------------------------------------------------
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Counter clock = APB1 timer clock = 84 MHz
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Sample rate = 84 MHz / (PSC+1) / (ARR+1) = 84 MHz / 1 / 328 = ~256 kHz
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TRGO fires on every update event, which triggers the DAC */
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TIM6->PSC = 0;
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TIM6->ARR = 3279; /* reload value: 84MHz/3280 = ~25.6kHz, /256 samples = ~100Hz */
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TIM6->CR2 = (2 << TIM_CR2_MMS_Pos); /* MMS=010: Update -> TRGO */
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/* DMA1 Stream5 Channel7 (hardwired to DAC channel 1 in the DMA mux) --
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Memory (sine_table) -> Peripheral (DAC->DHR12R1)
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Circular: wraps back to the start after SINE_SAMPLES transfers */
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DMA1_Stream5->CR = 0;
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while (DMA1_Stream5->CR & DMA_SxCR_EN) {} /* wait for any prior EN to clear */
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DMA1_Stream5->CR = (7 << DMA_SxCR_CHSEL_Pos) | /* channel 7 */
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DMA_SxCR_DIR_0 | /* memory -> peripheral */
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DMA_SxCR_CIRC | /* circular mode */
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DMA_SxCR_MINC | /* increment memory pointer */
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DMA_SxCR_MSIZE_0 | /* memory word = 16 bit */
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DMA_SxCR_PSIZE_0; /* periph word = 16 bit */
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DMA1_Stream5->NDTR = SINE_SAMPLES; /* number of transfers */
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DMA1_Stream5->PAR = (uint32_t)&DAC->DHR12R1; /* destination: DAC data reg*/
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DMA1_Stream5->M0AR = (uint32_t)sine_table; /* source: our table */
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DMA1_Stream5->CR |= DMA_SxCR_EN;
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/* DAC channel 1 -------------------------------------------------------
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TEN1 = trigger enable
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TSEL1 = 000 (default) = TIM6 TRGO triggers each conversion
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DMAEN1 = DAC issues a DMA request on each trigger
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BOFF1 = 0 (default) = output buffer ON, drives PA4 directly
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EN1 = channel enable */
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DAC->CR = DAC_CR_TEN1 | DAC_CR_DMAEN1 | DAC_CR_EN1;
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/* Start the timer last so everything is ready when samples start flowing */
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TIM6->CR1 = TIM_CR1_CEN;
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}
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int main(void)
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{
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/* Blink LD2 (PA5) 5 times to confirm the MCU is executing */
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
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GPIOA->MODER = (GPIOA->MODER & ~(3U << (5*2))) | (1U << (5*2));
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for (int b = 0; b < 5; b++) {
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GPIOA->BSRR = (1U << 5);
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for (volatile int i = 0; i < 300000; i++) {}
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GPIOA->BSRR = (1U << (5+16));
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for (volatile int i = 0; i < 300000; i++) {}
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}
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clock_init();
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/* Build sine table at runtime: 12-bit unsigned, centred at mid-scale.
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Output swings 0-3.3V (or 0-Vref) peak-to-peak */
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for (int i = 0; i < SINE_SAMPLES; i++)
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sine_table[i] = (uint16_t)(2048 + 2047.0f * sinf(2.0f * 3.14159265f * i / SINE_SAMPLES));
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dac_dma_init();
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while (1) {}
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}
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void Error_Handler(void)
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{
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__disable_irq();
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while (1) {}
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}
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cmake/stm32cubemx/CMakeLists.txt
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cmake/stm32cubemx/CMakeLists.txt
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target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE ${MX_LINK_DIRS})
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# Add libraries to the project
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target_link_libraries(${CMAKE_PROJECT_NAME} ${MX_LINK_LIBS})
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# Add the map file to the list of files to be removed with 'clean' target
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set_target_properties(${CMAKE_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES ${CMAKE_PROJECT_NAME}.map)
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target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE ${MX_LINK_DIRS})
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# Add libraries to the project
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target_link_libraries(${CMAKE_PROJECT_NAME} ${MX_LINK_LIBS} m)
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# Add the map file to the list of files to be removed with 'clean' target
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set_target_properties(${CMAKE_PROJECT_NAME} PROPERTIES ADDITIONAL_CLEAN_FILES ${CMAKE_PROJECT_NAME}.map)