+2 -1

target/m68k/cpu.h

··· 573 573 } 574 574 } 575 575 576 576 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env); 576 576 + void dump_mmu(CPUM68KState *env); 577 577 + 577 578 #endif

+56 -59

target/m68k/helper.c

··· 369 369 370 370 /* MMU: 68040 only */ 371 371 372 372 - static void print_address_zone(FILE *f, fprintf_function cpu_fprintf, 373 373 - uint32_t logical, uint32_t physical, 372 372 + static void print_address_zone(uint32_t logical, uint32_t physical, 374 373 uint32_t size, int attr) 375 374 { 376 376 - cpu_fprintf(f, "%08x - %08x -> %08x - %08x %c ", 375 375 + qemu_printf("%08x - %08x -> %08x - %08x %c ", 377 376 logical, logical + size - 1, 378 377 physical, physical + size - 1, 379 378 attr & 4 ? 'W' : '-'); 380 379 size >>= 10; 381 380 if (size < 1024) { 382 382 - cpu_fprintf(f, "(%d KiB)\n", size); 381 381 + qemu_printf("(%d KiB)\n", size); 383 382 } else { 384 383 size >>= 10; 385 384 if (size < 1024) { 386 386 - cpu_fprintf(f, "(%d MiB)\n", size); 385 385 + qemu_printf("(%d MiB)\n", size); 387 386 } else { 388 387 size >>= 10; 389 389 - cpu_fprintf(f, "(%d GiB)\n", size); 388 388 + qemu_printf("(%d GiB)\n", size); 390 389 } 391 390 } 392 391 } 393 392 394 394 - static void dump_address_map(FILE *f, fprintf_function cpu_fprintf, 395 395 - CPUM68KState *env, uint32_t root_pointer) 393 393 + static void dump_address_map(CPUM68KState *env, uint32_t root_pointer) 396 394 { 397 395 int i, j, k; 398 396 int tic_size, tic_shift; ··· 454 452 if (first_logical != 0xffffffff) { 455 453 size = last_logical + (1 << tic_shift) - 456 454 first_logical; 457 457 - print_address_zone(f, cpu_fprintf, first_logical, 455 455 + print_address_zone(first_logical, 458 456 first_physical, size, last_attr); 459 457 } 460 458 first_logical = logical; ··· 465 463 } 466 464 if (first_logical != logical || (attr & 4) != (last_attr & 4)) { 467 465 size = logical + (1 << tic_shift) - first_logical; 468 468 - print_address_zone(f, cpu_fprintf, first_logical, first_physical, size, 469 469 - last_attr); 466 466 + print_address_zone(first_logical, first_physical, size, last_attr); 470 467 } 471 468 } 472 469 473 470 #define DUMP_CACHEFLAGS(a) \ 474 471 switch (a & M68K_DESC_CACHEMODE) { \ 475 472 case M68K_DESC_CM_WRTHRU: /* cachable, write-through */ \ 476 476 - cpu_fprintf(f, "T"); \ 473 473 + qemu_printf("T"); \ 477 474 break; \ 478 475 case M68K_DESC_CM_COPYBK: /* cachable, copyback */ \ 479 479 - cpu_fprintf(f, "C"); \ 476 476 + qemu_printf("C"); \ 480 477 break; \ 481 478 case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \ 482 482 - cpu_fprintf(f, "S"); \ 479 479 + qemu_printf("S"); \ 483 480 break; \ 484 481 case M68K_DESC_CM_NCACHE: /* noncachable */ \ 485 485 - cpu_fprintf(f, "N"); \ 482 482 + qemu_printf("N"); \ 486 483 break; \ 487 484 } 488 485 489 489 - static void dump_ttr(FILE *f, fprintf_function cpu_fprintf, uint32_t ttr) 486 486 + static void dump_ttr(uint32_t ttr) 490 487 { 491 488 if ((ttr & M68K_TTR_ENABLED) == 0) { 492 492 - cpu_fprintf(f, "disabled\n"); 489 489 + qemu_printf("disabled\n"); 493 490 return; 494 491 } 495 495 - cpu_fprintf(f, "Base: 0x%08x Mask: 0x%08x Control: ", 492 492 + qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ", 496 493 ttr & M68K_TTR_ADDR_BASE, 497 494 (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT); 498 495 switch (ttr & M68K_TTR_SFIELD) { 499 496 case M68K_TTR_SFIELD_USER: 500 500 - cpu_fprintf(f, "U"); 497 497 + qemu_printf("U"); 501 498 break; 502 499 case M68K_TTR_SFIELD_SUPER: 503 503 - cpu_fprintf(f, "S"); 500 500 + qemu_printf("S"); 504 501 break; 505 502 default: 506 506 - cpu_fprintf(f, "*"); 503 503 + qemu_printf("*"); 507 504 break; 508 505 } 509 506 DUMP_CACHEFLAGS(ttr); 510 507 if (ttr & M68K_DESC_WRITEPROT) { 511 511 - cpu_fprintf(f, "R"); 508 508 + qemu_printf("R"); 512 509 } else { 513 513 - cpu_fprintf(f, "W"); 510 510 + qemu_printf("W"); 514 511 } 515 515 - cpu_fprintf(f, " U: %d\n", (ttr & M68K_DESC_USERATTR) >> 512 512 + qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >> 516 513 M68K_DESC_USERATTR_SHIFT); 517 514 } 518 515 519 519 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env) 516 516 + void dump_mmu(CPUM68KState *env) 520 517 { 521 518 if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) { 522 522 - cpu_fprintf(f, "Translation disabled\n"); 519 519 + qemu_printf("Translation disabled\n"); 523 520 return; 524 521 } 525 525 - cpu_fprintf(f, "Page Size: "); 522 522 + qemu_printf("Page Size: "); 526 523 if (env->mmu.tcr & M68K_TCR_PAGE_8K) { 527 527 - cpu_fprintf(f, "8kB\n"); 524 524 + qemu_printf("8kB\n"); 528 525 } else { 529 529 - cpu_fprintf(f, "4kB\n"); 526 526 + qemu_printf("4kB\n"); 530 527 } 531 528 532 532 - cpu_fprintf(f, "MMUSR: "); 529 529 + qemu_printf("MMUSR: "); 533 530 if (env->mmu.mmusr & M68K_MMU_B_040) { 534 534 - cpu_fprintf(f, "BUS ERROR\n"); 531 531 + qemu_printf("BUS ERROR\n"); 535 532 } else { 536 536 - cpu_fprintf(f, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000); 533 533 + qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000); 537 534 /* flags found on the page descriptor */ 538 535 if (env->mmu.mmusr & M68K_MMU_G_040) { 539 539 - cpu_fprintf(f, "G"); /* Global */ 536 536 + qemu_printf("G"); /* Global */ 540 537 } else { 541 541 - cpu_fprintf(f, "."); 538 538 + qemu_printf("."); 542 539 } 543 540 if (env->mmu.mmusr & M68K_MMU_S_040) { 544 544 - cpu_fprintf(f, "S"); /* Supervisor */ 541 541 + qemu_printf("S"); /* Supervisor */ 545 542 } else { 546 546 - cpu_fprintf(f, "."); 543 543 + qemu_printf("."); 547 544 } 548 545 if (env->mmu.mmusr & M68K_MMU_M_040) { 549 549 - cpu_fprintf(f, "M"); /* Modified */ 546 546 + qemu_printf("M"); /* Modified */ 550 547 } else { 551 551 - cpu_fprintf(f, "."); 548 548 + qemu_printf("."); 552 549 } 553 550 if (env->mmu.mmusr & M68K_MMU_WP_040) { 554 554 - cpu_fprintf(f, "W"); /* Write protect */ 551 551 + qemu_printf("W"); /* Write protect */ 555 552 } else { 556 556 - cpu_fprintf(f, "."); 553 553 + qemu_printf("."); 557 554 } 558 555 if (env->mmu.mmusr & M68K_MMU_T_040) { 559 559 - cpu_fprintf(f, "T"); /* Transparent */ 556 556 + qemu_printf("T"); /* Transparent */ 560 557 } else { 561 561 - cpu_fprintf(f, "."); 558 558 + qemu_printf("."); 562 559 } 563 560 if (env->mmu.mmusr & M68K_MMU_R_040) { 564 564 - cpu_fprintf(f, "R"); /* Resident */ 561 561 + qemu_printf("R"); /* Resident */ 565 562 } else { 566 566 - cpu_fprintf(f, "."); 563 563 + qemu_printf("."); 567 564 } 568 568 - cpu_fprintf(f, " Cache: "); 565 565 + qemu_printf(" Cache: "); 569 566 DUMP_CACHEFLAGS(env->mmu.mmusr); 570 570 - cpu_fprintf(f, " U: %d\n", (env->mmu.mmusr >> 8) & 3); 571 571 - cpu_fprintf(f, "\n"); 567 567 + qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3); 568 568 + qemu_printf("\n"); 572 569 } 573 570 574 574 - cpu_fprintf(f, "ITTR0: "); 575 575 - dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_ITTR0]); 576 576 - cpu_fprintf(f, "ITTR1: "); 577 577 - dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_ITTR1]); 578 578 - cpu_fprintf(f, "DTTR0: "); 579 579 - dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_DTTR0]); 580 580 - cpu_fprintf(f, "DTTR1: "); 581 581 - dump_ttr(f, cpu_fprintf, env->mmu.ttr[M68K_DTTR1]); 571 571 + qemu_printf("ITTR0: "); 572 572 + dump_ttr(env->mmu.ttr[M68K_ITTR0]); 573 573 + qemu_printf("ITTR1: "); 574 574 + dump_ttr(env->mmu.ttr[M68K_ITTR1]); 575 575 + qemu_printf("DTTR0: "); 576 576 + dump_ttr(env->mmu.ttr[M68K_DTTR0]); 577 577 + qemu_printf("DTTR1: "); 578 578 + dump_ttr(env->mmu.ttr[M68K_DTTR1]); 582 579 583 583 - cpu_fprintf(f, "SRP: 0x%08x\n", env->mmu.srp); 584 584 - dump_address_map(f, cpu_fprintf, env, env->mmu.srp); 580 580 + qemu_printf("SRP: 0x%08x\n", env->mmu.srp); 581 581 + dump_address_map(env, env->mmu.srp); 585 582 586 586 - cpu_fprintf(f, "URP: 0x%08x\n", env->mmu.urp); 587 587 - dump_address_map(f, cpu_fprintf, env, env->mmu.urp); 583 583 + qemu_printf("URP: 0x%08x\n", env->mmu.urp); 584 584 + dump_address_map(env, env->mmu.urp); 588 585 } 589 586 590 587 static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,

+1 -1

target/m68k/monitor.c

··· 19 19 return; 20 20 } 21 21 22 22 - dump_mmu((FILE *)mon, (fprintf_function)monitor_printf, env1); 22 22 + dump_mmu(env1); 23 23 } 24 24 25 25 static const MonitorDef monitor_defs[] = {

+1 -1

target/nios2/cpu.h

··· 212 212 void nios2_tcg_init(void); 213 213 void nios2_cpu_do_interrupt(CPUState *cs); 214 214 int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); 215 215 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env); 215 215 + void dump_mmu(CPUNios2State *env); 216 216 void nios2_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 217 217 int flags); 218 218 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

+4 -3

target/nios2/mmu.c

··· 20 20 21 21 #include "qemu/osdep.h" 22 22 #include "qemu-common.h" 23 23 + #include "qemu/qemu-print.h" 23 24 #include "cpu.h" 24 25 #include "exec/exec-all.h" 25 26 #include "mmu.h" ··· 264 265 mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries); 265 266 } 266 267 267 267 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env) 268 268 + void dump_mmu(CPUNios2State *env) 268 269 { 269 270 Nios2CPU *cpu = nios2_env_get_cpu(env); 270 271 int i; 271 272 272 272 - cpu_fprintf(f, "MMU: ways %d, entries %d, pid bits %d\n", 273 273 + qemu_printf("MMU: ways %d, entries %d, pid bits %d\n", 273 274 cpu->tlb_num_ways, cpu->tlb_num_entries, 274 275 cpu->pid_num_bits); 275 276 276 277 for (i = 0; i < cpu->tlb_num_entries; i++) { 277 278 Nios2TLBEntry *entry = &env->mmu.tlb[i]; 278 278 - cpu_fprintf(f, "TLB[%d] = %08X %08X %c VPN %05X " 279 279 + qemu_printf("TLB[%d] = %08X %08X %c VPN %05X " 279 280 "PID %02X %c PFN %05X %c%c%c%c\n", 280 281 i, entry->tag, entry->data, 281 282 (entry->tag & (1 << 10)) ? 'V' : '-',

+1 -1

target/nios2/monitor.c

··· 31 31 { 32 32 CPUArchState *env1 = mon_get_cpu_env(); 33 33 34 34 - dump_mmu((FILE *)mon, (fprintf_function)monitor_printf, env1); 34 34 + dump_mmu(env1); 35 35 }

+1 -1

target/ppc/cpu.h

··· 2629 2629 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i)); 2630 2630 } 2631 2631 2632 2632 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); 2632 2632 + void dump_mmu(CPUPPCState *env); 2633 2633 2634 2634 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); 2635 2635 #endif /* PPC_CPU_H */

+4 -3

target/ppc/mmu-hash64.c

··· 22 22 #include "exec/exec-all.h" 23 23 #include "exec/helper-proto.h" 24 24 #include "qemu/error-report.h" 25 25 + #include "qemu/qemu-print.h" 25 26 #include "sysemu/hw_accel.h" 26 27 #include "kvm_ppc.h" 27 28 #include "mmu-hash64.h" ··· 71 72 return NULL; 72 73 } 73 74 74 74 - void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu) 75 75 + void dump_slb(PowerPCCPU *cpu) 75 76 { 76 77 CPUPPCState *env = &cpu->env; 77 78 int i; ··· 79 80 80 81 cpu_synchronize_state(CPU(cpu)); 81 82 82 82 - cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); 83 83 + qemu_printf("SLB\tESID\t\t\tVSID\n"); 83 84 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 84 85 slbe = env->slb[i].esid; 85 86 slbv = env->slb[i].vsid; 86 87 if (slbe == 0 && slbv == 0) { 87 88 continue; 88 89 } 89 89 - cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", 90 90 + qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", 90 91 i, slbe, slbv); 91 92 } 92 93 }

+1 -1

target/ppc/mmu-hash64.h

··· 4 4 #ifndef CONFIG_USER_ONLY 5 5 6 6 #ifdef TARGET_PPC64 7 7 - void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu); 7 7 + void dump_slb(PowerPCCPU *cpu); 8 8 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, 9 9 target_ulong esid, target_ulong vsid); 10 10 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

+33 -37

target/ppc/mmu_helper.c

··· 29 29 #include "exec/log.h" 30 30 #include "helper_regs.h" 31 31 #include "qemu/error-report.h" 32 32 + #include "qemu/qemu-print.h" 32 33 #include "mmu-book3s-v3.h" 33 34 #include "mmu-radix64.h" 34 35 ··· 1116 1117 "1T", "2T" 1117 1118 }; 1118 1119 1119 1119 - static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf, 1120 1120 - CPUPPCState *env) 1120 1120 + static void mmubooke_dump_mmu(CPUPPCState *env) 1121 1121 { 1122 1122 ppcemb_tlb_t *entry; 1123 1123 int i; 1124 1124 1125 1125 if (kvm_enabled() && !env->kvm_sw_tlb) { 1126 1126 - cpu_fprintf(f, "Cannot access KVM TLB\n"); 1126 1126 + qemu_printf("Cannot access KVM TLB\n"); 1127 1127 return; 1128 1128 } 1129 1129 1130 1130 - cpu_fprintf(f, "\nTLB:\n"); 1131 1131 - cpu_fprintf(f, "Effective Physical Size PID Prot " 1130 1130 + qemu_printf("\nTLB:\n"); 1131 1131 + qemu_printf("Effective Physical Size PID Prot " 1132 1132 "Attr\n"); 1133 1133 1134 1134 entry = &env->tlb.tlbe[0]; ··· 1153 1153 } else { 1154 1154 snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / KiB); 1155 1155 } 1156 1156 - cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n", 1156 1156 + qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n", 1157 1157 (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID, 1158 1158 entry->prot, entry->attr); 1159 1159 } 1160 1160 1161 1161 } 1162 1162 1163 1163 - static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf, 1164 1164 - CPUPPCState *env, int tlbn, int offset, 1163 1163 + static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset, 1165 1164 int tlbsize) 1166 1165 { 1167 1166 ppcmas_tlb_t *entry; 1168 1167 int i; 1169 1168 1170 1170 - cpu_fprintf(f, "\nTLB%d:\n", tlbn); 1171 1171 - cpu_fprintf(f, "Effective Physical Size TID TS SRWX" 1169 1169 + qemu_printf("\nTLB%d:\n", tlbn); 1170 1170 + qemu_printf("Effective Physical Size TID TS SRWX" 1172 1171 " URWX WIMGE U0123\n"); 1173 1172 1174 1173 entry = &env->tlb.tlbm[offset]; ··· 1185 1184 ea = entry->mas2 & ~(size - 1); 1186 1185 pa = entry->mas7_3 & ~(size - 1); 1187 1186 1188 1188 - cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c" 1187 1187 + qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c" 1189 1188 "U%c%c%c %c%c%c%c%c U%c%c%c%c\n", 1190 1189 (uint64_t)ea, (uint64_t)pa, 1191 1190 book3e_tsize_to_str[tsize], ··· 1209 1208 } 1210 1209 } 1211 1210 1212 1212 - static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, 1213 1213 - CPUPPCState *env) 1211 1211 + static void mmubooke206_dump_mmu(CPUPPCState *env) 1214 1212 { 1215 1213 int offset = 0; 1216 1214 int i; 1217 1215 1218 1216 if (kvm_enabled() && !env->kvm_sw_tlb) { 1219 1219 - cpu_fprintf(f, "Cannot access KVM TLB\n"); 1217 1217 + qemu_printf("Cannot access KVM TLB\n"); 1220 1218 return; 1221 1219 } 1222 1220 ··· 1227 1225 continue; 1228 1226 } 1229 1227 1230 1230 - mmubooke206_dump_one_tlb(f, cpu_fprintf, env, i, offset, size); 1228 1228 + mmubooke206_dump_one_tlb(env, i, offset, size); 1231 1229 offset += size; 1232 1230 } 1233 1231 } 1234 1232 1235 1235 - static void mmu6xx_dump_BATs(FILE *f, fprintf_function cpu_fprintf, 1236 1236 - CPUPPCState *env, int type) 1233 1233 + static void mmu6xx_dump_BATs(CPUPPCState *env, int type) 1237 1234 { 1238 1235 target_ulong *BATlt, *BATut, *BATu, *BATl; 1239 1236 target_ulong BEPIl, BEPIu, bl; ··· 1256 1253 BEPIu = *BATu & 0xF0000000; 1257 1254 BEPIl = *BATu & 0x0FFE0000; 1258 1255 bl = (*BATu & 0x00001FFC) << 15; 1259 1259 - cpu_fprintf(f, "%s BAT%d BATu " TARGET_FMT_lx 1256 1256 + qemu_printf("%s BAT%d BATu " TARGET_FMT_lx 1260 1257 " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " 1261 1258 TARGET_FMT_lx " " TARGET_FMT_lx "\n", 1262 1259 type == ACCESS_CODE ? "code" : "data", i, ··· 1264 1261 } 1265 1262 } 1266 1263 1267 1267 - static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf, 1268 1268 - CPUPPCState *env) 1264 1264 + static void mmu6xx_dump_mmu(CPUPPCState *env) 1269 1265 { 1270 1266 PowerPCCPU *cpu = ppc_env_get_cpu(env); 1271 1267 ppc6xx_tlb_t *tlb; 1272 1268 target_ulong sr; 1273 1269 int type, way, entry, i; 1274 1270 1275 1275 - cpu_fprintf(f, "HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu)); 1276 1276 - cpu_fprintf(f, "HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu)); 1271 1271 + qemu_printf("HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu)); 1272 1272 + qemu_printf("HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu)); 1277 1273 1278 1278 - cpu_fprintf(f, "\nSegment registers:\n"); 1274 1274 + qemu_printf("\nSegment registers:\n"); 1279 1275 for (i = 0; i < 32; i++) { 1280 1276 sr = env->sr[i]; 1281 1277 if (sr & 0x80000000) { 1282 1282 - cpu_fprintf(f, "%02d T=%d Ks=%d Kp=%d BUID=0x%03x " 1278 1278 + qemu_printf("%02d T=%d Ks=%d Kp=%d BUID=0x%03x " 1283 1279 "CNTLR_SPEC=0x%05x\n", i, 1284 1280 sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, 1285 1281 sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF), 1286 1282 (uint32_t)(sr & 0xFFFFF)); 1287 1283 } else { 1288 1288 - cpu_fprintf(f, "%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i, 1284 1284 + qemu_printf("%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i, 1289 1285 sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, 1290 1286 sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0, 1291 1287 (uint32_t)(sr & 0x00FFFFFF)); 1292 1288 } 1293 1289 } 1294 1290 1295 1295 - cpu_fprintf(f, "\nBATs:\n"); 1296 1296 - mmu6xx_dump_BATs(f, cpu_fprintf, env, ACCESS_INT); 1297 1297 - mmu6xx_dump_BATs(f, cpu_fprintf, env, ACCESS_CODE); 1291 1291 + qemu_printf("\nBATs:\n"); 1292 1292 + mmu6xx_dump_BATs(env, ACCESS_INT); 1293 1293 + mmu6xx_dump_BATs(env, ACCESS_CODE); 1298 1294 1299 1295 if (env->id_tlbs != 1) { 1300 1300 - cpu_fprintf(f, "ERROR: 6xx MMU should have separated TLB" 1296 1296 + qemu_printf("ERROR: 6xx MMU should have separated TLB" 1301 1297 " for code and data\n"); 1302 1298 } 1303 1299 1304 1304 - cpu_fprintf(f, "\nTLBs [EPN EPN + SIZE]\n"); 1300 1300 + qemu_printf("\nTLBs [EPN EPN + SIZE]\n"); 1305 1301 1306 1302 for (type = 0; type < 2; type++) { 1307 1303 for (way = 0; way < env->nb_ways; way++) { ··· 1310 1306 entry++) { 1311 1307 1312 1308 tlb = &env->tlb.tlb6[entry]; 1313 1313 - cpu_fprintf(f, "%s TLB %02d/%02d way:%d %s [" 1309 1309 + qemu_printf("%s TLB %02d/%02d way:%d %s [" 1314 1310 TARGET_FMT_lx " " TARGET_FMT_lx "]\n", 1315 1311 type ? "code" : "data", entry % env->nb_tlb, 1316 1312 env->nb_tlb, way, ··· 1321 1317 } 1322 1318 } 1323 1319 1324 1324 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) 1320 1320 + void dump_mmu(CPUPPCState *env) 1325 1321 { 1326 1322 switch (env->mmu_model) { 1327 1323 case POWERPC_MMU_BOOKE: 1328 1328 - mmubooke_dump_mmu(f, cpu_fprintf, env); 1324 1324 + mmubooke_dump_mmu(env); 1329 1325 break; 1330 1326 case POWERPC_MMU_BOOKE206: 1331 1331 - mmubooke206_dump_mmu(f, cpu_fprintf, env); 1327 1327 + mmubooke206_dump_mmu(env); 1332 1328 break; 1333 1329 case POWERPC_MMU_SOFT_6xx: 1334 1330 case POWERPC_MMU_SOFT_74xx: 1335 1335 - mmu6xx_dump_mmu(f, cpu_fprintf, env); 1331 1331 + mmu6xx_dump_mmu(env); 1336 1332 break; 1337 1333 #if defined(TARGET_PPC64) 1338 1334 case POWERPC_MMU_64B: 1339 1335 case POWERPC_MMU_2_03: 1340 1336 case POWERPC_MMU_2_06: 1341 1337 case POWERPC_MMU_2_07: 1342 1342 - dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); 1338 1338 + dump_slb(ppc_env_get_cpu(env)); 1343 1339 break; 1344 1340 case POWERPC_MMU_3_00: 1345 1341 if (ppc64_v3_radix(ppc_env_get_cpu(env))) { 1346 1342 /* TODO - Unsupported */ 1347 1343 } else { 1348 1348 - dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); 1344 1344 + dump_slb(ppc_env_get_cpu(env)); 1349 1345 break; 1350 1346 } 1351 1347 #endif

+1 -1

target/ppc/monitor.c

··· 66 66 monitor_printf(mon, "No CPU available\n"); 67 67 return; 68 68 } 69 69 - dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1); 69 69 + dump_mmu(env1); 70 70 } 71 71 72 72 const MonitorDef monitor_defs[] = {

+1 -1

target/sparc/cpu.h

··· 583 583 int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, 584 584 int mmu_idx); 585 585 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 586 586 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); 586 586 + void dump_mmu(CPUSPARCState *env); 587 587 588 588 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 589 589 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,

+9 -9

target/sparc/ldst_helper.c

··· 198 198 replace_tlb_entry(&tlb[i], 0, 0, env1); 199 199 #ifdef DEBUG_MMU 200 200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); 201 201 - dump_mmu(stdout, fprintf, env1); 201 201 + dump_mmu(env1); 202 202 #endif 203 203 } 204 204 } ··· 260 260 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); 261 261 #ifdef DEBUG_MMU 262 262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); 263 263 - dump_mmu(stdout, fprintf, env1); 263 263 + dump_mmu(env1); 264 264 #endif 265 265 return; 266 266 } ··· 279 279 #ifdef DEBUG_MMU 280 280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", 281 281 strmmu, (replace_used ? "used" : "unused"), i); 282 282 - dump_mmu(stdout, fprintf, env1); 282 282 + dump_mmu(env1); 283 283 #endif 284 284 return; 285 285 } ··· 886 886 break; 887 887 } 888 888 #ifdef DEBUG_MMU 889 889 - dump_mmu(stdout, fprintf, env); 889 889 + dump_mmu(env); 890 890 #endif 891 891 } 892 892 break; ··· 941 941 reg, oldreg, env->mmuregs[reg]); 942 942 } 943 943 #ifdef DEBUG_MMU 944 944 - dump_mmu(stdout, fprintf, env); 944 944 + dump_mmu(env); 945 945 #endif 946 946 } 947 947 break; ··· 1634 1634 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); 1635 1635 } 1636 1636 #ifdef DEBUG_MMU 1637 1637 - dump_mmu(stdout, fprintf, env); 1637 1637 + dump_mmu(env); 1638 1638 #endif 1639 1639 return; 1640 1640 } ··· 1658 1658 } 1659 1659 #ifdef DEBUG_MMU 1660 1660 DPRINTF_MMU("immu data access replaced entry [%i]\n", i); 1661 1661 - dump_mmu(stdout, fprintf, env); 1661 1661 + dump_mmu(env); 1662 1662 #endif 1663 1663 return; 1664 1664 } ··· 1718 1718 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); 1719 1719 } 1720 1720 #ifdef DEBUG_MMU 1721 1721 - dump_mmu(stdout, fprintf, env); 1721 1721 + dump_mmu(env); 1722 1722 #endif 1723 1723 return; 1724 1724 } ··· 1740 1740 } 1741 1741 #ifdef DEBUG_MMU 1742 1742 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); 1743 1743 - dump_mmu(stdout, fprintf, env); 1743 1743 + dump_mmu(env); 1744 1744 #endif 1745 1745 return; 1746 1746 }

+49 -48

target/sparc/mmu_helper.c

··· 20 20 #include "qemu/osdep.h" 21 21 #include "cpu.h" 22 22 #include "exec/exec-all.h" 23 23 + #include "qemu/qemu-print.h" 23 24 #include "trace.h" 24 25 25 26 /* Sparc MMU emulation */ ··· 320 321 return 0; 321 322 } 322 323 323 323 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) 324 324 + void dump_mmu(CPUSPARCState *env) 324 325 { 325 326 CPUState *cs = CPU(sparc_env_get_cpu(env)); 326 327 target_ulong va, va1, va2; ··· 330 331 331 332 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); 332 333 pde = ldl_phys(cs->as, pde_ptr); 333 333 - (*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n", 334 334 - (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); 334 334 + qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", 335 335 + (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); 335 336 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { 336 337 pde = mmu_probe(env, va, 2); 337 338 if (pde) { 338 339 pa = cpu_get_phys_page_debug(cs, va); 339 339 - (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx 340 340 - " PDE: " TARGET_FMT_lx "\n", va, pa, pde); 340 340 + qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx 341 341 + " PDE: " TARGET_FMT_lx "\n", va, pa, pde); 341 342 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { 342 343 pde = mmu_probe(env, va1, 1); 343 344 if (pde) { 344 345 pa = cpu_get_phys_page_debug(cs, va1); 345 345 - (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " 346 346 - TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", 347 347 - va1, pa, pde); 346 346 + qemu_printf(" VA: " TARGET_FMT_lx ", PA: " 347 347 + TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", 348 348 + va1, pa, pde); 348 349 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { 349 350 pde = mmu_probe(env, va2, 0); 350 351 if (pde) { 351 352 pa = cpu_get_phys_page_debug(cs, va2); 352 352 - (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " 353 353 - TARGET_FMT_plx " PTE: " 354 354 - TARGET_FMT_lx "\n", 355 355 - va2, pa, pde); 353 353 + qemu_printf(" VA: " TARGET_FMT_lx ", PA: " 354 354 + TARGET_FMT_plx " PTE: " 355 355 + TARGET_FMT_lx "\n", 356 356 + va2, pa, pde); 356 357 } 357 358 } 358 359 } ··· 739 740 return 1; 740 741 } 741 742 742 742 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) 743 743 + void dump_mmu(CPUSPARCState *env) 743 744 { 744 745 unsigned int i; 745 746 const char *mask; 746 747 747 747 - (*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %" 748 748 - PRId64 "\n", 749 749 - env->dmmu.mmu_primary_context, 750 750 - env->dmmu.mmu_secondary_context); 751 751 - (*cpu_fprintf)(f, "DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64 752 752 - "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target); 748 748 + qemu_printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" 749 749 + PRId64 "\n", 750 750 + env->dmmu.mmu_primary_context, 751 751 + env->dmmu.mmu_secondary_context); 752 752 + qemu_printf("DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64 753 753 + "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target); 753 754 if ((env->lsu & DMMU_E) == 0) { 754 754 - (*cpu_fprintf)(f, "DMMU disabled\n"); 755 755 + qemu_printf("DMMU disabled\n"); 755 756 } else { 756 756 - (*cpu_fprintf)(f, "DMMU dump\n"); 757 757 + qemu_printf("DMMU dump\n"); 757 758 for (i = 0; i < 64; i++) { 758 759 switch (TTE_PGSIZE(env->dtlb[i].tte)) { 759 760 default: ··· 771 772 break; 772 773 } 773 774 if (TTE_IS_VALID(env->dtlb[i].tte)) { 774 774 - (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx" 775 775 - ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", 776 776 - i, 777 777 - env->dtlb[i].tag & (uint64_t)~0x1fffULL, 778 778 - TTE_PA(env->dtlb[i].tte), 779 779 - mask, 780 780 - TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", 781 781 - TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", 782 782 - TTE_IS_LOCKED(env->dtlb[i].tte) ? 783 783 - "locked" : "unlocked", 784 784 - env->dtlb[i].tag & (uint64_t)0x1fffULL, 785 785 - TTE_IS_GLOBAL(env->dtlb[i].tte) ? 786 786 - "global" : "local"); 775 775 + qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" 776 776 + ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", 777 777 + i, 778 778 + env->dtlb[i].tag & (uint64_t)~0x1fffULL, 779 779 + TTE_PA(env->dtlb[i].tte), 780 780 + mask, 781 781 + TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", 782 782 + TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", 783 783 + TTE_IS_LOCKED(env->dtlb[i].tte) ? 784 784 + "locked" : "unlocked", 785 785 + env->dtlb[i].tag & (uint64_t)0x1fffULL, 786 786 + TTE_IS_GLOBAL(env->dtlb[i].tte) ? 787 787 + "global" : "local"); 787 788 } 788 789 } 789 790 } 790 791 if ((env->lsu & IMMU_E) == 0) { 791 791 - (*cpu_fprintf)(f, "IMMU disabled\n"); 792 792 + qemu_printf("IMMU disabled\n"); 792 793 } else { 793 793 - (*cpu_fprintf)(f, "IMMU dump\n"); 794 794 + qemu_printf("IMMU dump\n"); 794 795 for (i = 0; i < 64; i++) { 795 796 switch (TTE_PGSIZE(env->itlb[i].tte)) { 796 797 default: ··· 808 809 break; 809 810 } 810 811 if (TTE_IS_VALID(env->itlb[i].tte)) { 811 811 - (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx" 812 812 - ", %s, %s, %s, ctx %" PRId64 " %s\n", 813 813 - i, 814 814 - env->itlb[i].tag & (uint64_t)~0x1fffULL, 815 815 - TTE_PA(env->itlb[i].tte), 816 816 - mask, 817 817 - TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", 818 818 - TTE_IS_LOCKED(env->itlb[i].tte) ? 819 819 - "locked" : "unlocked", 820 820 - env->itlb[i].tag & (uint64_t)0x1fffULL, 821 821 - TTE_IS_GLOBAL(env->itlb[i].tte) ? 822 822 - "global" : "local"); 812 812 + qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" 813 813 + ", %s, %s, %s, ctx %" PRId64 " %s\n", 814 814 + i, 815 815 + env->itlb[i].tag & (uint64_t)~0x1fffULL, 816 816 + TTE_PA(env->itlb[i].tte), 817 817 + mask, 818 818 + TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", 819 819 + TTE_IS_LOCKED(env->itlb[i].tte) ? 820 820 + "locked" : "unlocked", 821 821 + env->itlb[i].tag & (uint64_t)0x1fffULL, 822 822 + TTE_IS_GLOBAL(env->itlb[i].tte) ? 823 823 + "global" : "local"); 823 824 } 824 825 } 825 826 }

+1 -1

target/sparc/monitor.c

··· 36 36 monitor_printf(mon, "No CPU available\n"); 37 37 return; 38 38 } 39 39 - dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1); 39 39 + dump_mmu(env1); 40 40 } 41 41 42 42 #ifndef TARGET_SPARC64

+1 -1

target/xtensa/cpu.h

··· 673 673 uint32_t vaddr, int is_write, int mmu_idx, 674 674 uint32_t *paddr, uint32_t *page_size, unsigned *access); 675 675 void reset_mmu(CPUXtensaState *env); 676 676 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); 676 676 + void dump_mmu(CPUXtensaState *env); 677 677 678 678 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 679 679 {

+11 -13

target/xtensa/mmu_helper.c

··· 27 27 28 28 #include "qemu/osdep.h" 29 29 #include "qemu/main-loop.h" 30 30 + #include "qemu/qemu-print.h" 30 31 #include "qemu/units.h" 31 32 #include "cpu.h" 32 33 #include "exec/helper-proto.h" ··· 740 741 } 741 742 } 742 743 743 743 - static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, 744 744 - CPUXtensaState *env, bool dtlb) 744 744 + static void dump_tlb(CPUXtensaState *env, bool dtlb) 745 745 { 746 746 unsigned wi, ei; 747 747 const xtensa_tlb *conf = ··· 780 780 781 781 if (print_header) { 782 782 print_header = false; 783 783 - cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); 784 784 - cpu_fprintf(f, 785 785 - "\tVaddr Paddr ASID Attr RWX Cache\n" 783 783 + qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); 784 784 + qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" 786 785 "\t---------- ---------- ---- ---- --- -------\n"); 787 786 } 788 788 - cpu_fprintf(f, 789 789 - "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", 787 787 + qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", 790 788 entry->vaddr, 791 789 entry->paddr, 792 790 entry->asid, ··· 801 799 } 802 800 } 803 801 804 804 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) 802 802 + void dump_mmu(CPUXtensaState *env) 805 803 { 806 804 if (xtensa_option_bits_enabled(env->config, 807 805 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | 808 806 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | 809 807 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { 810 808 811 811 - cpu_fprintf(f, "ITLB:\n"); 812 812 - dump_tlb(f, cpu_fprintf, env, false); 813 813 - cpu_fprintf(f, "\nDTLB:\n"); 814 814 - dump_tlb(f, cpu_fprintf, env, true); 809 809 + qemu_printf("ITLB:\n"); 810 810 + dump_tlb(env, false); 811 811 + qemu_printf("\nDTLB:\n"); 812 812 + dump_tlb(env, true); 815 813 } else { 816 816 - cpu_fprintf(f, "No TLB for this CPU core\n"); 814 814 + qemu_printf("No TLB for this CPU core\n"); 817 815 } 818 816 }

+1 -1

target/xtensa/monitor.c

··· 35 35 monitor_printf(mon, "No CPU available\n"); 36 36 return; 37 37 } 38 38 - dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1); 38 38 + dump_mmu(env1); 39 39 }