jcs.org / qemu
qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/microblaze: Use env_cpu, env_archcpu

Cleanup in the boilerplate that each target must define.
Replace mb_env_get_cpu with env_archcpu. The combination
CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is available.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Richard Henderson f5c7e93a a8d92fd8

+20 -26
+1 -1
linux-user/microblaze/cpu_loop.c
··· 23 23 24 24 void cpu_loop(CPUMBState *env) 25 25 { 26 - CPUState *cs = CPU(mb_env_get_cpu(env)); 26 + CPUState *cs = env_cpu(env); 27 27 int trapnr, ret; 28 28 target_siginfo_t info; 29 29
+15 -20
target/microblaze/cpu.h
··· 310 310 CPUMBState env; 311 311 }; 312 312 313 - static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) 314 - { 315 - return container_of(env, MicroBlazeCPU, env); 316 - } 317 - 318 313 #define ENV_OFFSET offsetof(MicroBlazeCPU, env) 319 314 320 315 void mb_cpu_do_interrupt(CPUState *cs); ··· 344 339 #define MMU_USER_IDX 2 345 340 /* See NB_MMU_MODES further up the file. */ 346 341 347 - static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) 348 - { 349 - MicroBlazeCPU *cpu = mb_env_get_cpu(env); 350 - 351 - /* Are we in nommu mode?. */ 352 - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { 353 - return MMU_NOMMU_IDX; 354 - } 355 - 356 - if (env->sregs[SR_MSR] & MSR_UM) { 357 - return MMU_USER_IDX; 358 - } 359 - return MMU_KERNEL_IDX; 360 - } 361 - 362 342 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 363 343 MMUAccessType access_type, int mmu_idx, 364 344 bool probe, uintptr_t retaddr); ··· 383 363 int mmu_idx, MemTxAttrs attrs, 384 364 MemTxResult response, uintptr_t retaddr); 385 365 #endif 366 + 367 + static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) 368 + { 369 + MicroBlazeCPU *cpu = env_archcpu(env); 370 + 371 + /* Are we in nommu mode?. */ 372 + if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { 373 + return MMU_NOMMU_IDX; 374 + } 375 + 376 + if (env->sregs[SR_MSR] & MSR_UM) { 377 + return MMU_USER_IDX; 378 + } 379 + return MMU_KERNEL_IDX; 380 + } 386 381 387 382 #endif
+2 -3
target/microblaze/mmu.c
··· 34 34 35 35 static void mmu_flush_idx(CPUMBState *env, unsigned int idx) 36 36 { 37 - CPUState *cs = CPU(mb_env_get_cpu(env)); 37 + CPUState *cs = env_cpu(env); 38 38 struct microblaze_mmu *mmu = &env->mmu; 39 39 unsigned int tlb_size; 40 40 uint32_t tlb_tag, end, t; ··· 228 228 229 229 void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) 230 230 { 231 - MicroBlazeCPU *cpu = mb_env_get_cpu(env); 232 231 uint64_t tmp64; 233 232 unsigned int i; 234 233 qemu_log_mask(CPU_LOG_MMU, ··· 269 268 /* Changes to the zone protection reg flush the QEMU TLB. 270 269 Fortunately, these are very uncommon. */ 271 270 if (v != env->mmu.regs[rn]) { 272 - tlb_flush(CPU(cpu)); 271 + tlb_flush(env_cpu(env)); 273 272 } 274 273 env->mmu.regs[rn] = v; 275 274 break;
+1 -1
target/microblaze/op_helper.c
··· 65 65 66 66 void helper_raise_exception(CPUMBState *env, uint32_t index) 67 67 { 68 - CPUState *cs = CPU(mb_env_get_cpu(env)); 68 + CPUState *cs = env_cpu(env); 69 69 70 70 cs->exception_index = index; 71 71 cpu_loop_exit(cs);
+1 -1
target/microblaze/translate.c
··· 1604 1604 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1605 1605 { 1606 1606 CPUMBState *env = cs->env_ptr; 1607 - MicroBlazeCPU *cpu = mb_env_get_cpu(env); 1607 + MicroBlazeCPU *cpu = env_archcpu(env); 1608 1608 uint32_t pc_start; 1609 1609 struct DisasContext ctx; 1610 1610 struct DisasContext *dc = &ctx;