jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
watchdog: wdt_aspeed: Add support for the reset width register
The reset width register controls how the pulse on the SoC's WDTRST{1,2}
pins behaves. A pulse is emitted if the external reset bit is set in
WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns
to configure push-pull/open-drain and active-high/active-low
behaviours and thus needs some special handling in the write path.
As some of the capabilities depend on the SoC version a silicon-rev
property is introduced, which is used to guard version-specific
behaviour.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Andrew Jeffery
and committed by
Peter Maydell
f55d613b
b2bfe9f7
+84
-11
+82
-11
hw/watchdog/wdt_aspeed.c
+82
-11
hw/watchdog/wdt_aspeed.c
···
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "sysemu/watchdog.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#define WDT_STATUS (0x00 / 4)
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#define WDT_RELOAD_VALUE (0x04 / 4)
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#define WDT_RESTART (0x08 / 4)
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#define WDT_CTRL (0x0C / 4)
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#define WDT_STATUS (0x00 / 4)
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#define WDT_RELOAD_VALUE (0x04 / 4)
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#define WDT_RESTART (0x08 / 4)
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#define WDT_CTRL (0x0C / 4)
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#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
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#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
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#define WDT_CTRL_1MHZ_CLK BIT(4)
···
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#define WDT_CTRL_WDT_INTR BIT(2)
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#define WDT_CTRL_RESET_SYSTEM BIT(1)
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#define WDT_CTRL_ENABLE BIT(0)
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#define WDT_RESET_WIDTH (0x18 / 4)
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#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
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#define WDT_POLARITY_MASK (0xFF << 24)
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#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
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#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
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#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
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#define WDT_DRIVE_TYPE_MASK (0xFF << 24)
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#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
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#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
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-
#define WDT_TIMEOUT_STATUS (0x10 / 4)
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#define WDT_TIMEOUT_CLEAR (0x14 / 4)
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#define WDT_RESET_WDITH (0x18 / 4)
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#define WDT_TIMEOUT_STATUS (0x10 / 4)
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#define WDT_TIMEOUT_CLEAR (0x14 / 4)
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#define WDT_RESTART_MAGIC 0x4755
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#define WDT_RESTART_MAGIC 0x4755
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static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
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{
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return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
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}
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static bool is_ast2500(const AspeedWDTState *s)
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{
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switch (s->silicon_rev) {
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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return true;
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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default:
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break;
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}
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return false;
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}
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static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedWDTState *s = ASPEED_WDT(opaque);
···
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return 0;
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case WDT_CTRL:
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return s->regs[WDT_CTRL];
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case WDT_RESET_WIDTH:
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return s->regs[WDT_RESET_WIDTH];
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case WDT_TIMEOUT_STATUS:
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case WDT_TIMEOUT_CLEAR:
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case WDT_RESET_WDITH:
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qemu_log_mask(LOG_UNIMP,
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"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
···
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timer_del(s->timer);
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}
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break;
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case WDT_RESET_WIDTH:
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{
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uint32_t property = data & WDT_POLARITY_MASK;
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if (property && is_ast2500(s)) {
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if (property == WDT_ACTIVE_HIGH_MAGIC) {
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s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
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} else if (property == WDT_ACTIVE_LOW_MAGIC) {
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s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
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} else if (property == WDT_PUSH_PULL_MAGIC) {
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s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
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} else if (property == WDT_OPEN_DRAIN_MAGIC) {
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s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
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}
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}
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s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask;
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s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask;
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break;
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}
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case WDT_TIMEOUT_STATUS:
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case WDT_TIMEOUT_CLEAR:
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case WDT_RESET_WDITH:
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qemu_log_mask(LOG_UNIMP,
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"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
···
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s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
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s->regs[WDT_RESTART] = 0;
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s->regs[WDT_CTRL] = 0;
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s->regs[WDT_RESET_WIDTH] = 0xFF;
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timer_del(s->timer);
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}
···
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedWDTState *s = ASPEED_WDT(dev);
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if (!is_supported_silicon_rev(s->silicon_rev)) {
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error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
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s->silicon_rev);
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return;
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}
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->ext_pulse_width_mask = 0xff;
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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s->ext_pulse_width_mask = 0xfffff;
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break;
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default:
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g_assert_not_reached();
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}
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
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/* FIXME: This setting should be derived from the SCU hw strapping
···
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static Property aspeed_wdt_properties[] = {
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DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
···
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dc->reset = aspeed_wdt_reset;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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dc->vmsd = &vmstate_aspeed_wdt;
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dc->props = aspeed_wdt_properties;
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}
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static const TypeInfo aspeed_wdt_info = {