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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/mips: Clean up dsp_helper.c

Remove several minor checkpatch warnings and errors.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1556018982-3715-6-git-send-email-aleksandar.markovic@rt-rk.com>

Aleksandar Markovic f49ab2e1 1d336c87

+29 -11
+29 -11
target/mips/dsp_helper.c
··· 22 22 #include "exec/helper-proto.h" 23 23 #include "qemu/bitops.h" 24 24 25 - /* As the byte ordering doesn't matter, i.e. all columns are treated 26 - identically, these unions can be used directly. */ 25 + /* 26 + * As the byte ordering doesn't matter, i.e. all columns are treated 27 + * identically, these unions can be used directly. 28 + */ 27 29 typedef union { 28 30 uint8_t ub[4]; 29 31 int8_t sb[4]; ··· 1445 1447 return temp; 1446 1448 } 1447 1449 1448 - #define PRECR_QH_PW(name, var) \ 1449 - target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \ 1450 - uint32_t sa) \ 1450 + 1451 + /* 1452 + * In case sa == 0, use rt2, rt0, rs2, rs0. 1453 + * In case sa != 0, use rt3, rt1, rs3, rs1. 1454 + */ 1455 + #define PRECR_QH_PW(name, var) \ 1456 + target_ulong helper_precr_##name##_qh_pw(target_ulong rs, \ 1457 + target_ulong rt, \ 1458 + uint32_t sa) \ 1451 1459 { \ 1452 1460 uint16_t rs3, rs2, rs1, rs0; \ 1453 1461 uint16_t rt3, rt2, rt1, rt0; \ ··· 1456 1464 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ 1457 1465 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ 1458 1466 \ 1459 - /* When sa = 0, we use rt2, rt0, rs2, rs0; \ 1460 - * when sa != 0, we use rt3, rt1, rs3, rs1. */ \ 1461 1467 if (sa == 0) { \ 1462 1468 tempD = rt2 << var; \ 1463 1469 tempC = rt0 << var; \ ··· 1965 1971 #undef SHIFT_PH 1966 1972 1967 1973 /** DSP Multiply Sub-class insns **/ 1968 - /* Return value made up by two 16bits value. 1974 + /* 1975 + * Return value made up by two 16bits value. 1969 1976 * FIXME give the macro a better name. 1970 1977 */ 1971 1978 #define MUL_RETURN32_16_PH(name, func, \ ··· 3274 3281 CPUMIPSState *env) 3275 3282 { 3276 3283 uint64_t temp[3]; 3284 + target_ulong ret; 3277 3285 3278 3286 shift = shift & 0x3F; 3279 3287 3280 3288 mipsdsp_rndrashift_acc(temp, ac, shift, env); 3281 - return (temp[1] << 63) | (temp[0] >> 1); 3289 + 3290 + ret = (temp[1] << 63) | (temp[0] >> 1); 3291 + 3292 + return ret; 3282 3293 } 3283 3294 3284 3295 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, ··· 3286 3297 { 3287 3298 uint64_t temp[3]; 3288 3299 uint32_t temp128; 3300 + target_ulong ret; 3289 3301 3290 3302 shift = shift & 0x3F; 3291 3303 mipsdsp_rndrashift_acc(temp, ac, shift, env); ··· 3305 3317 set_DSPControl_overflow_flag(1, 23, env); 3306 3318 } 3307 3319 3308 - return (temp[1] << 63) | (temp[0] >> 1); 3320 + ret = (temp[1] << 63) | (temp[0] >> 1); 3321 + 3322 + return ret; 3309 3323 } 3310 3324 3311 3325 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, ··· 3313 3327 { 3314 3328 uint64_t temp[3]; 3315 3329 uint32_t temp128; 3330 + target_ulong ret; 3316 3331 3317 3332 shift = shift & 0x3F; 3318 3333 mipsdsp_rndrashift_acc(temp, ac, shift, env); ··· 3338 3353 } 3339 3354 set_DSPControl_overflow_flag(1, 23, env); 3340 3355 } 3341 - return (temp[1] << 63) | (temp[0] >> 1); 3356 + 3357 + ret = (temp[1] << 63) | (temp[0] >> 1); 3358 + 3359 + return ret; 3342 3360 } 3343 3361 #endif 3344 3362