+2 -4

tests/ds1338-test.c

··· 61 61 g_test_init(&argc, &argv, NULL); 62 62 63 63 s = qtest_start("-display none -machine imx25-pdk"); 64 64 - i2c = imx_i2c_create(IMX25_I2C_0_BASE); 64 64 + i2c = imx_i2c_create(s, IMX25_I2C_0_BASE); 65 65 addr = DS1338_ADDR; 66 66 67 67 qtest_add_func("/ds1338/tx-rx", send_and_receive); 68 68 69 69 ret = g_test_run(); 70 70 71 71 - if (s) { 72 72 - qtest_quit(s); 73 73 - } 71 71 + qtest_quit(s); 74 72 g_free(i2c); 75 73 76 74 return ret;

+34 -33

tests/libqos/i2c-imx.c

··· 40 40 static void imx_i2c_set_slave_addr(IMXI2C *s, uint8_t addr, 41 41 enum IMXI2CDirection direction) 42 42 { 43 43 - writeb(s->addr + I2DR_ADDR, (addr << 1) | 44 44 - (direction == IMX_I2C_READ ? 1 : 0)); 43 43 + qtest_writeb(s->parent.qts, s->addr + I2DR_ADDR, 44 44 + (addr << 1) | (direction == IMX_I2C_READ ? 1 : 0)); 45 45 } 46 46 47 47 static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr, ··· 63 63 I2CR_MTX | 64 64 I2CR_TXAK; 65 65 66 66 - writeb(s->addr + I2CR_ADDR, data); 67 67 - status = readb(s->addr + I2SR_ADDR); 66 66 + qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data); 67 67 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 68 68 g_assert((status & I2SR_IBB) != 0); 69 69 70 70 /* set the slave address */ 71 71 imx_i2c_set_slave_addr(s, addr, IMX_I2C_WRITE); 72 72 - status = readb(s->addr + I2SR_ADDR); 72 72 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 73 73 g_assert((status & I2SR_IIF) != 0); 74 74 g_assert((status & I2SR_RXAK) == 0); 75 75 76 76 /* ack the interrupt */ 77 77 - writeb(s->addr + I2SR_ADDR, 0); 78 78 - status = readb(s->addr + I2SR_ADDR); 77 77 + qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0); 78 78 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 79 79 g_assert((status & I2SR_IIF) == 0); 80 80 81 81 while (size < len) { 82 82 /* check we are still busy */ 83 83 - status = readb(s->addr + I2SR_ADDR); 83 83 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 84 84 g_assert((status & I2SR_IBB) != 0); 85 85 86 86 /* write the data */ 87 87 - writeb(s->addr + I2DR_ADDR, buf[size]); 88 88 - status = readb(s->addr + I2SR_ADDR); 87 87 + qtest_writeb(i2c->qts, s->addr + I2DR_ADDR, buf[size]); 88 88 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 89 89 g_assert((status & I2SR_IIF) != 0); 90 90 g_assert((status & I2SR_RXAK) == 0); 91 91 92 92 /* ack the interrupt */ 93 93 - writeb(s->addr + I2SR_ADDR, 0); 94 94 - status = readb(s->addr + I2SR_ADDR); 93 93 + qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0); 94 94 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 95 95 g_assert((status & I2SR_IIF) == 0); 96 96 97 97 size++; ··· 99 99 100 100 /* release the bus */ 101 101 data &= ~(I2CR_MSTA | I2CR_MTX); 102 102 - writeb(s->addr + I2CR_ADDR, data); 103 103 - status = readb(s->addr + I2SR_ADDR); 102 102 + qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data); 103 103 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 104 104 g_assert((status & I2SR_IBB) == 0); 105 105 } 106 106 ··· 123 123 I2CR_MTX | 124 124 I2CR_TXAK; 125 125 126 126 - writeb(s->addr + I2CR_ADDR, data); 127 127 - status = readb(s->addr + I2SR_ADDR); 126 126 + qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data); 127 127 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 128 128 g_assert((status & I2SR_IBB) != 0); 129 129 130 130 /* set the slave address */ 131 131 imx_i2c_set_slave_addr(s, addr, IMX_I2C_READ); 132 132 - status = readb(s->addr + I2SR_ADDR); 132 132 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 133 133 g_assert((status & I2SR_IIF) != 0); 134 134 g_assert((status & I2SR_RXAK) == 0); 135 135 136 136 /* ack the interrupt */ 137 137 - writeb(s->addr + I2SR_ADDR, 0); 138 138 - status = readb(s->addr + I2SR_ADDR); 137 137 + qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0); 138 138 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 139 139 g_assert((status & I2SR_IIF) == 0); 140 140 141 141 /* set the bus for read */ ··· 144 144 if (len != 1) { 145 145 data &= ~I2CR_TXAK; 146 146 } 147 147 - writeb(s->addr + I2CR_ADDR, data); 148 148 - status = readb(s->addr + I2SR_ADDR); 147 147 + qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data); 148 148 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 149 149 g_assert((status & I2SR_IBB) != 0); 150 150 151 151 /* dummy read */ 152 152 - readb(s->addr + I2DR_ADDR); 153 153 - status = readb(s->addr + I2SR_ADDR); 152 152 + qtest_readb(i2c->qts, s->addr + I2DR_ADDR); 153 153 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 154 154 g_assert((status & I2SR_IIF) != 0); 155 155 156 156 /* ack the interrupt */ 157 157 - writeb(s->addr + I2SR_ADDR, 0); 158 158 - status = readb(s->addr + I2SR_ADDR); 157 157 + qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0); 158 158 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 159 159 g_assert((status & I2SR_IIF) == 0); 160 160 161 161 while (size < len) { 162 162 /* check we are still busy */ 163 163 - status = readb(s->addr + I2SR_ADDR); 163 163 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 164 164 g_assert((status & I2SR_IBB) != 0); 165 165 166 166 if (size == (len - 1)) { ··· 170 170 /* ack the data read */ 171 171 data |= I2CR_TXAK; 172 172 } 173 173 - writeb(s->addr + I2CR_ADDR, data); 173 173 + qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data); 174 174 175 175 /* read the data */ 176 176 - buf[size] = readb(s->addr + I2DR_ADDR); 176 176 + buf[size] = qtest_readb(i2c->qts, s->addr + I2DR_ADDR); 177 177 178 178 if (size != (len - 1)) { 179 179 - status = readb(s->addr + I2SR_ADDR); 179 179 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 180 180 g_assert((status & I2SR_IIF) != 0); 181 181 182 182 /* ack the interrupt */ 183 183 - writeb(s->addr + I2SR_ADDR, 0); 183 183 + qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0); 184 184 } 185 185 186 186 - status = readb(s->addr + I2SR_ADDR); 186 186 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 187 187 g_assert((status & I2SR_IIF) == 0); 188 188 189 189 size++; 190 190 } 191 191 192 192 - status = readb(s->addr + I2SR_ADDR); 192 192 + status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR); 193 193 g_assert((status & I2SR_IBB) == 0); 194 194 } 195 195 196 196 - I2CAdapter *imx_i2c_create(uint64_t addr) 196 196 + I2CAdapter *imx_i2c_create(QTestState *qts, uint64_t addr) 197 197 { 198 198 IMXI2C *s = g_malloc0(sizeof(*s)); 199 199 I2CAdapter *i2c = (I2CAdapter *)s; ··· 202 202 203 203 i2c->send = imx_i2c_send; 204 204 i2c->recv = imx_i2c_recv; 205 205 + i2c->qts = qts; 205 206 206 207 return i2c; 207 208 }

+23 -22

tests/libqos/i2c-omap.c

··· 51 51 { 52 52 uint16_t data = addr; 53 53 54 54 - writew(s->addr + OMAP_I2C_SA, data); 55 55 - data = readw(s->addr + OMAP_I2C_SA); 54 54 + qtest_writew(s->parent.qts, s->addr + OMAP_I2C_SA, data); 55 55 + data = qtest_readw(s->parent.qts, s->addr + OMAP_I2C_SA); 56 56 g_assert_cmphex(data, ==, addr); 57 57 } 58 58 ··· 65 65 omap_i2c_set_slave_addr(s, addr); 66 66 67 67 data = len; 68 68 - writew(s->addr + OMAP_I2C_CNT, data); 68 68 + qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data); 69 69 70 70 data = OMAP_I2C_CON_I2C_EN | 71 71 OMAP_I2C_CON_TRX | 72 72 OMAP_I2C_CON_MST | 73 73 OMAP_I2C_CON_STT | 74 74 OMAP_I2C_CON_STP; 75 75 - writew(s->addr + OMAP_I2C_CON, data); 76 76 - data = readw(s->addr + OMAP_I2C_CON); 75 75 + qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data); 76 76 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON); 77 77 g_assert((data & OMAP_I2C_CON_STP) != 0); 78 78 79 79 - data = readw(s->addr + OMAP_I2C_STAT); 79 79 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT); 80 80 g_assert((data & OMAP_I2C_STAT_NACK) == 0); 81 81 82 82 while (len > 1) { 83 83 - data = readw(s->addr + OMAP_I2C_STAT); 83 83 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT); 84 84 g_assert((data & OMAP_I2C_STAT_XRDY) != 0); 85 85 86 86 data = buf[0] | ((uint16_t)buf[1] << 8); 87 87 - writew(s->addr + OMAP_I2C_DATA, data); 87 87 + qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data); 88 88 buf = (uint8_t *)buf + 2; 89 89 len -= 2; 90 90 } 91 91 if (len == 1) { 92 92 - data = readw(s->addr + OMAP_I2C_STAT); 92 92 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT); 93 93 g_assert((data & OMAP_I2C_STAT_XRDY) != 0); 94 94 95 95 data = buf[0]; 96 96 - writew(s->addr + OMAP_I2C_DATA, data); 96 96 + qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data); 97 97 } 98 98 99 99 - data = readw(s->addr + OMAP_I2C_CON); 99 99 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON); 100 100 g_assert((data & OMAP_I2C_CON_STP) == 0); 101 101 } 102 102 ··· 109 109 omap_i2c_set_slave_addr(s, addr); 110 110 111 111 data = len; 112 112 - writew(s->addr + OMAP_I2C_CNT, data); 112 112 + qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data); 113 113 114 114 data = OMAP_I2C_CON_I2C_EN | 115 115 OMAP_I2C_CON_MST | 116 116 OMAP_I2C_CON_STT | 117 117 OMAP_I2C_CON_STP; 118 118 - writew(s->addr + OMAP_I2C_CON, data); 119 119 - data = readw(s->addr + OMAP_I2C_CON); 118 118 + qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data); 119 119 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON); 120 120 g_assert((data & OMAP_I2C_CON_STP) == 0); 121 121 122 122 - data = readw(s->addr + OMAP_I2C_STAT); 122 122 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT); 123 123 g_assert((data & OMAP_I2C_STAT_NACK) == 0); 124 124 125 125 - data = readw(s->addr + OMAP_I2C_CNT); 125 125 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CNT); 126 126 g_assert_cmpuint(data, ==, len); 127 127 128 128 while (len > 0) { 129 129 - data = readw(s->addr + OMAP_I2C_STAT); 129 129 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT); 130 130 g_assert((data & OMAP_I2C_STAT_RRDY) != 0); 131 131 g_assert((data & OMAP_I2C_STAT_ROVR) == 0); 132 132 133 133 - data = readw(s->addr + OMAP_I2C_DATA); 133 133 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_DATA); 134 134 135 135 - stat = readw(s->addr + OMAP_I2C_STAT); 135 135 + stat = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT); 136 136 137 137 if (unlikely(len == 1)) { 138 138 g_assert((stat & OMAP_I2C_STAT_SBD) != 0); ··· 148 148 } 149 149 } 150 150 151 151 - data = readw(s->addr + OMAP_I2C_CON); 151 151 + data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON); 152 152 g_assert((data & OMAP_I2C_CON_STP) == 0); 153 153 } 154 154 155 155 - I2CAdapter *omap_i2c_create(uint64_t addr) 155 155 + I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr) 156 156 { 157 157 OMAPI2C *s = g_malloc0(sizeof(*s)); 158 158 I2CAdapter *i2c = (I2CAdapter *)s; ··· 162 162 163 163 i2c->send = omap_i2c_send; 164 164 i2c->recv = omap_i2c_recv; 165 165 + i2c->qts = qts; 165 166 166 167 /* verify the mmio address by looking for a known signature */ 167 167 - data = readw(addr + OMAP_I2C_REV); 168 168 + data = qtest_readw(qts, addr + OMAP_I2C_REV); 168 169 g_assert_cmphex(data, ==, 0x34); 169 170 170 171 return i2c;

+5 -2

tests/libqos/i2c.h

··· 9 9 #ifndef LIBQOS_I2C_H 10 10 #define LIBQOS_I2C_H 11 11 12 12 + #include "libqtest.h" 12 13 13 14 typedef struct I2CAdapter I2CAdapter; 14 15 struct I2CAdapter { ··· 16 17 const uint8_t *buf, uint16_t len); 17 18 void (*recv)(I2CAdapter *adapter, uint8_t addr, 18 19 uint8_t *buf, uint16_t len); 20 20 + 21 21 + QTestState *qts; 19 22 }; 20 23 21 24 void i2c_send(I2CAdapter *i2c, uint8_t addr, ··· 24 27 uint8_t *buf, uint16_t len); 25 28 26 29 /* libi2c-omap.c */ 27 27 - I2CAdapter *omap_i2c_create(uint64_t addr); 30 30 + I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr); 28 31 29 32 /* libi2c-imx.c */ 30 30 - I2CAdapter *imx_i2c_create(uint64_t addr); 33 33 + I2CAdapter *imx_i2c_create(QTestState *qts, uint64_t addr); 31 34 32 35 #endif

+2 -4

tests/tmp105-test.c

··· 155 155 s = qtest_start("-machine n800 " 156 156 "-device tmp105,bus=i2c-bus.0,id=" TMP105_TEST_ID 157 157 ",address=0x49"); 158 158 - i2c = omap_i2c_create(OMAP2_I2C_1_BASE); 158 158 + i2c = omap_i2c_create(s, OMAP2_I2C_1_BASE); 159 159 160 160 qtest_add_func("/tmp105/tx-rx", send_and_receive); 161 161 162 162 ret = g_test_run(); 163 163 164 164 - if (s) { 165 165 - qtest_quit(s); 166 166 - } 164 164 + qtest_quit(s); 167 165 g_free(i2c); 168 166 169 167 return ret;