arm/gicv3: update virtual irq state after IAR register read

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
register activates the highest priority pending interrupt and provides its
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
state - this change makes sure the virtual irq state is updated.

Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

authored by

Jeff Kubascik and committed by

Peter Maydell 6 years ago ef125521 85553291

1 changed file

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intc

arm_gicv3_cpuif.c

hw/intc/arm_gicv3_cpuif.c

··· 664 664 665 665 trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, 666 666 gicv3_redist_affid(cs), intid); 667 + 668 + gicv3_cpuif_virt_update(cs); 669 + 667 670 return intid; 668 671 } 669 672