Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into staging

+4

target-mips/cpu-qom.h

··· 74 74 75 75 #define ENV_OFFSET offsetof(MIPSCPU, env) 76 76 77 + #ifndef CONFIG_USER_ONLY 78 + extern const struct VMStateDescription vmstate_mips_cpu; 79 + #endif 80 + 77 81 void mips_cpu_do_interrupt(CPUState *cpu); 78 82 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); 79 83 void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,

+1

target-mips/cpu.c

··· 148 148 cc->do_unassigned_access = mips_cpu_unassigned_access; 149 149 cc->do_unaligned_access = mips_cpu_do_unaligned_access; 150 150 cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; 151 + cc->vmsd = &vmstate_mips_cpu; 151 152 #endif 152 153 153 154 cc->gdb_num_core_regs = 73;

+17 -2

target-mips/cpu.h

··· 614 614 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 615 615 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 616 616 617 - #define CPU_SAVE_VERSION 5 618 - 619 617 /* MMU modes definitions. We carefully match the indices with our 620 618 hflags layout. */ 621 619 #define MMU_MODE0_SUFFIX _kernel ··· 779 777 { 780 778 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, 781 779 &env->active_fpu.fp_status); 780 + } 781 + 782 + static inline void restore_fp_status(CPUMIPSState *env) 783 + { 784 + restore_rounding_mode(env); 785 + restore_flush_mode(env); 786 + } 787 + 788 + static inline void restore_msa_fp_status(CPUMIPSState *env) 789 + { 790 + float_status *status = &env->active_tc.msa_fp_status; 791 + int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; 792 + bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; 793 + 794 + set_float_rounding_mode(ieee_rm[rounding_mode], status); 795 + set_flush_to_zero(flush_to_zero, status); 796 + set_flush_inputs_to_zero(flush_to_zero, status); 782 797 } 783 798 784 799 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,

+253 -298

target-mips/machine.c

··· 1 1 #include "hw/hw.h" 2 - #include "hw/boards.h" 3 2 4 3 #include "cpu.h" 5 4 6 - static void save_tc(QEMUFile *f, TCState *tc) 5 + static int cpu_post_load(void *opaque, int version_id) 7 6 { 8 - int i; 7 + MIPSCPU *cpu = opaque; 8 + CPUMIPSState *env = &cpu->env; 9 9 10 - /* Save active TC */ 11 - for(i = 0; i < 32; i++) 12 - qemu_put_betls(f, &tc->gpr[i]); 13 - qemu_put_betls(f, &tc->PC); 14 - for(i = 0; i < MIPS_DSP_ACC; i++) 15 - qemu_put_betls(f, &tc->HI[i]); 16 - for(i = 0; i < MIPS_DSP_ACC; i++) 17 - qemu_put_betls(f, &tc->LO[i]); 18 - for(i = 0; i < MIPS_DSP_ACC; i++) 19 - qemu_put_betls(f, &tc->ACX[i]); 20 - qemu_put_betls(f, &tc->DSPControl); 21 - qemu_put_sbe32s(f, &tc->CP0_TCStatus); 22 - qemu_put_sbe32s(f, &tc->CP0_TCBind); 23 - qemu_put_betls(f, &tc->CP0_TCHalt); 24 - qemu_put_betls(f, &tc->CP0_TCContext); 25 - qemu_put_betls(f, &tc->CP0_TCSchedule); 26 - qemu_put_betls(f, &tc->CP0_TCScheFBack); 27 - qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); 28 - qemu_put_betls(f, &tc->CP0_UserLocal); 10 + restore_fp_status(env); 11 + restore_msa_fp_status(env); 12 + compute_hflags(env); 13 + 14 + return 0; 29 15 } 30 16 31 - static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) 17 + /* FPU state */ 18 + 19 + static int get_fpr(QEMUFile *f, void *pv, size_t size) 32 20 { 33 21 int i; 34 - 35 - for(i = 0; i < 32; i++) 36 - qemu_put_be64s(f, &fpu->fpr[i].d); 37 - qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); 38 - qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); 39 - qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); 40 - qemu_put_be32s(f, &fpu->fcr0); 41 - qemu_put_be32s(f, &fpu->fcr31); 22 + fpr_t *v = pv; 23 + /* Restore entire MSA vector register */ 24 + for (i = 0; i < MSA_WRLEN/64; i++) { 25 + qemu_get_sbe64s(f, &v->wr.d[i]); 26 + } 27 + return 0; 42 28 } 43 29 44 - void cpu_save(QEMUFile *f, void *opaque) 30 + static void put_fpr(QEMUFile *f, void *pv, size_t size) 45 31 { 46 - CPUMIPSState *env = opaque; 47 32 int i; 33 + fpr_t *v = pv; 34 + /* Save entire MSA vector register */ 35 + for (i = 0; i < MSA_WRLEN/64; i++) { 36 + qemu_put_sbe64s(f, &v->wr.d[i]); 37 + } 38 + } 48 39 49 - /* Save active TC */ 50 - save_tc(f, &env->active_tc); 40 + const VMStateInfo vmstate_info_fpr = { 41 + .name = "fpr", 42 + .get = get_fpr, 43 + .put = put_fpr, 44 + }; 51 45 52 - /* Save active FPU */ 53 - save_fpu(f, &env->active_fpu); 46 + #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ 47 + VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t) 54 48 55 - /* Save MVP */ 56 - qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); 57 - qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); 58 - qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); 49 + #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ 50 + VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) 59 51 60 - /* Save TLB */ 61 - qemu_put_be32s(f, &env->tlb->nb_tlb); 62 - qemu_put_be32s(f, &env->tlb->tlb_in_use); 63 - for(i = 0; i < MIPS_TLB_MAX; i++) { 64 - uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].EHINV << 15) | 65 - (env->tlb->mmu.r4k.tlb[i].RI1 << 14) | 66 - (env->tlb->mmu.r4k.tlb[i].RI0 << 13) | 67 - (env->tlb->mmu.r4k.tlb[i].XI1 << 12) | 68 - (env->tlb->mmu.r4k.tlb[i].XI0 << 11) | 69 - (env->tlb->mmu.r4k.tlb[i].G << 10) | 70 - (env->tlb->mmu.r4k.tlb[i].C0 << 7) | 71 - (env->tlb->mmu.r4k.tlb[i].C1 << 4) | 72 - (env->tlb->mmu.r4k.tlb[i].V0 << 3) | 73 - (env->tlb->mmu.r4k.tlb[i].V1 << 2) | 74 - (env->tlb->mmu.r4k.tlb[i].D0 << 1) | 75 - (env->tlb->mmu.r4k.tlb[i].D1 << 0)); 76 - uint8_t asid; 52 + static VMStateField vmstate_fpu_fields[] = { 53 + VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), 54 + VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), 55 + VMSTATE_UINT32(fcr31, CPUMIPSFPUContext), 56 + VMSTATE_END_OF_LIST() 57 + }; 77 58 78 - qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); 79 - qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); 80 - asid = env->tlb->mmu.r4k.tlb[i].ASID; 81 - qemu_put_8s(f, &asid); 82 - qemu_put_be16s(f, &flags); 83 - qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); 84 - qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); 85 - } 59 + const VMStateDescription vmstate_fpu = { 60 + .name = "cpu/fpu", 61 + .version_id = 1, 62 + .minimum_version_id = 1, 63 + .fields = vmstate_fpu_fields 64 + }; 86 65 87 - /* Save CPU metastate */ 88 - qemu_put_be32s(f, &env->current_tc); 89 - qemu_put_be32s(f, &env->current_fpu); 90 - qemu_put_sbe32s(f, &env->error_code); 91 - qemu_put_be32s(f, &env->hflags); 92 - qemu_put_betls(f, &env->btarget); 93 - i = env->bcond; 94 - qemu_put_sbe32s(f, &i); 66 + const VMStateDescription vmstate_inactive_fpu = { 67 + .name = "cpu/inactive_fpu", 68 + .version_id = 1, 69 + .minimum_version_id = 1, 70 + .fields = vmstate_fpu_fields 71 + }; 95 72 96 - /* Save remaining CP1 registers */ 97 - qemu_put_sbe32s(f, &env->CP0_Index); 98 - qemu_put_sbe32s(f, &env->CP0_Random); 99 - qemu_put_sbe32s(f, &env->CP0_VPEControl); 100 - qemu_put_sbe32s(f, &env->CP0_VPEConf0); 101 - qemu_put_sbe32s(f, &env->CP0_VPEConf1); 102 - qemu_put_betls(f, &env->CP0_YQMask); 103 - qemu_put_betls(f, &env->CP0_VPESchedule); 104 - qemu_put_betls(f, &env->CP0_VPEScheFBack); 105 - qemu_put_sbe32s(f, &env->CP0_VPEOpt); 106 - qemu_put_betls(f, &env->CP0_EntryLo0); 107 - qemu_put_betls(f, &env->CP0_EntryLo1); 108 - qemu_put_betls(f, &env->CP0_Context); 109 - qemu_put_sbe32s(f, &env->CP0_PageMask); 110 - qemu_put_sbe32s(f, &env->CP0_PageGrain); 111 - qemu_put_sbe32s(f, &env->CP0_Wired); 112 - qemu_put_sbe32s(f, &env->CP0_SRSConf0); 113 - qemu_put_sbe32s(f, &env->CP0_SRSConf1); 114 - qemu_put_sbe32s(f, &env->CP0_SRSConf2); 115 - qemu_put_sbe32s(f, &env->CP0_SRSConf3); 116 - qemu_put_sbe32s(f, &env->CP0_SRSConf4); 117 - qemu_put_sbe32s(f, &env->CP0_HWREna); 118 - qemu_put_betls(f, &env->CP0_BadVAddr); 119 - qemu_put_be32s(f, &env->CP0_BadInstr); 120 - qemu_put_be32s(f, &env->CP0_BadInstrP); 121 - qemu_put_sbe32s(f, &env->CP0_Count); 122 - qemu_put_betls(f, &env->CP0_EntryHi); 123 - qemu_put_sbe32s(f, &env->CP0_Compare); 124 - qemu_put_sbe32s(f, &env->CP0_Status); 125 - qemu_put_sbe32s(f, &env->CP0_IntCtl); 126 - qemu_put_sbe32s(f, &env->CP0_SRSCtl); 127 - qemu_put_sbe32s(f, &env->CP0_SRSMap); 128 - qemu_put_sbe32s(f, &env->CP0_Cause); 129 - qemu_put_betls(f, &env->CP0_EPC); 130 - qemu_put_sbe32s(f, &env->CP0_PRid); 131 - qemu_put_sbe32s(f, &env->CP0_EBase); 132 - qemu_put_sbe32s(f, &env->CP0_Config0); 133 - qemu_put_sbe32s(f, &env->CP0_Config1); 134 - qemu_put_sbe32s(f, &env->CP0_Config2); 135 - qemu_put_sbe32s(f, &env->CP0_Config3); 136 - qemu_put_sbe32s(f, &env->CP0_Config6); 137 - qemu_put_sbe32s(f, &env->CP0_Config7); 138 - qemu_put_betls(f, &env->lladdr); 139 - for(i = 0; i < 8; i++) 140 - qemu_put_betls(f, &env->CP0_WatchLo[i]); 141 - for(i = 0; i < 8; i++) 142 - qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); 143 - qemu_put_betls(f, &env->CP0_XContext); 144 - qemu_put_sbe32s(f, &env->CP0_Framemask); 145 - qemu_put_sbe32s(f, &env->CP0_Debug); 146 - qemu_put_betls(f, &env->CP0_DEPC); 147 - qemu_put_sbe32s(f, &env->CP0_Performance0); 148 - qemu_put_sbe32s(f, &env->CP0_TagLo); 149 - qemu_put_sbe32s(f, &env->CP0_DataLo); 150 - qemu_put_sbe32s(f, &env->CP0_TagHi); 151 - qemu_put_sbe32s(f, &env->CP0_DataHi); 152 - qemu_put_betls(f, &env->CP0_ErrorEPC); 153 - qemu_put_sbe32s(f, &env->CP0_DESAVE); 154 - for (i = 0; i < MIPS_KSCRATCH_NUM; i++) { 155 - qemu_put_betls(f, &env->CP0_KScratch[i]); 73 + /* TC state */ 74 + 75 + static VMStateField vmstate_tc_fields[] = { 76 + VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), 77 + VMSTATE_UINTTL(PC, TCState), 78 + VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), 79 + VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), 80 + VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC), 81 + VMSTATE_UINTTL(DSPControl, TCState), 82 + VMSTATE_INT32(CP0_TCStatus, TCState), 83 + VMSTATE_INT32(CP0_TCBind, TCState), 84 + VMSTATE_UINTTL(CP0_TCHalt, TCState), 85 + VMSTATE_UINTTL(CP0_TCContext, TCState), 86 + VMSTATE_UINTTL(CP0_TCSchedule, TCState), 87 + VMSTATE_UINTTL(CP0_TCScheFBack, TCState), 88 + VMSTATE_INT32(CP0_Debug_tcstatus, TCState), 89 + VMSTATE_UINTTL(CP0_UserLocal, TCState), 90 + VMSTATE_INT32(msacsr, TCState), 91 + VMSTATE_END_OF_LIST() 92 + }; 93 + 94 + const VMStateDescription vmstate_tc = { 95 + .name = "cpu/tc", 96 + .version_id = 1, 97 + .minimum_version_id = 1, 98 + .fields = vmstate_tc_fields 99 + }; 100 + 101 + const VMStateDescription vmstate_inactive_tc = { 102 + .name = "cpu/inactive_tc", 103 + .version_id = 1, 104 + .minimum_version_id = 1, 105 + .fields = vmstate_tc_fields 106 + }; 107 + 108 + /* MVP state */ 109 + 110 + const VMStateDescription vmstate_mvp = { 111 + .name = "cpu/mvp", 112 + .version_id = 1, 113 + .minimum_version_id = 1, 114 + .fields = (VMStateField[]) { 115 + VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext), 116 + VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext), 117 + VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext), 118 + VMSTATE_END_OF_LIST() 156 119 } 120 + }; 157 121 158 - /* Save inactive TC state */ 159 - for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) 160 - save_tc(f, &env->tcs[i]); 161 - for (i = 0; i < MIPS_FPU_MAX; i++) 162 - save_fpu(f, &env->fpus[i]); 163 - } 122 + /* TLB state */ 164 123 165 - static void load_tc(QEMUFile *f, TCState *tc, int version_id) 124 + static int get_tlb(QEMUFile *f, void *pv, size_t size) 166 125 { 167 - int i; 126 + r4k_tlb_t *v = pv; 127 + uint16_t flags; 168 128 169 - /* Save active TC */ 170 - for(i = 0; i < 32; i++) 171 - qemu_get_betls(f, &tc->gpr[i]); 172 - qemu_get_betls(f, &tc->PC); 173 - for(i = 0; i < MIPS_DSP_ACC; i++) 174 - qemu_get_betls(f, &tc->HI[i]); 175 - for(i = 0; i < MIPS_DSP_ACC; i++) 176 - qemu_get_betls(f, &tc->LO[i]); 177 - for(i = 0; i < MIPS_DSP_ACC; i++) 178 - qemu_get_betls(f, &tc->ACX[i]); 179 - qemu_get_betls(f, &tc->DSPControl); 180 - qemu_get_sbe32s(f, &tc->CP0_TCStatus); 181 - qemu_get_sbe32s(f, &tc->CP0_TCBind); 182 - qemu_get_betls(f, &tc->CP0_TCHalt); 183 - qemu_get_betls(f, &tc->CP0_TCContext); 184 - qemu_get_betls(f, &tc->CP0_TCSchedule); 185 - qemu_get_betls(f, &tc->CP0_TCScheFBack); 186 - qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); 187 - if (version_id >= 4) { 188 - qemu_get_betls(f, &tc->CP0_UserLocal); 189 - } 129 + qemu_get_betls(f, &v->VPN); 130 + qemu_get_be32s(f, &v->PageMask); 131 + qemu_get_8s(f, &v->ASID); 132 + qemu_get_be16s(f, &flags); 133 + v->G = (flags >> 10) & 1; 134 + v->C0 = (flags >> 7) & 3; 135 + v->C1 = (flags >> 4) & 3; 136 + v->V0 = (flags >> 3) & 1; 137 + v->V1 = (flags >> 2) & 1; 138 + v->D0 = (flags >> 1) & 1; 139 + v->D1 = (flags >> 0) & 1; 140 + v->EHINV = (flags >> 15) & 1; 141 + v->RI1 = (flags >> 14) & 1; 142 + v->RI0 = (flags >> 13) & 1; 143 + v->XI1 = (flags >> 12) & 1; 144 + v->XI0 = (flags >> 11) & 1; 145 + qemu_get_betls(f, &v->PFN[0]); 146 + qemu_get_betls(f, &v->PFN[1]); 147 + 148 + return 0; 190 149 } 191 150 192 - static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) 151 + static void put_tlb(QEMUFile *f, void *pv, size_t size) 193 152 { 194 - int i; 153 + r4k_tlb_t *v = pv; 154 + 155 + uint16_t flags = ((v->EHINV << 15) | 156 + (v->RI1 << 14) | 157 + (v->RI0 << 13) | 158 + (v->XI1 << 12) | 159 + (v->XI0 << 11) | 160 + (v->G << 10) | 161 + (v->C0 << 7) | 162 + (v->C1 << 4) | 163 + (v->V0 << 3) | 164 + (v->V1 << 2) | 165 + (v->D0 << 1) | 166 + (v->D1 << 0)); 195 167 196 - for(i = 0; i < 32; i++) 197 - qemu_get_be64s(f, &fpu->fpr[i].d); 198 - qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); 199 - qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); 200 - qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); 201 - qemu_get_be32s(f, &fpu->fcr0); 202 - qemu_get_be32s(f, &fpu->fcr31); 168 + qemu_put_betls(f, &v->VPN); 169 + qemu_put_be32s(f, &v->PageMask); 170 + qemu_put_8s(f, &v->ASID); 171 + qemu_put_be16s(f, &flags); 172 + qemu_put_betls(f, &v->PFN[0]); 173 + qemu_put_betls(f, &v->PFN[1]); 203 174 } 204 175 205 - int cpu_load(QEMUFile *f, void *opaque, int version_id) 206 - { 207 - CPUMIPSState *env = opaque; 208 - MIPSCPU *cpu = mips_env_get_cpu(env); 209 - int i; 176 + const VMStateInfo vmstate_info_tlb = { 177 + .name = "tlb_entry", 178 + .get = get_tlb, 179 + .put = put_tlb, 180 + }; 210 181 211 - if (version_id < 3) { 212 - return -EINVAL; 182 + #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \ 183 + VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t) 184 + 185 + #define VMSTATE_TLB_ARRAY(_f, _s, _n) \ 186 + VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0) 187 + 188 + const VMStateDescription vmstate_tlb = { 189 + .name = "cpu/tlb", 190 + .version_id = 1, 191 + .minimum_version_id = 1, 192 + .fields = (VMStateField[]) { 193 + VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), 194 + VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), 195 + VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX), 196 + VMSTATE_END_OF_LIST() 213 197 } 198 + }; 214 199 215 - /* Load active TC */ 216 - load_tc(f, &env->active_tc, version_id); 200 + /* MIPS CPU state */ 217 201 218 - /* Load active FPU */ 219 - load_fpu(f, &env->active_fpu); 202 + const VMStateDescription vmstate_mips_cpu = { 203 + .name = "cpu", 204 + .version_id = 6, 205 + .minimum_version_id = 6, 206 + .post_load = cpu_post_load, 207 + .fields = (VMStateField[]) { 208 + /* Active TC */ 209 + VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState), 220 210 221 - /* Load MVP */ 222 - qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); 223 - qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); 224 - qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); 211 + /* Active FPU */ 212 + VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu, 213 + CPUMIPSFPUContext), 225 214 226 - /* Load TLB */ 227 - qemu_get_be32s(f, &env->tlb->nb_tlb); 228 - qemu_get_be32s(f, &env->tlb->tlb_in_use); 229 - for(i = 0; i < MIPS_TLB_MAX; i++) { 230 - uint16_t flags; 231 - uint8_t asid; 215 + /* MVP */ 216 + VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp, 217 + CPUMIPSMVPContext), 232 218 233 - qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); 234 - qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); 235 - qemu_get_8s(f, &asid); 236 - env->tlb->mmu.r4k.tlb[i].ASID = asid; 237 - qemu_get_be16s(f, &flags); 238 - env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; 239 - env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; 240 - env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; 241 - env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; 242 - env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; 243 - env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; 244 - env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; 245 - if (version_id >= 5) { 246 - env->tlb->mmu.r4k.tlb[i].EHINV = (flags >> 15) & 1; 247 - env->tlb->mmu.r4k.tlb[i].RI1 = (flags >> 14) & 1; 248 - env->tlb->mmu.r4k.tlb[i].RI0 = (flags >> 13) & 1; 249 - env->tlb->mmu.r4k.tlb[i].XI1 = (flags >> 12) & 1; 250 - env->tlb->mmu.r4k.tlb[i].XI0 = (flags >> 11) & 1; 251 - } 252 - qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); 253 - qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); 254 - } 219 + /* TLB */ 220 + VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb, 221 + CPUMIPSTLBContext), 255 222 256 - /* Load CPU metastate */ 257 - qemu_get_be32s(f, &env->current_tc); 258 - qemu_get_be32s(f, &env->current_fpu); 259 - qemu_get_sbe32s(f, &env->error_code); 260 - qemu_get_be32s(f, &env->hflags); 261 - qemu_get_betls(f, &env->btarget); 262 - qemu_get_sbe32s(f, &i); 263 - env->bcond = i; 223 + /* CPU metastate */ 224 + VMSTATE_UINT32(env.current_tc, MIPSCPU), 225 + VMSTATE_UINT32(env.current_fpu, MIPSCPU), 226 + VMSTATE_INT32(env.error_code, MIPSCPU), 227 + VMSTATE_UINTTL(env.btarget, MIPSCPU), 228 + VMSTATE_UINTTL(env.bcond, MIPSCPU), 264 229 265 - /* Load remaining CP1 registers */ 266 - qemu_get_sbe32s(f, &env->CP0_Index); 267 - qemu_get_sbe32s(f, &env->CP0_Random); 268 - qemu_get_sbe32s(f, &env->CP0_VPEControl); 269 - qemu_get_sbe32s(f, &env->CP0_VPEConf0); 270 - qemu_get_sbe32s(f, &env->CP0_VPEConf1); 271 - qemu_get_betls(f, &env->CP0_YQMask); 272 - qemu_get_betls(f, &env->CP0_VPESchedule); 273 - qemu_get_betls(f, &env->CP0_VPEScheFBack); 274 - qemu_get_sbe32s(f, &env->CP0_VPEOpt); 275 - qemu_get_betls(f, &env->CP0_EntryLo0); 276 - qemu_get_betls(f, &env->CP0_EntryLo1); 277 - qemu_get_betls(f, &env->CP0_Context); 278 - qemu_get_sbe32s(f, &env->CP0_PageMask); 279 - qemu_get_sbe32s(f, &env->CP0_PageGrain); 280 - qemu_get_sbe32s(f, &env->CP0_Wired); 281 - qemu_get_sbe32s(f, &env->CP0_SRSConf0); 282 - qemu_get_sbe32s(f, &env->CP0_SRSConf1); 283 - qemu_get_sbe32s(f, &env->CP0_SRSConf2); 284 - qemu_get_sbe32s(f, &env->CP0_SRSConf3); 285 - qemu_get_sbe32s(f, &env->CP0_SRSConf4); 286 - qemu_get_sbe32s(f, &env->CP0_HWREna); 287 - qemu_get_betls(f, &env->CP0_BadVAddr); 288 - if (version_id >= 5) { 289 - qemu_get_be32s(f, &env->CP0_BadInstr); 290 - qemu_get_be32s(f, &env->CP0_BadInstrP); 291 - } 292 - qemu_get_sbe32s(f, &env->CP0_Count); 293 - qemu_get_betls(f, &env->CP0_EntryHi); 294 - qemu_get_sbe32s(f, &env->CP0_Compare); 295 - qemu_get_sbe32s(f, &env->CP0_Status); 296 - qemu_get_sbe32s(f, &env->CP0_IntCtl); 297 - qemu_get_sbe32s(f, &env->CP0_SRSCtl); 298 - qemu_get_sbe32s(f, &env->CP0_SRSMap); 299 - qemu_get_sbe32s(f, &env->CP0_Cause); 300 - qemu_get_betls(f, &env->CP0_EPC); 301 - qemu_get_sbe32s(f, &env->CP0_PRid); 302 - qemu_get_sbe32s(f, &env->CP0_EBase); 303 - qemu_get_sbe32s(f, &env->CP0_Config0); 304 - qemu_get_sbe32s(f, &env->CP0_Config1); 305 - qemu_get_sbe32s(f, &env->CP0_Config2); 306 - qemu_get_sbe32s(f, &env->CP0_Config3); 307 - qemu_get_sbe32s(f, &env->CP0_Config6); 308 - qemu_get_sbe32s(f, &env->CP0_Config7); 309 - qemu_get_betls(f, &env->lladdr); 310 - for(i = 0; i < 8; i++) 311 - qemu_get_betls(f, &env->CP0_WatchLo[i]); 312 - for(i = 0; i < 8; i++) 313 - qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); 314 - qemu_get_betls(f, &env->CP0_XContext); 315 - qemu_get_sbe32s(f, &env->CP0_Framemask); 316 - qemu_get_sbe32s(f, &env->CP0_Debug); 317 - qemu_get_betls(f, &env->CP0_DEPC); 318 - qemu_get_sbe32s(f, &env->CP0_Performance0); 319 - qemu_get_sbe32s(f, &env->CP0_TagLo); 320 - qemu_get_sbe32s(f, &env->CP0_DataLo); 321 - qemu_get_sbe32s(f, &env->CP0_TagHi); 322 - qemu_get_sbe32s(f, &env->CP0_DataHi); 323 - qemu_get_betls(f, &env->CP0_ErrorEPC); 324 - qemu_get_sbe32s(f, &env->CP0_DESAVE); 325 - if (version_id >= 5) { 326 - for (i = 0; i < MIPS_KSCRATCH_NUM; i++) { 327 - qemu_get_betls(f, &env->CP0_KScratch[i]); 328 - } 329 - } 230 + /* Remaining CP0 registers */ 231 + VMSTATE_INT32(env.CP0_Index, MIPSCPU), 232 + VMSTATE_INT32(env.CP0_Random, MIPSCPU), 233 + VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), 234 + VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), 235 + VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU), 236 + VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU), 237 + VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU), 238 + VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU), 239 + VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), 240 + VMSTATE_UINTTL(env.CP0_EntryLo0, MIPSCPU), 241 + VMSTATE_UINTTL(env.CP0_EntryLo1, MIPSCPU), 242 + VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), 243 + VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), 244 + VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), 245 + VMSTATE_INT32(env.CP0_Wired, MIPSCPU), 246 + VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), 247 + VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), 248 + VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU), 249 + VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU), 250 + VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU), 251 + VMSTATE_INT32(env.CP0_HWREna, MIPSCPU), 252 + VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), 253 + VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), 254 + VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), 255 + VMSTATE_INT32(env.CP0_Count, MIPSCPU), 256 + VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), 257 + VMSTATE_INT32(env.CP0_Compare, MIPSCPU), 258 + VMSTATE_INT32(env.CP0_Status, MIPSCPU), 259 + VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU), 260 + VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU), 261 + VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU), 262 + VMSTATE_INT32(env.CP0_Cause, MIPSCPU), 263 + VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), 264 + VMSTATE_INT32(env.CP0_PRid, MIPSCPU), 265 + VMSTATE_INT32(env.CP0_EBase, MIPSCPU), 266 + VMSTATE_INT32(env.CP0_Config0, MIPSCPU), 267 + VMSTATE_INT32(env.CP0_Config1, MIPSCPU), 268 + VMSTATE_INT32(env.CP0_Config2, MIPSCPU), 269 + VMSTATE_INT32(env.CP0_Config3, MIPSCPU), 270 + VMSTATE_INT32(env.CP0_Config6, MIPSCPU), 271 + VMSTATE_INT32(env.CP0_Config7, MIPSCPU), 272 + VMSTATE_UINTTL(env.lladdr, MIPSCPU), 273 + VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), 274 + VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), 275 + VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), 276 + VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), 277 + VMSTATE_INT32(env.CP0_Debug, MIPSCPU), 278 + VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), 279 + VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), 280 + VMSTATE_INT32(env.CP0_TagLo, MIPSCPU), 281 + VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), 282 + VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), 283 + VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), 284 + VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), 285 + VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU), 286 + VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM), 330 287 331 - /* Load inactive TC state */ 332 - for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) { 333 - load_tc(f, &env->tcs[i], version_id); 334 - } 335 - for (i = 0; i < MIPS_FPU_MAX; i++) 336 - load_fpu(f, &env->fpus[i]); 288 + /* Inactive TC */ 289 + VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, 290 + vmstate_inactive_tc, TCState), 291 + VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1, 292 + vmstate_inactive_fpu, CPUMIPSFPUContext), 337 293 338 - /* XXX: ensure compatibility for halted bit ? */ 339 - tlb_flush(CPU(cpu), 1); 340 - return 0; 341 - } 294 + VMSTATE_END_OF_LIST() 295 + }, 296 + };

+1 -11

target-mips/msa_helper.c

··· 1348 1348 break; 1349 1349 case 1: 1350 1350 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK; 1351 - /* set float_status rounding mode */ 1352 - set_float_rounding_mode( 1353 - ieee_rm[(env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM], 1354 - &env->active_tc.msa_fp_status); 1355 - /* set float_status flush modes */ 1356 - set_flush_to_zero( 1357 - (env->active_tc.msacsr & MSACSR_FS_MASK) != 0 ? 1 : 0, 1358 - &env->active_tc.msa_fp_status); 1359 - set_flush_inputs_to_zero( 1360 - (env->active_tc.msacsr & MSACSR_FS_MASK) != 0 ? 1 : 0, 1361 - &env->active_tc.msa_fp_status); 1351 + restore_msa_fp_status(env); 1362 1352 /* check exception */ 1363 1353 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED) 1364 1354 & GET_FP_CAUSE(env->active_tc.msacsr)) {

+2 -8

target-mips/translate_init.c

··· 835 835 - round to nearest / ties to even (RM bits are 0) */ 836 836 env->active_tc.msacsr = 0; 837 837 838 + restore_msa_fp_status(env); 839 + 838 840 /* tininess detected after rounding.*/ 839 841 set_float_detect_tininess(float_tininess_after_rounding, 840 842 &env->active_tc.msa_fp_status); 841 843 842 844 /* clear float_status exception flags */ 843 845 set_float_exception_flags(0, &env->active_tc.msa_fp_status); 844 - 845 - /* set float_status rounding mode */ 846 - set_float_rounding_mode(float_round_nearest_even, 847 - &env->active_tc.msa_fp_status); 848 - 849 - /* set float_status flush modes */ 850 - set_flush_to_zero(0, &env->active_tc.msa_fp_status); 851 - set_flush_inputs_to_zero(0, &env->active_tc.msa_fp_status); 852 846 853 847 /* clear float_status nan mode */ 854 848 set_default_nan_mode(0, &env->active_tc.msa_fp_status);