jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
apic: rename apic specific bitopts
apic has its own version of bitops, with the
difference that it works on u32 and not long.
Add apic_ prefix to avoid namespace clashes.
We should look into reusing standard bitops long-term,
but that's not entirely trivial.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
+21
-21
+21
-21
hw/intc/apic.c
+21
-21
hw/intc/apic.c
···
40
40
uint8_t dest, uint8_t dest_mode);
41
41
42
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/* Find first bit starting from msb */
43
-
static int fls_bit(uint32_t value)
43
+
static int apic_fls_bit(uint32_t value)
44
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{
45
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return 31 - clz32(value);
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}
47
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/* Find first bit starting from lsb */
49
-
static int ffs_bit(uint32_t value)
49
+
static int apic_ffs_bit(uint32_t value)
50
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{
51
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return ctz32(value);
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}
53
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54
-
static inline void set_bit(uint32_t *tab, int index)
54
+
static inline void apic_set_bit(uint32_t *tab, int index)
55
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{
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int i, mask;
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i = index >> 5;
···
59
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tab[i] |= mask;
60
60
}
61
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62
-
static inline void reset_bit(uint32_t *tab, int index)
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+
static inline void apic_reset_bit(uint32_t *tab, int index)
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63
{
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int i, mask;
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i = index >> 5;
···
67
67
tab[i] &= ~mask;
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}
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69
70
-
static inline int get_bit(uint32_t *tab, int index)
70
+
static inline int apic_get_bit(uint32_t *tab, int index)
71
71
{
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int i, mask;
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i = index >> 5;
···
81
81
int i;
82
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for (i = 7; i >= 0; i--) {
83
83
if (tab[i] != 0) {
84
-
return i * 32 + fls_bit(tab[i]);
84
+
return i * 32 + apic_fls_bit(tab[i]);
85
85
}
86
86
}
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87
return -1;
···
184
184
case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
187
-
reset_bit(s->irr, lvt & 0xff);
187
+
apic_reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
···
230
230
d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) {
232
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if (deliver_bitmask[i]) {
233
-
d = i * 32 + ffs_bit(deliver_bitmask[i]);
233
+
d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
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break;
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}
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}
···
386
386
387
387
static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
388
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{
389
-
apic_report_irq_delivered(!get_bit(s->irr, vector_num));
389
+
apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
390
390
391
-
set_bit(s->irr, vector_num);
391
+
apic_set_bit(s->irr, vector_num);
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if (trigger_mode)
393
-
set_bit(s->tmr, vector_num);
393
+
apic_set_bit(s->tmr, vector_num);
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else
395
-
reset_bit(s->tmr, vector_num);
395
+
apic_reset_bit(s->tmr, vector_num);
396
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if (s->vapic_paddr) {
397
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apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
398
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/*
···
412
412
isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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return;
415
-
reset_bit(s->isr, isrv);
416
-
if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
415
+
apic_reset_bit(s->isr, isrv);
416
+
if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
417
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ioapic_eoi_broadcast(isrv);
418
418
}
419
419
apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
···
452
452
int idx = apic_find_dest(dest);
453
453
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
454
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if (idx >= 0)
455
-
set_bit(deliver_bitmask, idx);
455
+
apic_set_bit(deliver_bitmask, idx);
456
456
}
457
457
} else {
458
458
/* XXX: cluster mode */
···
462
462
if (apic_iter) {
463
463
if (apic_iter->dest_mode == 0xf) {
464
464
if (dest & apic_iter->log_dest)
465
-
set_bit(deliver_bitmask, i);
465
+
apic_set_bit(deliver_bitmask, i);
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466
} else if (apic_iter->dest_mode == 0x0) {
467
467
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
468
468
(dest & apic_iter->log_dest & 0x0f)) {
469
-
set_bit(deliver_bitmask, i);
469
+
apic_set_bit(deliver_bitmask, i);
470
470
}
471
471
}
472
472
} else {
···
509
509
break;
510
510
case 1:
511
511
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
512
-
set_bit(deliver_bitmask, s->idx);
512
+
apic_set_bit(deliver_bitmask, s->idx);
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513
break;
514
514
case 2:
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515
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
516
516
break;
517
517
case 3:
518
518
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
519
-
reset_bit(deliver_bitmask, s->idx);
519
+
apic_reset_bit(deliver_bitmask, s->idx);
520
520
break;
521
521
}
522
522
···
573
573
apic_sync_vapic(s, SYNC_TO_VAPIC);
574
574
return s->spurious_vec & 0xff;
575
575
}
576
-
reset_bit(s->irr, intno);
577
-
set_bit(s->isr, intno);
576
+
apic_reset_bit(s->irr, intno);
577
+
apic_set_bit(s->isr, intno);
578
578
apic_sync_vapic(s, SYNC_TO_VAPIC);
579
579
580
580
/* re-inject if there is still a pending PIC interrupt */