+2

include/block/raw-aio.h

··· 12 12 * Contributions after 2012-01-13 are licensed under the terms of the 13 13 * GNU GPL, version 2 or (at your option) any later version. 14 14 */ 15 15 + 15 16 #ifndef QEMU_RAW_AIO_H 16 17 #define QEMU_RAW_AIO_H 17 18 19 19 + #include "block/aio.h" 18 20 #include "qemu/coroutine.h" 19 21 #include "qemu/iov.h" 20 22

+2

include/block/write-threshold.h

··· 9 9 * This work is licensed under the terms of the GNU LGPL, version 2 or later. 10 10 * See the COPYING.LIB file in the top-level directory. 11 11 */ 12 12 + 12 13 #ifndef BLOCK_WRITE_THRESHOLD_H 13 14 #define BLOCK_WRITE_THRESHOLD_H 14 15 16 16 + #include "block/block_int.h" 15 17 16 18 /* 17 19 * bdrv_write_threshold_set:

+1

include/disas/disas.h

··· 1 1 #ifndef QEMU_DISAS_H 2 2 #define QEMU_DISAS_H 3 3 4 4 + #include "exec/hwaddr.h" 4 5 5 6 #ifdef NEED_CPU_H 6 7 #include "cpu.h"

+3

include/exec/cputlb.h

··· 16 16 * You should have received a copy of the GNU Lesser General Public 17 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 18 */ 19 19 + 19 20 #ifndef CPUTLB_H 20 21 #define CPUTLB_H 22 22 + 23 23 + #include "exec/cpu-common.h" 21 24 22 25 #if !defined(CONFIG_USER_ONLY) 23 26 /* cputlb.c */

+1

include/exec/exec-all.h

··· 20 20 #ifndef EXEC_ALL_H 21 21 #define EXEC_ALL_H 22 22 23 23 + #include "cpu.h" 23 24 #include "exec/tb-context.h" 24 25 #include "sysemu/cpus.h" 25 26

+2

include/exec/ioport.h

··· 24 24 #ifndef IOPORT_H 25 25 #define IOPORT_H 26 26 27 27 + #include "exec/memory.h" 28 28 + 27 29 #define MAX_IOPORTS (64 * 1024) 28 30 #define IOPORTS_MASK (MAX_IOPORTS - 1) 29 31

+2

include/exec/memory-internal.h

··· 20 20 #ifndef MEMORY_INTERNAL_H 21 21 #define MEMORY_INTERNAL_H 22 22 23 23 + #include "cpu.h" 24 24 + 23 25 #ifndef CONFIG_USER_ONLY 24 26 static inline AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv) 25 27 {

+1

include/exec/ram_addr.h

··· 20 20 #define RAM_ADDR_H 21 21 22 22 #ifndef CONFIG_USER_ONLY 23 23 + #include "cpu.h" 23 24 #include "hw/xen/xen.h" 24 25 #include "sysemu/tcg.h" 25 26 #include "exec/ramlist.h"

+2

include/exec/softmmu-semi.h

··· 10 10 #ifndef SOFTMMU_SEMI_H 11 11 #define SOFTMMU_SEMI_H 12 12 13 13 + #include "cpu.h" 14 14 + 13 15 static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr) 14 16 { 15 17 uint64_t val;

+2

include/exec/tb-hash.h

··· 20 20 #ifndef EXEC_TB_HASH_H 21 21 #define EXEC_TB_HASH_H 22 22 23 23 + #include "exec/cpu-defs.h" 24 24 + #include "exec/exec-all.h" 23 25 #include "qemu/xxhash.h" 24 26 25 27 #ifdef CONFIG_SOFTMMU

+2

include/exec/user/thunk.h

··· 16 16 * You should have received a copy of the GNU Lesser General Public 17 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 18 */ 19 19 + 19 20 #ifndef THUNK_H 20 21 #define THUNK_H 21 22 22 23 #include "cpu.h" 24 24 + #include "exec/user/abitypes.h" 23 25 24 26 /* types enums definitions */ 25 27

+2

include/fpu/softfloat-macros.h

··· 82 82 #ifndef FPU_SOFTFLOAT_MACROS_H 83 83 #define FPU_SOFTFLOAT_MACROS_H 84 84 85 85 + #include "fpu/softfloat.h" 86 86 + 85 87 /*---------------------------------------------------------------------------- 86 88 | Shifts `a' right by the number of bits given in `count'. If any nonzero 87 89 | bits are shifted off, they are ``jammed'' into the least significant bit of

+3

include/hw/acpi/pci.h

··· 22 22 * You should have received a copy of the GNU General Public License along 23 23 * with this program; if not, see <http://www.gnu.org/licenses/>. 24 24 */ 25 25 + 25 26 #ifndef HW_ACPI_PCI_H 26 27 #define HW_ACPI_PCI_H 28 28 + 29 29 + #include "hw/acpi/bios-linker-loader.h" 27 30 28 31 typedef struct AcpiMcfgInfo { 29 32 uint64_t base;

+3

include/hw/acpi/tco.h

··· 6 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 7 * See the COPYING file in the top-level directory. 8 8 */ 9 9 + 9 10 #ifndef HW_ACPI_TCO_H 10 11 #define HW_ACPI_TCO_H 11 12 13 13 + #include "exec/memory.h" 14 14 + #include "migration/vmstate.h" 12 15 13 16 /* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */ 14 17 #define TCO_TICK_NSEC 600000000LL

+2

include/hw/adc/stm32f2xx_adc.h

··· 25 25 #ifndef HW_STM32F2XX_ADC_H 26 26 #define HW_STM32F2XX_ADC_H 27 27 28 28 + #include "hw/sysbus.h" 29 29 + 28 30 #define ADC_SR 0x00 29 31 #define ADC_CR1 0x04 30 32 #define ADC_CR2 0x08

+1

include/hw/arm/allwinner-a10.h

··· 11 11 #include "hw/ide/ahci.h" 12 12 13 13 #include "sysemu/sysemu.h" 14 14 + #include "target/arm/cpu.h" 14 15 15 16 16 17 #define AW_A10_PIC_REG_BASE 0x01c20400

+1

include/hw/arm/aspeed_soc.h

··· 22 22 #include "hw/ssi/aspeed_smc.h" 23 23 #include "hw/watchdog/wdt_aspeed.h" 24 24 #include "hw/net/ftgmac100.h" 25 25 + #include "target/arm/cpu.h" 25 26 26 27 #define ASPEED_SPIS_NUM 2 27 28 #define ASPEED_WDTS_NUM 3

+1

include/hw/arm/bcm2836.h

··· 13 13 14 14 #include "hw/arm/bcm2835_peripherals.h" 15 15 #include "hw/intc/bcm2836_control.h" 16 16 + #include "target/arm/cpu.h" 16 17 17 18 #define TYPE_BCM283X "bcm283x" 18 19 #define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)

+1 -2

include/hw/arm/exynos4210.h

··· 19 19 * 20 20 * You should have received a copy of the GNU General Public License along 21 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 22 - * 23 22 */ 24 23 25 24 #ifndef EXYNOS4210_H 26 25 #define EXYNOS4210_H 27 26 28 28 - #include "exec/memory.h" 27 27 + #include "hw/sysbus.h" 29 28 #include "target/arm/cpu-qom.h" 30 29 31 30 #define EXYNOS4210_NCPUS 2

+1

include/hw/arm/fsl-imx25.h

··· 27 27 #include "hw/i2c/imx_i2c.h" 28 28 #include "hw/gpio/imx_gpio.h" 29 29 #include "exec/memory.h" 30 30 + #include "target/arm/cpu.h" 30 31 31 32 #define TYPE_FSL_IMX25 "fsl,imx25" 32 33 #define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)

+1

include/hw/arm/fsl-imx31.h

··· 26 26 #include "hw/i2c/imx_i2c.h" 27 27 #include "hw/gpio/imx_gpio.h" 28 28 #include "exec/memory.h" 29 29 + #include "target/arm/cpu.h" 29 30 30 31 #define TYPE_FSL_IMX31 "fsl,imx31" 31 32 #define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)

+3

include/hw/arm/sharpsl.h

··· 3 3 * 4 4 * This file is licensed under the GNU GPL. 5 5 */ 6 6 + 6 7 #ifndef QEMU_SHARPSL_H 7 8 #define QEMU_SHARPSL_H 9 9 + 10 10 + #include "exec/hwaddr.h" 8 11 9 12 #define zaurus_printf(format, ...) \ 10 13 fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)

+1

include/hw/arm/xlnx-zynqmp.h

··· 32 32 #include "hw/intc/xlnx-zynqmp-ipi.h" 33 33 #include "hw/timer/xlnx-zynqmp-rtc.h" 34 34 #include "hw/cpu/cluster.h" 35 35 + #include "target/arm/cpu.h" 35 36 36 37 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 37 38 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \

+2

include/hw/block/fdc.h

··· 1 1 #ifndef HW_FDC_H 2 2 #define HW_FDC_H 3 3 4 4 + #include "exec/hwaddr.h" 5 5 + #include "hw/irq.h" 4 6 #include "qapi/qapi-types-block.h" 5 7 6 8 /* fdc.c */

+1

include/hw/block/flash.h

··· 4 4 /* NOR flash devices */ 5 5 6 6 #include "exec/memory.h" 7 7 + #include "migration/vmstate.h" 7 8 8 9 /* pflash_cfi01.c */ 9 10

+1

include/hw/char/escc.h

··· 3 3 4 4 #include "chardev/char-fe.h" 5 5 #include "chardev/char-serial.h" 6 6 + #include "hw/sysbus.h" 6 7 #include "ui/input.h" 7 8 8 9 /* escc.c */

+2

include/hw/char/xilinx_uartlite.h

··· 15 15 #ifndef XILINX_UARTLITE_H 16 16 #define XILINX_UARTLITE_H 17 17 18 18 + #include "hw/sysbus.h" 19 19 + 18 20 static inline DeviceState *xilinx_uartlite_create(hwaddr addr, 19 21 qemu_irq irq, 20 22 Chardev *chr)

+1

include/hw/core/generic-loader.h

··· 19 19 #define GENERIC_LOADER_H 20 20 21 21 #include "elf.h" 22 22 + #include "hw/qdev-core.h" 22 23 23 24 typedef struct GenericLoaderState { 24 25 /* <private> */

+1

include/hw/cris/etraxfs.h

··· 27 27 28 28 #include "net/net.h" 29 29 #include "hw/cris/etraxfs_dma.h" 30 30 + #include "hw/sysbus.h" 30 31 31 32 /* Instantiate an ETRAXFS Ethernet MAC. */ 32 33 static inline DeviceState *

+3

include/hw/cris/etraxfs_dma.h

··· 1 1 #ifndef HW_ETRAXFS_DMA_H 2 2 #define HW_ETRAXFS_DMA_H 3 3 4 4 + #include "exec/hwaddr.h" 5 5 + #include "hw/irq.h" 6 6 + 4 7 struct dma_context_metadata { 5 8 /* data descriptor md */ 6 9 uint16_t metadata;

+1

include/hw/display/i2c-ddc.h

··· 20 20 #define I2C_DDC_H 21 21 22 22 #include "hw/display/edid.h" 23 23 + #include "hw/i2c/i2c.h" 23 24 24 25 /* A simple I2C slave which just returns the contents of its EDID blob. */ 25 26 struct I2CDDCState {

+2

include/hw/empty_slot.h

··· 1 1 #ifndef HW_EMPTY_SLOT_H 2 2 #define HW_EMPTY_SLOT_H 3 3 4 4 + #include "exec/hwaddr.h" 5 5 + 4 6 /* empty_slot.c */ 5 7 void empty_slot_init(hwaddr addr, uint64_t slot_size); 6 8

+1

include/hw/gpio/bcm2835_gpio.h

··· 15 15 #define BCM2835_GPIO_H 16 16 17 17 #include "hw/sd/sd.h" 18 18 + #include "hw/sysbus.h" 18 19 19 20 typedef struct BCM2835GpioState { 20 21 SysBusDevice parent_obj;

+2

include/hw/i2c/aspeed_i2c.h

··· 17 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 19 */ 20 20 + 20 21 #ifndef ASPEED_I2C_H 21 22 #define ASPEED_I2C_H 22 23 23 24 #include "hw/i2c/i2c.h" 25 25 + #include "hw/sysbus.h" 24 26 25 27 #define TYPE_ASPEED_I2C "aspeed.i2c" 26 28 #define ASPEED_I2C(obj) \

+1

include/hw/i386/apic_internal.h

··· 24 24 #include "cpu.h" 25 25 #include "exec/memory.h" 26 26 #include "qemu/timer.h" 27 27 + #include "target/i386/cpu-qom.h" 27 28 28 29 /* APIC Local Vector Table */ 29 30 #define APIC_LVT_TIMER 0

+1

include/hw/i386/ioapic_internal.h

··· 24 24 25 25 #include "hw/hw.h" 26 26 #include "exec/memory.h" 27 27 + #include "hw/i386/ioapic.h" 27 28 #include "hw/sysbus.h" 28 29 #include "qemu/notify.h" 29 30

+2

include/hw/intc/allwinner-a10-pic.h

··· 1 1 #ifndef ALLWINNER_A10_PIC_H 2 2 #define ALLWINNER_A10_PIC_H 3 3 4 4 + #include "hw/sysbus.h" 5 5 + 4 6 #define TYPE_AW_A10_PIC "allwinner-a10-pic" 5 7 #define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC) 6 8

+2

include/hw/intc/heathrow_pic.h

··· 26 26 #ifndef HW_INTC_HEATHROW_PIC_H 27 27 #define HW_INTC_HEATHROW_PIC_H 28 28 29 29 + #include "hw/sysbus.h" 30 30 + 29 31 #define TYPE_HEATHROW "heathrow" 30 32 #define HEATHROW(obj) OBJECT_CHECK(HeathrowState, (obj), TYPE_HEATHROW) 31 33

+1

include/hw/intc/mips_gic.h

··· 13 13 14 14 #include "qemu/units.h" 15 15 #include "hw/timer/mips_gictimer.h" 16 16 + #include "hw/sysbus.h" 16 17 #include "cpu.h" 17 18 /* 18 19 * GIC Specific definitions

+2

include/hw/isa/vt82c686.h

··· 1 1 #ifndef HW_VT82C686_H 2 2 #define HW_VT82C686_H 3 3 4 4 + #include "hw/irq.h" 5 5 + 4 6 #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" 5 7 6 8 /* vt82c686.c */

+1

include/hw/mips/cps.h

··· 25 25 #include "hw/intc/mips_gic.h" 26 26 #include "hw/misc/mips_cpc.h" 27 27 #include "hw/misc/mips_itu.h" 28 28 + #include "target/mips/cpu.h" 28 29 29 30 #define TYPE_MIPS_CPS "mips-cps" 30 31 #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)

+2

include/hw/misc/macio/cuda.h

··· 26 26 #ifndef CUDA_H 27 27 #define CUDA_H 28 28 29 29 + #include "hw/misc/mos6522.h" 30 30 + 29 31 /* CUDA commands (2nd byte) */ 30 32 #define CUDA_WARM_START 0x0 31 33 #define CUDA_AUTOPOLL 0x1

+3

include/hw/misc/macio/gpio.h

··· 26 26 #ifndef MACIO_GPIO_H 27 27 #define MACIO_GPIO_H 28 28 29 29 + #include "hw/ppc/openpic.h" 30 30 + #include "hw/sysbus.h" 31 31 + 29 32 #define TYPE_MACIO_GPIO "macio-gpio" 30 33 #define MACIO_GPIO(obj) OBJECT_CHECK(MacIOGPIOState, (obj), TYPE_MACIO_GPIO) 31 34

+2

include/hw/misc/macio/macio.h

··· 27 27 #define MACIO_H 28 28 29 29 #include "hw/char/escc.h" 30 30 + #include "hw/ide/internal.h" 30 31 #include "hw/intc/heathrow_pic.h" 31 32 #include "hw/misc/macio/cuda.h" 32 33 #include "hw/misc/macio/gpio.h" 33 34 #include "hw/misc/macio/pmu.h" 35 35 + #include "hw/ppc/mac.h" 34 36 #include "hw/ppc/mac_dbdma.h" 35 37 #include "hw/ppc/openpic.h" 36 38

+3

include/hw/misc/macio/pmu.h

··· 10 10 #ifndef PMU_H 11 11 #define PMU_H 12 12 13 13 + #include "hw/misc/mos6522.h" 14 14 + #include "hw/misc/macio/gpio.h" 15 15 + 13 16 /* 14 17 * PMU commands 15 18 */

+2

include/hw/misc/mips_cmgcr.h

··· 10 10 #ifndef MIPS_CMGCR_H 11 11 #define MIPS_CMGCR_H 12 12 13 13 + #include "hw/sysbus.h" 14 14 + 13 15 #define TYPE_MIPS_GCR "mips-gcr" 14 16 #define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR) 15 17

+2

include/hw/misc/mips_cpc.h

··· 20 20 #ifndef MIPS_CPC_H 21 21 #define MIPS_CPC_H 22 22 23 23 + #include "hw/sysbus.h" 24 24 + 23 25 #define CPC_ADDRSPACE_SZ 0x6000 24 26 25 27 /* CPC blocks offsets relative to base address */

+3

include/hw/misc/pvpanic.h

··· 11 11 * See the COPYING file in the top-level directory. 12 12 * 13 13 */ 14 14 + 14 15 #ifndef HW_MISC_PVPANIC_H 15 16 #define HW_MISC_PVPANIC_H 17 17 + 18 18 + #include "qom/object.h" 16 19 17 20 #define TYPE_PVPANIC "pvpanic" 18 21

+1

include/hw/net/allwinner_emac.h

··· 27 27 #include "net/net.h" 28 28 #include "qemu/fifo8.h" 29 29 #include "hw/net/mii.h" 30 30 + #include "hw/sysbus.h" 30 31 31 32 #define TYPE_AW_EMAC "allwinner-emac" 32 33 #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)

+1

include/hw/net/lance.h

··· 31 31 32 32 #include "net/net.h" 33 33 #include "hw/net/pcnet.h" 34 34 + #include "hw/sysbus.h" 34 35 35 36 #define TYPE_LANCE "lance" 36 37 #define SYSBUS_PCNET(obj) \

+2

include/hw/nvram/chrp_nvram.h

··· 18 18 #ifndef CHRP_NVRAM_H 19 19 #define CHRP_NVRAM_H 20 20 21 21 + #include "qemu/bswap.h" 22 22 + 21 23 /* OpenBIOS NVRAM partition */ 22 24 typedef struct { 23 25 uint8_t signature;

+2

include/hw/pci-host/sabre.h

··· 1 1 #ifndef HW_PCI_HOST_SABRE_H 2 2 #define HW_PCI_HOST_SABRE_H 3 3 4 4 + #include "hw/pci/pci.h" 5 5 + #include "hw/pci/pci_host.h" 4 6 #include "hw/sparc/sun4u_iommu.h" 5 7 6 8 #define MAX_IVEC 0x40

+1 -1

include/hw/pci-host/uninorth.h

··· 26 26 #define UNINORTH_H 27 27 28 28 #include "hw/hw.h" 29 29 - 29 29 + #include "hw/pci/pci_host.h" 30 30 #include "hw/ppc/openpic.h" 31 31 32 32 /* UniNorth version */

+1

include/hw/pci/pcie_aer.h

··· 22 22 #define QEMU_PCIE_AER_H 23 23 24 24 #include "hw/hw.h" 25 25 + #include "hw/pci/pci_regs.h" 25 26 26 27 /* definitions which PCIExpressDevice uses */ 27 28

+1

include/hw/ppc/pnv_core.h

··· 21 21 #define PPC_PNV_CORE_H 22 22 23 23 #include "hw/cpu/core.h" 24 24 + #include "target/ppc/cpu.h" 24 25 25 26 #define TYPE_PNV_CORE "powernv-cpu-core" 26 27 #define PNV_CORE(obj) \

+4

include/hw/ppc/ppc4xx.h

··· 25 25 #ifndef PPC4XX_H 26 26 #define PPC4XX_H 27 27 28 28 + #include "hw/ppc/ppc.h" 29 29 + #include "exec/cpu-common.h" 30 30 + #include "exec/memory.h" 31 31 + 28 32 /* PowerPC 4xx core initialization */ 29 33 PowerPCCPU *ppc4xx_init(const char *cpu_model, 30 34 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,

+3

include/hw/ppc/spapr_irq.h

··· 10 10 #ifndef HW_SPAPR_IRQ_H 11 11 #define HW_SPAPR_IRQ_H 12 12 13 13 + #include "hw/irq.h" 14 14 + #include "target/ppc/cpu-qom.h" 15 15 + 13 16 /* 14 17 * IRQ range offsets per device type 15 18 */

+1

include/hw/ppc/spapr_vio.h

··· 22 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 23 */ 24 24 25 25 + #include "hw/ppc/spapr.h" 25 26 #include "sysemu/dma.h" 26 27 27 28 #define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device"

+2

include/hw/ppc/spapr_xive.h

··· 10 10 #ifndef PPC_SPAPR_XIVE_H 11 11 #define PPC_SPAPR_XIVE_H 12 12 13 13 + #include "hw/ppc/spapr_irq.h" 13 14 #include "hw/ppc/xive.h" 15 15 + #include "sysemu/sysemu.h" 14 16 15 17 #define TYPE_SPAPR_XIVE "spapr-xive" 16 18 #define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)

+3

include/hw/ppc/xive_regs.h

··· 16 16 #ifndef PPC_XIVE_REGS_H 17 17 #define PPC_XIVE_REGS_H 18 18 19 19 + #include "qemu/bswap.h" 20 20 + #include "qemu/host-utils.h" 21 21 + 19 22 /* 20 23 * Interrupt source number encoding on PowerBUS 21 24 */

+2

include/hw/riscv/boot.h

··· 20 20 #ifndef RISCV_BOOT_H 21 21 #define RISCV_BOOT_H 22 22 23 23 + #include "exec/cpu-defs.h" 24 24 + 23 25 void riscv_find_and_load_firmware(MachineState *machine, 24 26 const char *default_machine_firmware, 25 27 hwaddr firmware_load_addr);

+3

include/hw/riscv/riscv_hart.h

··· 21 21 #ifndef HW_RISCV_HART_H 22 22 #define HW_RISCV_HART_H 23 23 24 24 + #include "hw/sysbus.h" 25 25 + #include "target/riscv/cpu.h" 26 26 + 24 27 #define TYPE_RISCV_HART_ARRAY "riscv.hart_array" 25 28 26 29 #define RISCV_HART_ARRAY(obj) \

+2

include/hw/riscv/sifive_clint.h

··· 20 20 #ifndef HW_SIFIVE_CLINT_H 21 21 #define HW_SIFIVE_CLINT_H 22 22 23 23 + #include "hw/sysbus.h" 24 24 + 23 25 #define TYPE_SIFIVE_CLINT "riscv.sifive.clint" 24 26 25 27 #define SIFIVE_CLINT(obj) \

+1

include/hw/riscv/sifive_e.h

··· 19 19 #ifndef HW_SIFIVE_E_H 20 20 #define HW_SIFIVE_E_H 21 21 22 22 + #include "hw/riscv/riscv_hart.h" 22 23 #include "hw/riscv/sifive_gpio.h" 23 24 24 25 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"

+1 -1

include/hw/riscv/sifive_plic.h

··· 21 21 #ifndef HW_SIFIVE_PLIC_H 22 22 #define HW_SIFIVE_PLIC_H 23 23 24 24 - #include "hw/irq.h" 24 24 + #include "hw/sysbus.h" 25 25 26 26 #define TYPE_SIFIVE_PLIC "riscv.sifive.plic" 27 27

+2

include/hw/riscv/sifive_prci.h

··· 19 19 #ifndef HW_SIFIVE_PRCI_H 20 20 #define HW_SIFIVE_PRCI_H 21 21 22 22 + #include "hw/sysbus.h" 23 23 + 22 24 enum { 23 25 SIFIVE_PRCI_HFROSCCFG = 0x0, 24 26 SIFIVE_PRCI_HFXOSCCFG = 0x4,

+2

include/hw/riscv/sifive_test.h

··· 19 19 #ifndef HW_SIFIVE_TEST_H 20 20 #define HW_SIFIVE_TEST_H 21 21 22 22 + #include "hw/sysbus.h" 23 23 + 22 24 #define TYPE_SIFIVE_TEST "riscv.sifive.test" 23 25 24 26 #define SIFIVE_TEST(obj) \

+1

include/hw/riscv/sifive_u.h

··· 20 20 #define HW_SIFIVE_U_H 21 21 22 22 #include "hw/net/cadence_gem.h" 23 23 + #include "hw/riscv/riscv_hart.h" 23 24 24 25 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" 25 26 #define RISCV_U_SOC(obj) \

+3

include/hw/riscv/sifive_uart.h

··· 20 20 #ifndef HW_SIFIVE_UART_H 21 21 #define HW_SIFIVE_UART_H 22 22 23 23 + #include "chardev/char-fe.h" 24 24 + #include "hw/sysbus.h" 25 25 + 23 26 enum { 24 27 SIFIVE_UART_TXFIFO = 0, 25 28 SIFIVE_UART_RXFIFO = 4,

+3

include/hw/riscv/spike.h

··· 19 19 #ifndef HW_RISCV_SPIKE_H 20 20 #define HW_RISCV_SPIKE_H 21 21 22 22 + #include "hw/riscv/riscv_hart.h" 23 23 + #include "hw/sysbus.h" 24 24 + 22 25 typedef struct { 23 26 /*< private >*/ 24 27 SysBusDevice parent_obj;

+3

include/hw/riscv/virt.h

··· 19 19 #ifndef HW_RISCV_VIRT_H 20 20 #define HW_RISCV_VIRT_H 21 21 22 22 + #include "hw/riscv/riscv_hart.h" 23 23 + #include "hw/sysbus.h" 24 24 + 22 25 typedef struct { 23 26 /*< private >*/ 24 27 SysBusDevice parent_obj;

+3

include/hw/s390x/ap-device.h

··· 7 7 * your option) any later version. See the COPYING file in the top-level 8 8 * directory. 9 9 */ 10 10 + 10 11 #ifndef HW_S390X_AP_DEVICE_H 11 12 #define HW_S390X_AP_DEVICE_H 13 13 + 14 14 + #include "hw/qdev-core.h" 12 15 13 16 #define AP_DEVICE_TYPE "ap-device" 14 17

+2 -1

include/hw/s390x/css-bridge.h

··· 12 12 13 13 #ifndef HW_S390X_CSS_BRIDGE_H 14 14 #define HW_S390X_CSS_BRIDGE_H 15 15 + 15 16 #include "qom/object.h" 16 16 - #include "hw/qdev-core.h" 17 17 + #include "hw/sysbus.h" 17 18 18 19 /* virtual css bridge */ 19 20 typedef struct VirtualCssBridge {

+1

include/hw/s390x/css.h

··· 17 17 #include "hw/s390x/s390_flic.h" 18 18 #include "hw/s390x/ioinst.h" 19 19 #include "sysemu/kvm.h" 20 20 + #include "target/s390x/cpu-qom.h" 20 21 21 22 /* Channel subsystem constants. */ 22 23 #define MAX_DEVNO 65535

+1 -1

include/hw/s390x/tod.h

··· 12 12 #define HW_S390_TOD_H 13 13 14 14 #include "hw/qdev.h" 15 15 - #include "s390-tod.h" 15 15 + #include "target/s390x/s390-tod.h" 16 16 17 17 typedef struct S390TOD { 18 18 uint8_t high;

+2

include/hw/semihosting/console.h

··· 9 9 #ifndef SEMIHOST_CONSOLE_H 10 10 #define SEMIHOST_CONSOLE_H 11 11 12 12 + #include "cpu.h" 13 13 + 12 14 /** 13 15 * qemu_semihosting_console_outs: 14 16 * @env: CPUArchState

+1

include/hw/sh4/sh_intc.h

··· 1 1 #ifndef SH_INTC_H 2 2 #define SH_INTC_H 3 3 4 4 + #include "exec/memory.h" 4 5 #include "hw/irq.h" 5 6 6 7 typedef unsigned char intc_enum;

+2

include/hw/sparc/sparc64.h

··· 1 1 #ifndef HW_SPARC_SPARC64_H 2 2 #define HW_SPARC_SPARC64_H 3 3 4 4 + #include "target/sparc/cpu-qom.h" 5 5 + 4 6 #define IVEC_MAX 0x40 5 7 6 8 SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr);

+1

include/hw/ssi/aspeed_smc.h

··· 26 26 #define ASPEED_SMC_H 27 27 28 28 #include "hw/ssi/ssi.h" 29 29 + #include "hw/sysbus.h" 29 30 30 31 typedef struct AspeedSegments { 31 32 hwaddr addr;

+1

include/hw/ssi/xilinx_spips.h

··· 28 28 #include "hw/ssi/ssi.h" 29 29 #include "qemu/fifo32.h" 30 30 #include "hw/stream.h" 31 31 + #include "hw/sysbus.h" 31 32 32 33 typedef struct XilinxSPIPS XilinxSPIPS; 33 34

+1

include/hw/timer/allwinner-a10-pit.h

··· 2 2 #define ALLWINNER_A10_PIT_H 3 3 4 4 #include "hw/ptimer.h" 5 5 + #include "hw/sysbus.h" 5 6 6 7 #define TYPE_AW_A10_PIT "allwinner-A10-timer" 7 8 #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)

+1

include/hw/timer/i8254_internal.h

··· 27 27 28 28 #include "hw/hw.h" 29 29 #include "hw/isa/isa.h" 30 30 + #include "hw/timer/i8254.h" 30 31 #include "qemu/timer.h" 31 32 32 33 typedef struct PITChannelState {

+2

include/hw/timer/m48t59.h

··· 1 1 #ifndef HW_M48T59_H 2 2 #define HW_M48T59_H 3 3 4 4 + #include "exec/hwaddr.h" 5 5 + #include "hw/irq.h" 4 6 #include "qom/object.h" 5 7 6 8 #define TYPE_NVRAM "nvram"

+2

include/hw/timer/mc146818rtc_regs.h

··· 25 25 #ifndef MC146818RTC_REGS_H 26 26 #define MC146818RTC_REGS_H 27 27 28 28 + #include "qemu/timer.h" 29 29 + 28 30 #define RTC_ISA_IRQ 8 29 31 30 32 #define RTC_SECONDS 0

+1

include/hw/timer/xlnx-zynqmp-rtc.h

··· 28 28 #define HW_TIMER_XLNX_ZYNQMP_RTC_H 29 29 30 30 #include "hw/register.h" 31 31 + #include "hw/sysbus.h" 31 32 32 33 #define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc" 33 34

+1

include/hw/virtio/virtio-access.h

··· 16 16 #ifndef QEMU_VIRTIO_ACCESS_H 17 17 #define QEMU_VIRTIO_ACCESS_H 18 18 19 19 + #include "exec/hwaddr.h" 19 20 #include "hw/virtio/virtio.h" 20 21 #include "hw/virtio/virtio-bus.h" 21 22

+1

include/hw/virtio/virtio-gpu-bswap.h

··· 15 15 #define HW_VIRTIO_GPU_BSWAP_H 16 16 17 17 #include "qemu/bswap.h" 18 18 + #include "standard-headers/linux/virtio_gpu.h" 18 19 19 20 static inline void 20 21 virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr)

+1

include/hw/virtio/virtio-rng.h

··· 12 12 #ifndef QEMU_VIRTIO_RNG_H 13 13 #define QEMU_VIRTIO_RNG_H 14 14 15 15 + #include "hw/virtio/virtio.h" 15 16 #include "sysemu/rng.h" 16 17 #include "sysemu/rng-random.h" 17 18 #include "standard-headers/linux/virtio_rng.h"

+1

include/hw/watchdog/wdt_aspeed.h

··· 10 10 #ifndef WDT_ASPEED_H 11 11 #define WDT_ASPEED_H 12 12 13 13 + #include "hw/misc/aspeed_scu.h" 13 14 #include "hw/sysbus.h" 14 15 15 16 #define TYPE_ASPEED_WDT "aspeed.wdt"

+1

include/libdecnumber/decNumberLocal.h

··· 44 44 #define DECNLAUTHOR "Mike Cowlishaw" /* Who to blame */ 45 45 46 46 #include "libdecnumber/dconfig.h" 47 47 + #include "libdecnumber/decContext.h" 47 48 48 49 /* Conditional code flag -- set this to match hardware platform */ 49 50 /* 1=little-endian, 0=big-endian */

+3

include/migration/cpu.h

··· 1 1 /* Declarations for use for CPU state serialization. */ 2 2 + 2 3 #ifndef MIGRATION_CPU_H 3 4 #define MIGRATION_CPU_H 5 5 + 6 6 + #include "exec/cpu-defs.h" 4 7 5 8 #if TARGET_LONG_BITS == 64 6 9 #define qemu_put_betl qemu_put_be64

+2

include/monitor/hmp-target.h

··· 25 25 #ifndef MONITOR_HMP_TARGET_H 26 26 #define MONITOR_HMP_TARGET_H 27 27 28 28 + #include "cpu.h" 29 29 + 28 30 #define MD_TLONG 0 29 31 #define MD_I32 1 30 32

+2

include/qemu/atomic128.h

··· 13 13 #ifndef QEMU_ATOMIC128_H 14 14 #define QEMU_ATOMIC128_H 15 15 16 16 + #include "qemu/int128.h" 17 17 + 16 18 /* 17 19 * GCC is a house divided about supporting large atomic operations. 18 20 *

+2

include/qemu/ratelimit.h

··· 14 14 #ifndef QEMU_RATELIMIT_H 15 15 #define QEMU_RATELIMIT_H 16 16 17 17 + #include "qemu/timer.h" 18 18 + 17 19 typedef struct { 18 20 int64_t slice_start_time; 19 21 int64_t slice_end_time;

+1 -1

include/qemu/thread-win32.h

··· 47 47 }; 48 48 49 49 /* Only valid for joinable threads. */ 50 50 - HANDLE qemu_thread_get_handle(QemuThread *thread); 50 50 + HANDLE qemu_thread_get_handle(struct QemuThread *thread); 51 51 52 52 #endif

+1

include/sysemu/balloon.h

··· 14 14 #ifndef QEMU_BALLOON_H 15 15 #define QEMU_BALLOON_H 16 16 17 17 + #include "exec/cpu-common.h" 17 18 #include "qapi/qapi-types-misc.h" 18 19 19 20 typedef void (QEMUBalloonEvent)(void *opaque, ram_addr_t target);

+3

include/sysemu/cryptodev-vhost-user.h

··· 20 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 21 * 22 22 */ 23 23 + 23 24 #ifndef CRYPTODEV_VHOST_USER_H 24 25 #define CRYPTODEV_VHOST_USER_H 26 26 + 27 27 + #include "sysemu/cryptodev-vhost.h" 25 28 26 29 #define VHOST_USER_MAX_AUTH_KEY_LEN 512 27 30 #define VHOST_USER_MAX_CIPHER_KEY_LEN 64

+1

include/sysemu/hvf.h

··· 13 13 #ifndef HVF_H 14 14 #define HVF_H 15 15 16 16 + #include "cpu.h" 16 17 #include "qemu/bitops.h" 17 18 #include "exec/memory.h" 18 19 #include "sysemu/accel.h"

+1

include/sysemu/iothread.h

··· 16 16 17 17 #include "block/aio.h" 18 18 #include "qemu/thread.h" 19 19 + #include "qom/object.h" 19 20 20 21 #define TYPE_IOTHREAD "iothread" 21 22

+2

include/sysemu/kvm_int.h

··· 9 9 #ifndef QEMU_KVM_INT_H 10 10 #define QEMU_KVM_INT_H 11 11 12 12 + #include "exec/cpu-common.h" 13 13 + #include "exec/memory.h" 12 14 #include "sysemu/sysemu.h" 13 15 #include "sysemu/accel.h" 14 16 #include "sysemu/kvm.h"

+2

include/sysemu/memory_mapping.h

··· 15 15 #define MEMORY_MAPPING_H 16 16 17 17 #include "qemu/queue.h" 18 18 + #include "exec/cpu-common.h" 19 19 + #include "exec/cpu-defs.h" 18 20 #include "exec/memory.h" 19 21 20 22 typedef struct GuestPhysBlock {

+2

include/sysemu/xen-mapcache.h

··· 9 9 #ifndef XEN_MAPCACHE_H 10 10 #define XEN_MAPCACHE_H 11 11 12 12 + #include "exec/cpu-common.h" 13 13 + 12 14 typedef hwaddr (*phys_offset_to_gaddr_t)(hwaddr phys_offset, 13 15 ram_addr_t size); 14 16 #ifdef CONFIG_XEN

+3

include/ui/egl-helpers.h

··· 4 4 #include <epoxy/gl.h> 5 5 #include <epoxy/egl.h> 6 6 #include <gbm.h> 7 7 + #include "qapi/qapi-types-ui.h" 8 8 + #include "ui/console.h" 9 9 + #include "ui/shader.h" 7 10 8 11 extern EGLDisplay *qemu_egl_display; 9 12 extern EGLConfig qemu_egl_config;

+1

include/ui/input.h

··· 2 2 #define INPUT_H 3 3 4 4 #include "qapi/qapi-types-ui.h" 5 5 + #include "qemu/notify.h" 5 6 6 7 #define INPUT_EVENT_MASK_KEY (1<<INPUT_EVENT_KIND_KEY) 7 8 #define INPUT_EVENT_MASK_BTN (1<<INPUT_EVENT_KIND_BTN)

+1

include/ui/spice-display.h

··· 18 18 #ifndef UI_SPICE_DISPLAY_H 19 19 #define UI_SPICE_DISPLAY_H 20 20 21 21 + #include <spice.h> 21 22 #include <spice/ipc_ring.h> 22 23 #include <spice/enums.h> 23 24 #include <spice/qxl_dev.h>

+1 -1

target/hppa/cpu.h

··· 22 22 23 23 #include "cpu-qom.h" 24 24 #include "exec/cpu-defs.h" 25 25 - 25 25 + #include "exec/memory.h" 26 26 27 27 /* PA-RISC 1.x processors have a strong memory model. */ 28 28 /* ??? While we do not yet implement PA-RISC 2.0, those processors have