+1 -1

hw/alpha/dp264.c

··· 181 181 mc->init = clipper_init; 182 182 mc->block_default_type = IF_IDE; 183 183 mc->max_cpus = 4; 184 184 - mc->is_default = 1; 184 184 + mc->is_default = true; 185 185 mc->default_cpu_type = ALPHA_CPU_TYPE_NAME("ev67"); 186 186 mc->default_ram_id = "ram"; 187 187 }

+1 -1

hw/cris/axis_dev88.c

··· 344 344 { 345 345 mc->desc = "AXIS devboard 88"; 346 346 mc->init = axisdev88_init; 347 347 - mc->is_default = 1; 347 347 + mc->is_default = true; 348 348 mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32"); 349 349 mc->default_ram_id = "axisdev88.ram"; 350 350 }

+1 -1

hw/hppa/machine.c

··· 290 290 mc->block_default_type = IF_SCSI; 291 291 mc->max_cpus = HPPA_MAX_CPUS; 292 292 mc->default_cpus = 1; 293 293 - mc->is_default = 1; 293 293 + mc->is_default = true; 294 294 mc->default_ram_size = 512 * MiB; 295 295 mc->default_boot_order = "cd"; 296 296 mc->default_ram_id = "ram";

+5 -5

hw/i386/pc_piix.c

··· 423 423 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 424 424 pc_i440fx_machine_options(m); 425 425 m->alias = "pc"; 426 426 - m->is_default = 1; 426 426 + m->is_default = true; 427 427 pcmc->default_cpu_version = 1; 428 428 } 429 429 ··· 434 434 { 435 435 pc_i440fx_5_0_machine_options(m); 436 436 m->alias = NULL; 437 437 - m->is_default = 0; 437 437 + m->is_default = false; 438 438 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 439 439 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 440 440 } ··· 446 446 { 447 447 pc_i440fx_4_2_machine_options(m); 448 448 m->alias = NULL; 449 449 - m->is_default = 0; 449 449 + m->is_default = false; 450 450 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 451 451 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 452 452 } ··· 459 459 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 460 460 pc_i440fx_4_1_machine_options(m); 461 461 m->alias = NULL; 462 462 - m->is_default = 0; 462 462 + m->is_default = false; 463 463 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 464 464 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 465 465 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); ··· 473 473 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 474 474 475 475 pc_i440fx_4_0_machine_options(m); 476 476 - m->is_default = 0; 476 476 + m->is_default = false; 477 477 pcmc->do_not_add_smb_acpi = true; 478 478 m->smbus_no_migration_support = true; 479 479 m->alias = NULL;

+1 -1

hw/lm32/lm32_boards.c

··· 295 295 296 296 mc->desc = "LatticeMico32 EVR32 eval system"; 297 297 mc->init = lm32_evr_init; 298 298 - mc->is_default = 1; 298 298 + mc->is_default = true; 299 299 mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); 300 300 mc->default_ram_size = 64 * MiB; 301 301 mc->default_ram_id = "lm32_evr.sdram";

+1 -1

hw/m68k/mcf5208.c

··· 350 350 { 351 351 mc->desc = "MCF5208EVB"; 352 352 mc->init = mcf5208evb_init; 353 353 - mc->is_default = 1; 353 353 + mc->is_default = true; 354 354 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 355 355 mc->default_ram_id = "mcf5208.ram"; 356 356 }

+1 -1

hw/microblaze/petalogix_s3adsp1800_mmu.c

··· 132 132 { 133 133 mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; 134 134 mc->init = petalogix_s3adsp1800_init; 135 135 - mc->is_default = 1; 135 135 + mc->is_default = true; 136 136 } 137 137 138 138 DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init)

+1 -1

hw/mips/mips_malta.c

··· 1439 1439 mc->init = mips_malta_init; 1440 1440 mc->block_default_type = IF_IDE; 1441 1441 mc->max_cpus = 16; 1442 1442 - mc->is_default = 1; 1442 1442 + mc->is_default = true; 1443 1443 #ifdef TARGET_MIPS64 1444 1444 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); 1445 1445 #else

+1 -1

hw/moxie/moxiesim.c

··· 150 150 { 151 151 mc->desc = "Moxie simulator platform"; 152 152 mc->init = moxiesim_init; 153 153 - mc->is_default = 1; 153 153 + mc->is_default = true; 154 154 mc->default_cpu_type = MOXIE_CPU_TYPE_NAME("MoxieLite"); 155 155 } 156 156

+1 -1

hw/nios2/10m50_devboard.c

··· 120 120 { 121 121 mc->desc = "Altera 10M50 GHRD Nios II design"; 122 122 mc->init = nios2_10m50_ghrd_init; 123 123 - mc->is_default = 1; 123 123 + mc->is_default = true; 124 124 } 125 125 126 126 DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);

+1 -1

hw/openrisc/openrisc_sim.c

··· 176 176 mc->desc = "or1k simulation"; 177 177 mc->init = openrisc_sim_init; 178 178 mc->max_cpus = 2; 179 179 - mc->is_default = 1; 179 179 + mc->is_default = true; 180 180 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 181 181 } 182 182

+1 -1

hw/ppc/mac_oldworld.c

··· 435 435 mc->block_default_type = IF_IDE; 436 436 mc->max_cpus = MAX_CPUS; 437 437 #ifndef TARGET_PPC64 438 438 - mc->is_default = 1; 438 438 + mc->is_default = true; 439 439 #endif 440 440 /* TOFIX "cad" when Mac floppy is implemented */ 441 441 mc->default_boot_order = "cd";

+1 -1

hw/ppc/spapr.c

··· 4560 4560 static void spapr_machine_latest_class_options(MachineClass *mc) 4561 4561 { 4562 4562 mc->alias = "pseries"; 4563 4563 - mc->is_default = 1; 4563 4563 + mc->is_default = true; 4564 4564 } 4565 4565 4566 4566 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \

+1 -1

hw/riscv/spike.c

··· 448 448 mc->desc = "RISC-V Spike Board"; 449 449 mc->init = spike_board_init; 450 450 mc->max_cpus = 1; 451 451 - mc->is_default = 1; 451 451 + mc->is_default = true; 452 452 mc->default_cpu_type = SPIKE_V1_10_0_CPU; 453 453 } 454 454

+1 -1

hw/s390x/s390-virtio-ccw.c

··· 630 630 mc->desc = "VirtIO-ccw based S390 machine v" verstr; \ 631 631 if (latest) { \ 632 632 mc->alias = "s390-ccw-virtio"; \ 633 633 - mc->is_default = 1; \ 633 633 + mc->is_default = true; \ 634 634 } \ 635 635 } \ 636 636 static void ccw_machine_##suffix##_instance_init(Object *obj) \

+1 -1

hw/sh4/shix.c

··· 82 82 { 83 83 mc->desc = "shix card"; 84 84 mc->init = shix_init; 85 85 - mc->is_default = 1; 85 85 + mc->is_default = true; 86 86 mc->default_cpu_type = TYPE_SH7750R_CPU; 87 87 } 88 88

+1 -1

hw/sparc/sun4m.c

··· 1402 1402 mc->desc = "Sun4m platform, SPARCstation 5"; 1403 1403 mc->init = ss5_init; 1404 1404 mc->block_default_type = IF_SCSI; 1405 1405 - mc->is_default = 1; 1405 1405 + mc->is_default = true; 1406 1406 mc->default_boot_order = "c"; 1407 1407 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1408 1408 mc->default_display = "tcx";

+1 -1

hw/sparc64/sun4u.c

··· 816 816 mc->init = sun4u_init; 817 817 mc->block_default_type = IF_IDE; 818 818 mc->max_cpus = 1; /* XXX for now */ 819 819 - mc->is_default = 1; 819 819 + mc->is_default = true; 820 820 mc->default_boot_order = "c"; 821 821 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 822 822 mc->ignore_boot_device_suffixes = true;

+1 -1

hw/unicore32/puv3.c

··· 140 140 { 141 141 mc->desc = "PKUnity Version-3 based on UniCore32"; 142 142 mc->init = puv3_init; 143 143 - mc->is_default = 1; 143 143 + mc->is_default = true; 144 144 mc->default_cpu_type = UNICORE32_CPU_TYPE_NAME("UniCore-II"); 145 145 } 146 146

+3 -1

include/hw/boards.h

··· 81 81 * @max_cpus: maximum number of CPUs supported. Default: 1 82 82 * @min_cpus: minimum number of CPUs supported. Default: 1 83 83 * @default_cpus: number of CPUs instantiated if none are specified. Default: 1 84 84 + * @is_default: 85 85 + * If true QEMU will use this machine by default if no '-M' option is given. 84 86 * @get_hotplug_handler: this function is called during bus-less 85 87 * device hotplug. If defined it returns pointer to an instance 86 88 * of HotplugHandler object, which handles hotplug operation ··· 181 183 no_sdcard:1, 182 184 pci_allow_0_address:1, 183 185 legacy_fw_cfg_order:1; 184 184 - int is_default; 186 186 + bool is_default; 185 187 const char *default_machine_opts; 186 188 const char *default_boot_order; 187 189 const char *default_display;