jcs.org / qemu
qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/arm: Clear SVE high bits for FMOV

Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180502221552.3873-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 9a9f1f59521f46e8ff4527d9a2b52f83577e2aa3)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

authored by

Richard Henderson and committed by
Michael Roth e5af958d c708ce7d

+5 -12
+5 -12
target/arm/translate-a64.c
··· 5438 5438 5439 5439 if (itof) { 5440 5440 TCGv_i64 tcg_rn = cpu_reg(s, rn); 5441 + TCGv_i64 tmp; 5441 5442 5442 5443 switch (type) { 5443 5444 case 0: 5444 - { 5445 5445 /* 32 bit */ 5446 - TCGv_i64 tmp = tcg_temp_new_i64(); 5446 + tmp = tcg_temp_new_i64(); 5447 5447 tcg_gen_ext32u_i64(tmp, tcg_rn); 5448 - tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64)); 5449 - tcg_gen_movi_i64(tmp, 0); 5450 - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); 5448 + write_fp_dreg(s, rd, tmp); 5451 5449 tcg_temp_free_i64(tmp); 5452 5450 break; 5453 - } 5454 5451 case 1: 5455 - { 5456 5452 /* 64 bit */ 5457 - TCGv_i64 tmp = tcg_const_i64(0); 5458 - tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64)); 5459 - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); 5460 - tcg_temp_free_i64(tmp); 5453 + write_fp_dreg(s, rd, tcg_rn); 5461 5454 break; 5462 - } 5463 5455 case 2: 5464 5456 /* 64 bit to top half. */ 5465 5457 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); 5458 + clear_vec_high(s, true, rd); 5466 5459 break; 5467 5460 } 5468 5461 } else {