qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

hw/dma/xilinx_axidma: Add DMA memory-region property

Add DMA memory-region property to externally control what
address-space this DMA operates on.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200506082513.18751-5-edgar.iglesias@gmail.com>

+23 -7
+23 -7
hw/dma/xilinx_axidma.c
··· 33 33 #include "qemu/log.h" 34 34 #include "qemu/module.h" 35 35 36 + #include "sysemu/dma.h" 36 37 #include "hw/stream.h" 37 38 38 39 #define D(x) ··· 103 104 }; 104 105 105 106 struct Stream { 107 + struct XilinxAXIDMA *dma; 106 108 ptimer_state *ptimer; 107 109 qemu_irq irq; 108 110 ··· 125 127 struct XilinxAXIDMA { 126 128 SysBusDevice busdev; 127 129 MemoryRegion iomem; 130 + MemoryRegion *dma_mr; 131 + AddressSpace as; 132 + 128 133 uint32_t freqhz; 129 134 StreamSlave *tx_data_dev; 130 135 StreamSlave *tx_control_dev; ··· 186 191 { 187 192 struct SDesc *d = &s->desc; 188 193 189 - cpu_physical_memory_read(addr, d, sizeof *d); 194 + address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); 190 195 191 196 /* Convert from LE into host endianness. */ 192 197 d->buffer_address = le64_to_cpu(d->buffer_address); ··· 204 209 d->nxtdesc = cpu_to_le64(d->nxtdesc); 205 210 d->control = cpu_to_le32(d->control); 206 211 d->status = cpu_to_le32(d->status); 207 - cpu_physical_memory_write(addr, d, sizeof *d); 212 + address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, 213 + d, sizeof *d); 208 214 } 209 215 210 216 static void stream_update_irq(struct Stream *s) ··· 286 292 txlen + s->pos); 287 293 } 288 294 289 - cpu_physical_memory_read(s->desc.buffer_address, 290 - s->txbuf + s->pos, txlen); 295 + address_space_read(&s->dma->as, s->desc.buffer_address, 296 + MEMTXATTRS_UNSPECIFIED, 297 + s->txbuf + s->pos, txlen); 291 298 s->pos += txlen; 292 299 293 300 if (stream_desc_eof(&s->desc)) { ··· 336 343 rxlen = len; 337 344 } 338 345 339 - cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen); 346 + address_space_write(&s->dma->as, s->desc.buffer_address, 347 + MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen); 340 348 len -= rxlen; 341 349 pos += rxlen; 342 350 ··· 525 533 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( 526 534 &s->rx_control_dev); 527 535 Error *local_err = NULL; 536 + int i; 528 537 529 538 object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA, 530 539 (Object **)&ds->dma, ··· 545 554 goto xilinx_axidma_realize_fail; 546 555 } 547 556 548 - int i; 549 - 550 557 for (i = 0; i < 2; i++) { 551 558 struct Stream *st = &s->streams[i]; 552 559 560 + st->dma = s; 553 561 st->nr = i; 554 562 st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); 555 563 ptimer_transaction_begin(st->ptimer); 556 564 ptimer_set_freq(st->ptimer, s->freqhz); 557 565 ptimer_transaction_commit(st->ptimer); 558 566 } 567 + 568 + address_space_init(&s->as, 569 + s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 559 570 return; 560 571 561 572 xilinx_axidma_realize_fail: ··· 575 586 &s->rx_control_dev, sizeof(s->rx_control_dev), 576 587 TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort, 577 588 NULL); 589 + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 590 + (Object **)&s->dma_mr, 591 + qdev_prop_allow_set_link_before_realize, 592 + OBJ_PROP_LINK_STRONG, 593 + &error_abort); 578 594 579 595 sysbus_init_irq(sbd, &s->streams[0].irq); 580 596 sysbus_init_irq(sbd, &s->streams[1].irq);