Merge remote-tracking branch 'remotes/xtensa/tags/20180316-xtensa' into staging

+1 -1

MAINTAINERS

··· 289 289 290 290 Xtensa 291 291 M: Max Filippov <jcmvbkbc@gmail.com> 292 - W: http://wiki.osll.spb.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa 292 + W: http://wiki.osll.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa 293 293 S: Maintained 294 294 F: target/xtensa/ 295 295 F: hw/xtensa/

+1

configure

··· 6880 6880 ;; 6881 6881 xtensa|xtensaeb) 6882 6882 TARGET_ARCH=xtensa 6883 + mttcg="yes" 6883 6884 ;; 6884 6885 *) 6885 6886 error_exit "Unsupported target CPU"

+1

default-configs/xtensa-linux-user.mak

··· 1 + # Default configuration for xtensa-linux-user

+1

default-configs/xtensaeb-linux-user.mak

··· 1 + # Default configuration for xtensa-linux-user

+58

linux-user/elfload.c

··· 1273 1273 1274 1274 #endif /* TARGET_HPPA */ 1275 1275 1276 + #ifdef TARGET_XTENSA 1277 + 1278 + #define ELF_START_MMAP 0x20000000 1279 + 1280 + #define ELF_CLASS ELFCLASS32 1281 + #define ELF_ARCH EM_XTENSA 1282 + 1283 + static inline void init_thread(struct target_pt_regs *regs, 1284 + struct image_info *infop) 1285 + { 1286 + regs->windowbase = 0; 1287 + regs->windowstart = 1; 1288 + regs->areg[1] = infop->start_stack; 1289 + regs->pc = infop->entry; 1290 + } 1291 + 1292 + /* See linux kernel: arch/xtensa/include/asm/elf.h. */ 1293 + #define ELF_NREG 128 1294 + typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG]; 1295 + 1296 + enum { 1297 + TARGET_REG_PC, 1298 + TARGET_REG_PS, 1299 + TARGET_REG_LBEG, 1300 + TARGET_REG_LEND, 1301 + TARGET_REG_LCOUNT, 1302 + TARGET_REG_SAR, 1303 + TARGET_REG_WINDOWSTART, 1304 + TARGET_REG_WINDOWBASE, 1305 + TARGET_REG_THREADPTR, 1306 + TARGET_REG_AR0 = 64, 1307 + }; 1308 + 1309 + static void elf_core_copy_regs(target_elf_gregset_t *regs, 1310 + const CPUXtensaState *env) 1311 + { 1312 + unsigned i; 1313 + 1314 + (*regs)[TARGET_REG_PC] = tswapreg(env->pc); 1315 + (*regs)[TARGET_REG_PS] = tswapreg(env->sregs[PS] & ~PS_EXCM); 1316 + (*regs)[TARGET_REG_LBEG] = tswapreg(env->sregs[LBEG]); 1317 + (*regs)[TARGET_REG_LEND] = tswapreg(env->sregs[LEND]); 1318 + (*regs)[TARGET_REG_LCOUNT] = tswapreg(env->sregs[LCOUNT]); 1319 + (*regs)[TARGET_REG_SAR] = tswapreg(env->sregs[SAR]); 1320 + (*regs)[TARGET_REG_WINDOWSTART] = tswapreg(env->sregs[WINDOW_START]); 1321 + (*regs)[TARGET_REG_WINDOWBASE] = tswapreg(env->sregs[WINDOW_BASE]); 1322 + (*regs)[TARGET_REG_THREADPTR] = tswapreg(env->uregs[THREADPTR]); 1323 + xtensa_sync_phys_from_window((CPUXtensaState *)env); 1324 + for (i = 0; i < env->config->nareg; ++i) { 1325 + (*regs)[TARGET_REG_AR0 + i] = tswapreg(env->phys_regs[i]); 1326 + } 1327 + } 1328 + 1329 + #define USE_ELF_CORE_DUMP 1330 + #define ELF_EXEC_PAGESIZE 4096 1331 + 1332 + #endif /* TARGET_XTENSA */ 1333 + 1276 1334 #ifndef ELF_PLATFORM 1277 1335 #define ELF_PLATFORM (NULL) 1278 1336 #endif

+245

linux-user/main.c

··· 3841 3841 3842 3842 #endif /* TARGET_HPPA */ 3843 3843 3844 + #ifdef TARGET_XTENSA 3845 + 3846 + static void xtensa_rfw(CPUXtensaState *env) 3847 + { 3848 + xtensa_restore_owb(env); 3849 + env->pc = env->sregs[EPC1]; 3850 + } 3851 + 3852 + static void xtensa_rfwu(CPUXtensaState *env) 3853 + { 3854 + env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]); 3855 + xtensa_rfw(env); 3856 + } 3857 + 3858 + static void xtensa_rfwo(CPUXtensaState *env) 3859 + { 3860 + env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]); 3861 + xtensa_rfw(env); 3862 + } 3863 + 3864 + static void xtensa_overflow4(CPUXtensaState *env) 3865 + { 3866 + put_user_ual(env->regs[0], env->regs[5] - 16); 3867 + put_user_ual(env->regs[1], env->regs[5] - 12); 3868 + put_user_ual(env->regs[2], env->regs[5] - 8); 3869 + put_user_ual(env->regs[3], env->regs[5] - 4); 3870 + xtensa_rfwo(env); 3871 + } 3872 + 3873 + static void xtensa_underflow4(CPUXtensaState *env) 3874 + { 3875 + get_user_ual(env->regs[0], env->regs[5] - 16); 3876 + get_user_ual(env->regs[1], env->regs[5] - 12); 3877 + get_user_ual(env->regs[2], env->regs[5] - 8); 3878 + get_user_ual(env->regs[3], env->regs[5] - 4); 3879 + xtensa_rfwu(env); 3880 + } 3881 + 3882 + static void xtensa_overflow8(CPUXtensaState *env) 3883 + { 3884 + put_user_ual(env->regs[0], env->regs[9] - 16); 3885 + get_user_ual(env->regs[0], env->regs[1] - 12); 3886 + put_user_ual(env->regs[1], env->regs[9] - 12); 3887 + put_user_ual(env->regs[2], env->regs[9] - 8); 3888 + put_user_ual(env->regs[3], env->regs[9] - 4); 3889 + put_user_ual(env->regs[4], env->regs[0] - 32); 3890 + put_user_ual(env->regs[5], env->regs[0] - 28); 3891 + put_user_ual(env->regs[6], env->regs[0] - 24); 3892 + put_user_ual(env->regs[7], env->regs[0] - 20); 3893 + xtensa_rfwo(env); 3894 + } 3895 + 3896 + static void xtensa_underflow8(CPUXtensaState *env) 3897 + { 3898 + get_user_ual(env->regs[0], env->regs[9] - 16); 3899 + get_user_ual(env->regs[1], env->regs[9] - 12); 3900 + get_user_ual(env->regs[2], env->regs[9] - 8); 3901 + get_user_ual(env->regs[7], env->regs[1] - 12); 3902 + get_user_ual(env->regs[3], env->regs[9] - 4); 3903 + get_user_ual(env->regs[4], env->regs[7] - 32); 3904 + get_user_ual(env->regs[5], env->regs[7] - 28); 3905 + get_user_ual(env->regs[6], env->regs[7] - 24); 3906 + get_user_ual(env->regs[7], env->regs[7] - 20); 3907 + xtensa_rfwu(env); 3908 + } 3909 + 3910 + static void xtensa_overflow12(CPUXtensaState *env) 3911 + { 3912 + put_user_ual(env->regs[0], env->regs[13] - 16); 3913 + get_user_ual(env->regs[0], env->regs[1] - 12); 3914 + put_user_ual(env->regs[1], env->regs[13] - 12); 3915 + put_user_ual(env->regs[2], env->regs[13] - 8); 3916 + put_user_ual(env->regs[3], env->regs[13] - 4); 3917 + put_user_ual(env->regs[4], env->regs[0] - 48); 3918 + put_user_ual(env->regs[5], env->regs[0] - 44); 3919 + put_user_ual(env->regs[6], env->regs[0] - 40); 3920 + put_user_ual(env->regs[7], env->regs[0] - 36); 3921 + put_user_ual(env->regs[8], env->regs[0] - 32); 3922 + put_user_ual(env->regs[9], env->regs[0] - 28); 3923 + put_user_ual(env->regs[10], env->regs[0] - 24); 3924 + put_user_ual(env->regs[11], env->regs[0] - 20); 3925 + xtensa_rfwo(env); 3926 + } 3927 + 3928 + static void xtensa_underflow12(CPUXtensaState *env) 3929 + { 3930 + get_user_ual(env->regs[0], env->regs[13] - 16); 3931 + get_user_ual(env->regs[1], env->regs[13] - 12); 3932 + get_user_ual(env->regs[2], env->regs[13] - 8); 3933 + get_user_ual(env->regs[11], env->regs[1] - 12); 3934 + get_user_ual(env->regs[3], env->regs[13] - 4); 3935 + get_user_ual(env->regs[4], env->regs[11] - 48); 3936 + get_user_ual(env->regs[5], env->regs[11] - 44); 3937 + get_user_ual(env->regs[6], env->regs[11] - 40); 3938 + get_user_ual(env->regs[7], env->regs[11] - 36); 3939 + get_user_ual(env->regs[8], env->regs[11] - 32); 3940 + get_user_ual(env->regs[9], env->regs[11] - 28); 3941 + get_user_ual(env->regs[10], env->regs[11] - 24); 3942 + get_user_ual(env->regs[11], env->regs[11] - 20); 3943 + xtensa_rfwu(env); 3944 + } 3945 + 3946 + void cpu_loop(CPUXtensaState *env) 3947 + { 3948 + CPUState *cs = CPU(xtensa_env_get_cpu(env)); 3949 + target_siginfo_t info; 3950 + abi_ulong ret; 3951 + int trapnr; 3952 + 3953 + while (1) { 3954 + cpu_exec_start(cs); 3955 + trapnr = cpu_exec(cs); 3956 + cpu_exec_end(cs); 3957 + process_queued_cpu_work(cs); 3958 + 3959 + env->sregs[PS] &= ~PS_EXCM; 3960 + switch (trapnr) { 3961 + case EXCP_INTERRUPT: 3962 + break; 3963 + 3964 + case EXC_WINDOW_OVERFLOW4: 3965 + xtensa_overflow4(env); 3966 + break; 3967 + case EXC_WINDOW_UNDERFLOW4: 3968 + xtensa_underflow4(env); 3969 + break; 3970 + case EXC_WINDOW_OVERFLOW8: 3971 + xtensa_overflow8(env); 3972 + break; 3973 + case EXC_WINDOW_UNDERFLOW8: 3974 + xtensa_underflow8(env); 3975 + break; 3976 + case EXC_WINDOW_OVERFLOW12: 3977 + xtensa_overflow12(env); 3978 + break; 3979 + case EXC_WINDOW_UNDERFLOW12: 3980 + xtensa_underflow12(env); 3981 + break; 3982 + 3983 + case EXC_USER: 3984 + switch (env->sregs[EXCCAUSE]) { 3985 + case ILLEGAL_INSTRUCTION_CAUSE: 3986 + case PRIVILEGED_CAUSE: 3987 + info.si_signo = TARGET_SIGILL; 3988 + info.si_errno = 0; 3989 + info.si_code = 3990 + env->sregs[EXCCAUSE] == ILLEGAL_INSTRUCTION_CAUSE ? 3991 + TARGET_ILL_ILLOPC : TARGET_ILL_PRVOPC; 3992 + info._sifields._sigfault._addr = env->sregs[EPC1]; 3993 + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3994 + break; 3995 + 3996 + case SYSCALL_CAUSE: 3997 + env->pc += 3; 3998 + ret = do_syscall(env, env->regs[2], 3999 + env->regs[6], env->regs[3], 4000 + env->regs[4], env->regs[5], 4001 + env->regs[8], env->regs[9], 0, 0); 4002 + switch (ret) { 4003 + default: 4004 + env->regs[2] = ret; 4005 + break; 4006 + 4007 + case -TARGET_ERESTARTSYS: 4008 + case -TARGET_QEMU_ESIGRETURN: 4009 + break; 4010 + } 4011 + break; 4012 + 4013 + case ALLOCA_CAUSE: 4014 + env->sregs[PS] = deposit32(env->sregs[PS], 4015 + PS_OWB_SHIFT, 4016 + PS_OWB_LEN, 4017 + env->sregs[WINDOW_BASE]); 4018 + 4019 + switch (env->regs[0] & 0xc0000000) { 4020 + case 0x00000000: 4021 + case 0x40000000: 4022 + xtensa_rotate_window(env, -1); 4023 + xtensa_underflow4(env); 4024 + break; 4025 + 4026 + case 0x80000000: 4027 + xtensa_rotate_window(env, -2); 4028 + xtensa_underflow8(env); 4029 + break; 4030 + 4031 + case 0xc0000000: 4032 + xtensa_rotate_window(env, -3); 4033 + xtensa_underflow12(env); 4034 + break; 4035 + } 4036 + break; 4037 + 4038 + case INTEGER_DIVIDE_BY_ZERO_CAUSE: 4039 + info.si_signo = TARGET_SIGFPE; 4040 + info.si_errno = 0; 4041 + info.si_code = TARGET_FPE_INTDIV; 4042 + info._sifields._sigfault._addr = env->sregs[EPC1]; 4043 + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 4044 + break; 4045 + 4046 + case LOAD_PROHIBITED_CAUSE: 4047 + case STORE_PROHIBITED_CAUSE: 4048 + info.si_signo = TARGET_SIGSEGV; 4049 + info.si_errno = 0; 4050 + info.si_code = TARGET_SEGV_ACCERR; 4051 + info._sifields._sigfault._addr = env->sregs[EXCVADDR]; 4052 + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 4053 + break; 4054 + 4055 + default: 4056 + fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]); 4057 + g_assert_not_reached(); 4058 + } 4059 + break; 4060 + case EXCP_DEBUG: 4061 + trapnr = gdb_handlesig(cs, TARGET_SIGTRAP); 4062 + if (trapnr) { 4063 + info.si_signo = trapnr; 4064 + info.si_errno = 0; 4065 + info.si_code = TARGET_TRAP_BRKPT; 4066 + queue_signal(env, trapnr, QEMU_SI_FAULT, &info); 4067 + } 4068 + break; 4069 + case EXC_DEBUG: 4070 + default: 4071 + fprintf(stderr, "trapnr = %d\n", trapnr); 4072 + g_assert_not_reached(); 4073 + } 4074 + process_pending_signals(env); 4075 + } 4076 + } 4077 + 4078 + #endif /* TARGET_XTENSA */ 4079 + 3844 4080 __thread CPUState *thread_cpu; 3845 4081 3846 4082 bool qemu_cpu_is_self(CPUState *cpu) ··· 4872 5108 } 4873 5109 env->iaoq_f = regs->iaoq[0]; 4874 5110 env->iaoq_b = regs->iaoq[1]; 5111 + } 5112 + #elif defined(TARGET_XTENSA) 5113 + { 5114 + int i; 5115 + for (i = 0; i < 16; ++i) { 5116 + env->regs[i] = regs->areg[i]; 5117 + } 5118 + env->sregs[WINDOW_START] = regs->windowstart; 5119 + env->pc = regs->pc; 4875 5120 } 4876 5121 #else 4877 5122 #error unsupported target CPU

+255 -1

linux-user/signal.c

··· 7048 7048 return -TARGET_QEMU_ESIGRETURN; 7049 7049 } 7050 7050 7051 + #elif defined(TARGET_XTENSA) 7052 + 7053 + struct target_sigcontext { 7054 + abi_ulong sc_pc; 7055 + abi_ulong sc_ps; 7056 + abi_ulong sc_lbeg; 7057 + abi_ulong sc_lend; 7058 + abi_ulong sc_lcount; 7059 + abi_ulong sc_sar; 7060 + abi_ulong sc_acclo; 7061 + abi_ulong sc_acchi; 7062 + abi_ulong sc_a[16]; 7063 + abi_ulong sc_xtregs; 7064 + }; 7065 + 7066 + struct target_ucontext { 7067 + abi_ulong tuc_flags; 7068 + abi_ulong tuc_link; 7069 + target_stack_t tuc_stack; 7070 + struct target_sigcontext tuc_mcontext; 7071 + target_sigset_t tuc_sigmask; 7072 + }; 7073 + 7074 + struct target_rt_sigframe { 7075 + target_siginfo_t info; 7076 + struct target_ucontext uc; 7077 + /* TODO: xtregs */ 7078 + uint8_t retcode[6]; 7079 + abi_ulong window[4]; 7080 + }; 7081 + 7082 + static abi_ulong get_sigframe(struct target_sigaction *sa, 7083 + CPUXtensaState *env, 7084 + unsigned long framesize) 7085 + { 7086 + abi_ulong sp = env->regs[1]; 7087 + 7088 + /* This is the X/Open sanctioned signal stack switching. */ 7089 + if ((sa->sa_flags & TARGET_SA_ONSTACK) != 0 && !sas_ss_flags(sp)) { 7090 + sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size; 7091 + } 7092 + return (sp - framesize) & -16; 7093 + } 7094 + 7095 + static int flush_window_regs(CPUXtensaState *env) 7096 + { 7097 + const uint32_t nareg_mask = env->config->nareg - 1; 7098 + uint32_t wb = env->sregs[WINDOW_BASE]; 7099 + uint32_t ws = (xtensa_replicate_windowstart(env) >> (wb + 1)) & 7100 + ((1 << env->config->nareg / 4) - 1); 7101 + uint32_t d = ctz32(ws) + 1; 7102 + uint32_t sp; 7103 + abi_long ret = 0; 7104 + 7105 + wb += d; 7106 + ws >>= d; 7107 + 7108 + xtensa_sync_phys_from_window(env); 7109 + sp = env->phys_regs[(wb * 4 + 1) & nareg_mask]; 7110 + 7111 + while (ws && ret == 0) { 7112 + int d; 7113 + int i; 7114 + int idx; 7115 + 7116 + if (ws & 0x1) { 7117 + ws >>= 1; 7118 + d = 1; 7119 + } else if (ws & 0x2) { 7120 + ws >>= 2; 7121 + d = 2; 7122 + for (i = 0; i < 4; ++i) { 7123 + idx = (wb * 4 + 4 + i) & nareg_mask; 7124 + ret |= put_user_ual(env->phys_regs[idx], sp + (i - 12) * 4); 7125 + } 7126 + } else if (ws & 0x4) { 7127 + ws >>= 3; 7128 + d = 3; 7129 + for (i = 0; i < 8; ++i) { 7130 + idx = (wb * 4 + 4 + i) & nareg_mask; 7131 + ret |= put_user_ual(env->phys_regs[idx], sp + (i - 16) * 4); 7132 + } 7133 + } else { 7134 + g_assert_not_reached(); 7135 + } 7136 + sp = env->phys_regs[((wb + d) * 4 + 1) & nareg_mask]; 7137 + for (i = 0; i < 4; ++i) { 7138 + idx = (wb * 4 + i) & nareg_mask; 7139 + ret |= put_user_ual(env->phys_regs[idx], sp + (i - 4) * 4); 7140 + } 7141 + wb += d; 7142 + } 7143 + return ret == 0; 7144 + } 7145 + 7146 + static int setup_sigcontext(struct target_rt_sigframe *frame, 7147 + CPUXtensaState *env) 7148 + { 7149 + struct target_sigcontext *sc = &frame->uc.tuc_mcontext; 7150 + int i; 7151 + 7152 + __put_user(env->pc, &sc->sc_pc); 7153 + __put_user(env->sregs[PS], &sc->sc_ps); 7154 + __put_user(env->sregs[LBEG], &sc->sc_lbeg); 7155 + __put_user(env->sregs[LEND], &sc->sc_lend); 7156 + __put_user(env->sregs[LCOUNT], &sc->sc_lcount); 7157 + if (!flush_window_regs(env)) { 7158 + return 0; 7159 + } 7160 + for (i = 0; i < 16; ++i) { 7161 + __put_user(env->regs[i], sc->sc_a + i); 7162 + } 7163 + __put_user(0, &sc->sc_xtregs); 7164 + /* TODO: xtregs */ 7165 + return 1; 7166 + } 7167 + 7168 + static void setup_rt_frame(int sig, struct target_sigaction *ka, 7169 + target_siginfo_t *info, 7170 + target_sigset_t *set, CPUXtensaState *env) 7171 + { 7172 + abi_ulong frame_addr; 7173 + struct target_rt_sigframe *frame; 7174 + uint32_t ra; 7175 + int i; 7176 + 7177 + frame_addr = get_sigframe(ka, env, sizeof(*frame)); 7178 + trace_user_setup_rt_frame(env, frame_addr); 7179 + 7180 + if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { 7181 + goto give_sigsegv; 7182 + } 7183 + 7184 + if (ka->sa_flags & SA_SIGINFO) { 7185 + tswap_siginfo(&frame->info, info); 7186 + } 7187 + 7188 + __put_user(0, &frame->uc.tuc_flags); 7189 + __put_user(0, &frame->uc.tuc_link); 7190 + __put_user(target_sigaltstack_used.ss_sp, 7191 + &frame->uc.tuc_stack.ss_sp); 7192 + __put_user(sas_ss_flags(env->regs[1]), 7193 + &frame->uc.tuc_stack.ss_flags); 7194 + __put_user(target_sigaltstack_used.ss_size, 7195 + &frame->uc.tuc_stack.ss_size); 7196 + if (!setup_sigcontext(frame, env)) { 7197 + unlock_user_struct(frame, frame_addr, 0); 7198 + goto give_sigsegv; 7199 + } 7200 + for (i = 0; i < TARGET_NSIG_WORDS; ++i) { 7201 + __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); 7202 + } 7203 + 7204 + if (ka->sa_flags & TARGET_SA_RESTORER) { 7205 + ra = ka->sa_restorer; 7206 + } else { 7207 + ra = frame_addr + offsetof(struct target_rt_sigframe, retcode); 7208 + #ifdef TARGET_WORDS_BIGENDIAN 7209 + /* Generate instruction: MOVI a2, __NR_rt_sigreturn */ 7210 + __put_user(0x22, &frame->retcode[0]); 7211 + __put_user(0x0a, &frame->retcode[1]); 7212 + __put_user(TARGET_NR_rt_sigreturn, &frame->retcode[2]); 7213 + /* Generate instruction: SYSCALL */ 7214 + __put_user(0x00, &frame->retcode[3]); 7215 + __put_user(0x05, &frame->retcode[4]); 7216 + __put_user(0x00, &frame->retcode[5]); 7217 + #else 7218 + /* Generate instruction: MOVI a2, __NR_rt_sigreturn */ 7219 + __put_user(0x22, &frame->retcode[0]); 7220 + __put_user(0xa0, &frame->retcode[1]); 7221 + __put_user(TARGET_NR_rt_sigreturn, &frame->retcode[2]); 7222 + /* Generate instruction: SYSCALL */ 7223 + __put_user(0x00, &frame->retcode[3]); 7224 + __put_user(0x50, &frame->retcode[4]); 7225 + __put_user(0x00, &frame->retcode[5]); 7226 + #endif 7227 + } 7228 + env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); 7229 + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER)) { 7230 + env->sregs[PS] |= PS_WOE | (1 << PS_CALLINC_SHIFT); 7231 + } 7232 + memset(env->regs, 0, sizeof(env->regs)); 7233 + env->pc = ka->_sa_handler; 7234 + env->regs[1] = frame_addr; 7235 + env->sregs[WINDOW_BASE] = 0; 7236 + env->sregs[WINDOW_START] = 1; 7237 + 7238 + env->regs[4] = (ra & 0x3fffffff) | 0x40000000; 7239 + env->regs[6] = sig; 7240 + env->regs[7] = frame_addr + offsetof(struct target_rt_sigframe, info); 7241 + env->regs[8] = frame_addr + offsetof(struct target_rt_sigframe, uc); 7242 + unlock_user_struct(frame, frame_addr, 1); 7243 + return; 7244 + 7245 + give_sigsegv: 7246 + force_sigsegv(sig); 7247 + return; 7248 + } 7249 + 7250 + static void restore_sigcontext(CPUXtensaState *env, 7251 + struct target_rt_sigframe *frame) 7252 + { 7253 + struct target_sigcontext *sc = &frame->uc.tuc_mcontext; 7254 + uint32_t ps; 7255 + int i; 7256 + 7257 + __get_user(env->pc, &sc->sc_pc); 7258 + __get_user(ps, &sc->sc_ps); 7259 + __get_user(env->sregs[LBEG], &sc->sc_lbeg); 7260 + __get_user(env->sregs[LEND], &sc->sc_lend); 7261 + __get_user(env->sregs[LCOUNT], &sc->sc_lcount); 7262 + 7263 + env->sregs[WINDOW_BASE] = 0; 7264 + env->sregs[WINDOW_START] = 1; 7265 + env->sregs[PS] = deposit32(env->sregs[PS], 7266 + PS_CALLINC_SHIFT, 7267 + PS_CALLINC_LEN, 7268 + extract32(ps, PS_CALLINC_SHIFT, 7269 + PS_CALLINC_LEN)); 7270 + for (i = 0; i < 16; ++i) { 7271 + __get_user(env->regs[i], sc->sc_a + i); 7272 + } 7273 + /* TODO: xtregs */ 7274 + } 7275 + 7276 + long do_rt_sigreturn(CPUXtensaState *env) 7277 + { 7278 + abi_ulong frame_addr = env->regs[1]; 7279 + struct target_rt_sigframe *frame; 7280 + sigset_t set; 7281 + 7282 + trace_user_do_rt_sigreturn(env, frame_addr); 7283 + if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { 7284 + goto badframe; 7285 + } 7286 + target_to_host_sigset(&set, &frame->uc.tuc_sigmask); 7287 + set_sigmask(&set); 7288 + 7289 + restore_sigcontext(env, frame); 7290 + 7291 + if (do_sigaltstack(frame_addr + 7292 + offsetof(struct target_rt_sigframe, uc.tuc_stack), 7293 + 0, get_sp_from_cpustate(env)) == -TARGET_EFAULT) { 7294 + goto badframe; 7295 + } 7296 + unlock_user_struct(frame, frame_addr, 0); 7297 + return -TARGET_QEMU_ESIGRETURN; 7298 + 7299 + badframe: 7300 + unlock_user_struct(frame, frame_addr, 0); 7301 + force_sig(TARGET_SIGSEGV); 7302 + return -TARGET_QEMU_ESIGRETURN; 7303 + } 7304 + 7051 7305 #else 7052 7306 #error Target needs to add support for signal handling 7053 7307 #endif ··· 7126 7380 || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) \ 7127 7381 || defined(TARGET_PPC64) || defined(TARGET_HPPA) \ 7128 7382 || defined(TARGET_NIOS2) || defined(TARGET_X86_64) \ 7129 - || defined(TARGET_RISCV) 7383 + || defined(TARGET_RISCV) || defined(TARGET_XTENSA) 7130 7384 /* These targets do not have traditional signals. */ 7131 7385 setup_rt_frame(sig, sa, &k->info, &target_old_set, cpu_env); 7132 7386 #else

+2

linux-user/syscall.c

··· 709 709 return 0; 710 710 } 711 711 } 712 + #elif defined(TARGET_XTENSA) 713 + static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } 712 714 #else 713 715 static inline int regpairs_aligned(void *cpu_env, int num) { return 0; } 714 716 #endif

+62 -3

linux-user/syscall_defs.h

··· 71 71 || defined(TARGET_M68K) || defined(TARGET_CRIS) \ 72 72 || defined(TARGET_S390X) \ 73 73 || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) \ 74 - || defined(TARGET_NIOS2) || defined(TARGET_RISCV) 74 + || defined(TARGET_NIOS2) || defined(TARGET_RISCV) \ 75 + || defined(TARGET_XTENSA) 75 76 76 77 #define TARGET_IOC_SIZEBITS 14 77 78 #define TARGET_IOC_DIRBITS 2 ··· 423 424 || defined(TARGET_MICROBLAZE) \ 424 425 || defined(TARGET_S390X) || defined(TARGET_OPENRISC) \ 425 426 || defined(TARGET_TILEGX) || defined(TARGET_HPPA) || defined(TARGET_NIOS2) \ 426 - || defined(TARGET_RISCV) 427 + || defined(TARGET_RISCV) || defined(TARGET_XTENSA) 427 428 428 429 #if defined(TARGET_SPARC) 429 430 #define TARGET_SA_NOCLDSTOP 8u ··· 1379 1380 #define TARGET_MAP_NONBLOCK 0x20000 /* do not block on IO */ 1380 1381 #define TARGET_MAP_STACK 0x40000 /* ignored */ 1381 1382 #define TARGET_MAP_HUGETLB 0x80000 /* create a huge page mapping */ 1383 + #elif defined(TARGET_XTENSA) 1384 + #define TARGET_MAP_FIXED 0x10 /* Interpret addr exactly */ 1385 + #define TARGET_MAP_ANONYMOUS 0x0800 /* don't use a file */ 1386 + #define TARGET_MAP_GROWSDOWN 0x1000 /* stack-like segment */ 1387 + #define TARGET_MAP_DENYWRITE 0x2000 /* ETXTBSY */ 1388 + #define TARGET_MAP_EXECUTABLE 0x4000 /* mark it as an executable */ 1389 + #define TARGET_MAP_LOCKED 0x8000 /* pages are locked */ 1390 + #define TARGET_MAP_NORESERVE 0x0400 /* don't check for reservations */ 1391 + #define TARGET_MAP_POPULATE 0x10000 /* populate (prefault) pagetables */ 1392 + #define TARGET_MAP_NONBLOCK 0x20000 /* do not block on IO */ 1393 + #define TARGET_MAP_STACK 0x40000 1394 + #define TARGET_MAP_HUGETLB 0x80000 /* create a huge page mapping */ 1382 1395 #else 1383 1396 #define TARGET_MAP_FIXED 0x10 /* Interpret addr exactly */ 1384 1397 #define TARGET_MAP_ANONYMOUS 0x20 /* don't use a file */ ··· 2080 2093 abi_ulong target_st_ctime_nsec; 2081 2094 unsigned int __unused[2]; 2082 2095 }; 2096 + #elif defined(TARGET_XTENSA) 2097 + struct target_stat { 2098 + abi_ulong st_dev; 2099 + abi_ulong st_ino; 2100 + unsigned int st_mode; 2101 + unsigned int st_nlink; 2102 + unsigned int st_uid; 2103 + unsigned int st_gid; 2104 + abi_ulong st_rdev; 2105 + abi_long st_size; 2106 + abi_ulong st_blksize; 2107 + abi_ulong st_blocks; 2108 + abi_ulong target_st_atime; 2109 + abi_ulong target_st_atime_nsec; 2110 + abi_ulong target_st_mtime; 2111 + abi_ulong target_st_mtime_nsec; 2112 + abi_ulong target_st_ctime; 2113 + abi_ulong target_st_ctime_nsec; 2114 + abi_ulong __unused4; 2115 + abi_ulong __unused5; 2116 + }; 2117 + 2118 + #define TARGET_HAS_STRUCT_STAT64 2119 + struct target_stat64 { 2120 + uint64_t st_dev; /* Device */ 2121 + uint64_t st_ino; /* File serial number */ 2122 + unsigned int st_mode; /* File mode. */ 2123 + unsigned int st_nlink; /* Link count. */ 2124 + unsigned int st_uid; /* User ID of the file's owner. */ 2125 + unsigned int st_gid; /* Group ID of the file's group. */ 2126 + uint64_t st_rdev; /* Device number, if device. */ 2127 + int64_t st_size; /* Size of file, in bytes. */ 2128 + abi_ulong st_blksize; /* Optimal block size for I/O. */ 2129 + abi_ulong __unused2; 2130 + uint64_t st_blocks; /* Number 512-byte blocks allocated. */ 2131 + abi_ulong target_st_atime; /* Time of last access. */ 2132 + abi_ulong target_st_atime_nsec; 2133 + abi_ulong target_st_mtime; /* Time of last modification. */ 2134 + abi_ulong target_st_mtime_nsec; 2135 + abi_ulong target_st_ctime; /* Time of last status change. */ 2136 + abi_ulong target_st_ctime_nsec; 2137 + abi_ulong __unused4; 2138 + abi_ulong __unused5; 2139 + }; 2140 + 2083 2141 #elif defined(TARGET_OPENRISC) || defined(TARGET_TILEGX) || \ 2084 2142 defined(TARGET_NIOS2) || defined(TARGET_RISCV) 2085 2143 ··· 2590 2648 short l_whence; 2591 2649 #if defined(TARGET_PPC) || defined(TARGET_X86_64) || defined(TARGET_MIPS) \ 2592 2650 || defined(TARGET_SPARC) || defined(TARGET_HPPA) \ 2593 - || defined(TARGET_MICROBLAZE) || defined(TARGET_TILEGX) 2651 + || defined(TARGET_MICROBLAZE) || defined(TARGET_TILEGX) \ 2652 + || defined(TARGET_XTENSA) 2594 2653 int __pad; 2595 2654 #endif 2596 2655 abi_llong l_start;

linux-user/xtensa/syscall.h

This is a binary file and will not be displayed.

+437

linux-user/xtensa/syscall_nr.h

··· 1 + /* 2 + * include/asm-xtensa/unistd.h 3 + * 4 + * This file is subject to the terms and conditions of the GNU General Public 5 + * License. See the file "COPYING" in the main directory of this archive 6 + * for more details. 7 + * 8 + * Copyright (C) 2001 - 2009 Tensilica Inc. 9 + */ 10 + 11 + #ifndef _XTENSA_UNISTD_H 12 + #define _XTENSA_UNISTD_H 13 + 14 + #define TARGET_NR_spill 0 15 + #define TARGET_NR_xtensa 1 16 + #define TARGET_NR_available4 2 17 + #define TARGET_NR_available5 3 18 + #define TARGET_NR_available6 4 19 + #define TARGET_NR_available7 5 20 + #define TARGET_NR_available8 6 21 + #define TARGET_NR_available9 7 22 + 23 + /* File Operations */ 24 + 25 + #define TARGET_NR_open 8 26 + #define TARGET_NR_close 9 27 + #define TARGET_NR_dup 10 28 + #define TARGET_NR_dup2 11 29 + #define TARGET_NR_read 12 30 + #define TARGET_NR_write 13 31 + #define TARGET_NR_select 14 32 + #define TARGET_NR_lseek 15 33 + #define TARGET_NR_poll 16 34 + #define TARGET_NR__llseek 17 35 + #define TARGET_NR_epoll_wait 18 36 + #define TARGET_NR_epoll_ctl 19 37 + #define TARGET_NR_epoll_create 20 38 + #define TARGET_NR_creat 21 39 + #define TARGET_NR_truncate 22 40 + #define TARGET_NR_ftruncate 23 41 + #define TARGET_NR_readv 24 42 + #define TARGET_NR_writev 25 43 + #define TARGET_NR_fsync 26 44 + #define TARGET_NR_fdatasync 27 45 + #define TARGET_NR_truncate64 28 46 + #define TARGET_NR_ftruncate64 29 47 + #define TARGET_NR_pread64 30 48 + #define TARGET_NR_pwrite64 31 49 + 50 + #define TARGET_NR_link 32 51 + #define TARGET_NR_rename 33 52 + #define TARGET_NR_symlink 34 53 + #define TARGET_NR_readlink 35 54 + #define TARGET_NR_mknod 36 55 + #define TARGET_NR_pipe 37 56 + #define TARGET_NR_unlink 38 57 + #define TARGET_NR_rmdir 39 58 + 59 + #define TARGET_NR_mkdir 40 60 + #define TARGET_NR_chdir 41 61 + #define TARGET_NR_fchdir 42 62 + #define TARGET_NR_getcwd 43 63 + 64 + #define TARGET_NR_chmod 44 65 + #define TARGET_NR_chown 45 66 + #define TARGET_NR_stat 46 67 + #define TARGET_NR_stat64 47 68 + 69 + #define TARGET_NR_lchown 48 70 + #define TARGET_NR_lstat 49 71 + #define TARGET_NR_lstat64 50 72 + #define TARGET_NR_available51 51 73 + 74 + #define TARGET_NR_fchmod 52 75 + #define TARGET_NR_fchown 53 76 + #define TARGET_NR_fstat 54 77 + #define TARGET_NR_fstat64 55 78 + 79 + #define TARGET_NR_flock 56 80 + #define TARGET_NR_access 57 81 + #define TARGET_NR_umask 58 82 + #define TARGET_NR_getdents 59 83 + #define TARGET_NR_getdents64 60 84 + #define TARGET_NR_fcntl64 61 85 + #define TARGET_NR_fallocate 62 86 + #define TARGET_NR_fadvise64_64 63 87 + #define TARGET_NR_utime 64 /* glibc 2.3.3 ?? */ 88 + #define TARGET_NR_utimes 65 89 + #define TARGET_NR_ioctl 66 90 + #define TARGET_NR_fcntl 67 91 + 92 + #define TARGET_NR_setxattr 68 93 + #define TARGET_NR_getxattr 69 94 + #define TARGET_NR_listxattr 70 95 + #define TARGET_NR_removexattr 71 96 + #define TARGET_NR_lsetxattr 72 97 + #define TARGET_NR_lgetxattr 73 98 + #define TARGET_NR_llistxattr 74 99 + #define TARGET_NR_lremovexattr 75 100 + #define TARGET_NR_fsetxattr 76 101 + #define TARGET_NR_fgetxattr 77 102 + #define TARGET_NR_flistxattr 78 103 + #define TARGET_NR_fremovexattr 79 104 + 105 + /* File Map / Shared Memory Operations */ 106 + 107 + #define TARGET_NR_mmap2 80 108 + #define TARGET_NR_munmap 81 109 + #define TARGET_NR_mprotect 82 110 + #define TARGET_NR_brk 83 111 + #define TARGET_NR_mlock 84 112 + #define TARGET_NR_munlock 85 113 + #define TARGET_NR_mlockall 86 114 + #define TARGET_NR_munlockall 87 115 + #define TARGET_NR_mremap 88 116 + #define TARGET_NR_msync 89 117 + #define TARGET_NR_mincore 90 118 + #define TARGET_NR_madvise 91 119 + #define TARGET_NR_shmget 92 120 + #define TARGET_NR_shmat 93 121 + #define TARGET_NR_shmctl 94 122 + #define TARGET_NR_shmdt 95 123 + 124 + /* Socket Operations */ 125 + 126 + #define TARGET_NR_socket 96 127 + #define TARGET_NR_setsockopt 97 128 + #define TARGET_NR_getsockopt 98 129 + #define TARGET_NR_shutdown 99 130 + 131 + #define TARGET_NR_bind 100 132 + #define TARGET_NR_connect 101 133 + #define TARGET_NR_listen 102 134 + #define TARGET_NR_accept 103 135 + 136 + #define TARGET_NR_getsockname 104 137 + #define TARGET_NR_getpeername 105 138 + #define TARGET_NR_sendmsg 106 139 + #define TARGET_NR_recvmsg 107 140 + #define TARGET_NR_send 108 141 + #define TARGET_NR_recv 109 142 + #define TARGET_NR_sendto 110 143 + #define TARGET_NR_recvfrom 111 144 + 145 + #define TARGET_NR_socketpair 112 146 + #define TARGET_NR_sendfile 113 147 + #define TARGET_NR_sendfile64 114 148 + #define TARGET_NR_sendmmsg 115 149 + 150 + /* Process Operations */ 151 + 152 + #define TARGET_NR_clone 116 153 + #define TARGET_NR_execve 117 154 + #define TARGET_NR_exit 118 155 + #define TARGET_NR_exit_group 119 156 + #define TARGET_NR_getpid 120 157 + #define TARGET_NR_wait4 121 158 + #define TARGET_NR_waitid 122 159 + #define TARGET_NR_kill 123 160 + #define TARGET_NR_tkill 124 161 + #define TARGET_NR_tgkill 125 162 + #define TARGET_NR_set_tid_address 126 163 + #define TARGET_NR_gettid 127 164 + #define TARGET_NR_setsid 128 165 + #define TARGET_NR_getsid 129 166 + #define TARGET_NR_prctl 130 167 + #define TARGET_NR_personality 131 168 + #define TARGET_NR_getpriority 132 169 + #define TARGET_NR_setpriority 133 170 + #define TARGET_NR_setitimer 134 171 + #define TARGET_NR_getitimer 135 172 + #define TARGET_NR_setuid 136 173 + #define TARGET_NR_getuid 137 174 + #define TARGET_NR_setgid 138 175 + #define TARGET_NR_getgid 139 176 + #define TARGET_NR_geteuid 140 177 + #define TARGET_NR_getegid 141 178 + #define TARGET_NR_setreuid 142 179 + #define TARGET_NR_setregid 143 180 + #define TARGET_NR_setresuid 144 181 + #define TARGET_NR_getresuid 145 182 + #define TARGET_NR_setresgid 146 183 + #define TARGET_NR_getresgid 147 184 + #define TARGET_NR_setpgid 148 185 + #define TARGET_NR_getpgid 149 186 + #define TARGET_NR_getppid 150 187 + #define TARGET_NR_getpgrp 151 188 + 189 + #define TARGET_NR_reserved152 152 /* set_thread_area */ 190 + #define TARGET_NR_reserved153 153 /* get_thread_area */ 191 + #define TARGET_NR_times 154 192 + #define TARGET_NR_acct 155 193 + #define TARGET_NR_sched_setaffinity 156 194 + #define TARGET_NR_sched_getaffinity 157 195 + #define TARGET_NR_capget 158 196 + #define TARGET_NR_capset 159 197 + #define TARGET_NR_ptrace 160 198 + #define TARGET_NR_semtimedop 161 199 + #define TARGET_NR_semget 162 200 + #define TARGET_NR_semop 163 201 + #define TARGET_NR_semctl 164 202 + #define TARGET_NR_available165 165 203 + #define TARGET_NR_msgget 166 204 + #define TARGET_NR_msgsnd 167 205 + #define TARGET_NR_msgrcv 168 206 + #define TARGET_NR_msgctl 169 207 + #define TARGET_NR_available170 170 208 + 209 + /* File System */ 210 + 211 + #define TARGET_NR_umount2 171 212 + #define TARGET_NR_mount 172 213 + #define TARGET_NR_swapon 173 214 + #define TARGET_NR_chroot 174 215 + #define TARGET_NR_pivot_root 175 216 + #define TARGET_NR_umount 176 217 + #define TARGET_NR_swapoff 177 218 + #define TARGET_NR_sync 178 219 + #define TARGET_NR_syncfs 179 220 + #define TARGET_NR_setfsuid 180 221 + #define TARGET_NR_setfsgid 181 222 + #define TARGET_NR_sysfs 182 223 + #define TARGET_NR_ustat 183 224 + #define TARGET_NR_statfs 184 225 + #define TARGET_NR_fstatfs 185 226 + #define TARGET_NR_statfs64 186 227 + #define TARGET_NR_fstatfs64 187 228 + 229 + /* System */ 230 + 231 + #define TARGET_NR_setrlimit 188 232 + #define TARGET_NR_getrlimit 189 233 + #define TARGET_NR_getrusage 190 234 + #define TARGET_NR_futex 191 235 + #define TARGET_NR_gettimeofday 192 236 + #define TARGET_NR_settimeofday 193 237 + #define TARGET_NR_adjtimex 194 238 + #define TARGET_NR_nanosleep 195 239 + #define TARGET_NR_getgroups 196 240 + #define TARGET_NR_setgroups 197 241 + #define TARGET_NR_sethostname 198 242 + #define TARGET_NR_setdomainname 199 243 + #define TARGET_NR_syslog 200 244 + #define TARGET_NR_vhangup 201 245 + #define TARGET_NR_uselib 202 246 + #define TARGET_NR_reboot 203 247 + #define TARGET_NR_quotactl 204 248 + #define TARGET_NR_nfsservctl 205 249 + #define TARGET_NR__sysctl 206 250 + #define TARGET_NR_bdflush 207 251 + #define TARGET_NR_uname 208 252 + #define TARGET_NR_sysinfo 209 253 + #define TARGET_NR_init_module 210 254 + #define TARGET_NR_delete_module 211 255 + 256 + #define TARGET_NR_sched_setparam 212 257 + #define TARGET_NR_sched_getparam 213 258 + #define TARGET_NR_sched_setscheduler 214 259 + #define TARGET_NR_sched_getscheduler 215 260 + #define TARGET_NR_sched_get_priority_max 216 261 + #define TARGET_NR_sched_get_priority_min 217 262 + #define TARGET_NR_sched_rr_get_interval 218 263 + #define TARGET_NR_sched_yield 219 264 + #define TARGET_NR_available222 222 265 + 266 + /* Signal Handling */ 267 + 268 + #define TARGET_NR_restart_syscall 223 269 + #define TARGET_NR_sigaltstack 224 270 + #define TARGET_NR_rt_sigreturn 225 271 + #define TARGET_NR_rt_sigaction 226 272 + #define TARGET_NR_rt_sigprocmask 227 273 + #define TARGET_NR_rt_sigpending 228 274 + #define TARGET_NR_rt_sigtimedwait 229 275 + #define TARGET_NR_rt_sigqueueinfo 230 276 + #define TARGET_NR_rt_sigsuspend 231 277 + 278 + /* Message */ 279 + 280 + #define TARGET_NR_mq_open 232 281 + #define TARGET_NR_mq_unlink 233 282 + #define TARGET_NR_mq_timedsend 234 283 + #define TARGET_NR_mq_timedreceive 235 284 + #define TARGET_NR_mq_notify 236 285 + #define TARGET_NR_mq_getsetattr 237 286 + #define TARGET_NR_available238 238 287 + 288 + /* IO */ 289 + 290 + #define TARGET_NR_io_setup 239 291 + #define TARGET_NR_io_destroy 240 292 + #define TARGET_NR_io_submit 241 293 + #define TARGET_NR_io_getevents 242 294 + #define TARGET_NR_io_cancel 243 295 + #define TARGET_NR_clock_settime 244 296 + #define TARGET_NR_clock_gettime 245 297 + #define TARGET_NR_clock_getres 246 298 + #define TARGET_NR_clock_nanosleep 247 299 + 300 + /* Timer */ 301 + 302 + #define TARGET_NR_timer_create 248 303 + #define TARGET_NR_timer_delete 249 304 + #define TARGET_NR_timer_settime 250 305 + #define TARGET_NR_timer_gettime 251 306 + #define TARGET_NR_timer_getoverrun 252 307 + 308 + /* System */ 309 + 310 + #define TARGET_NR_reserved253 253 311 + #define TARGET_NR_lookup_dcookie 254 312 + #define TARGET_NR_available255 255 313 + #define TARGET_NR_add_key 256 314 + #define TARGET_NR_request_key 257 315 + #define TARGET_NR_keyctl 258 316 + #define TARGET_NR_available259 259 317 + 318 + 319 + #define TARGET_NR_readahead 260 320 + #define TARGET_NR_remap_file_pages 261 321 + #define TARGET_NR_migrate_pages 262 322 + #define TARGET_NR_mbind 263 323 + #define TARGET_NR_get_mempolicy 264 324 + #define TARGET_NR_set_mempolicy 265 325 + #define TARGET_NR_unshare 266 326 + #define TARGET_NR_move_pages 267 327 + #define TARGET_NR_splice 268 328 + #define TARGET_NR_tee 269 329 + #define TARGET_NR_vmsplice 270 330 + #define TARGET_NR_available271 271 331 + 332 + #define TARGET_NR_pselect6 272 333 + #define TARGET_NR_ppoll 273 334 + #define TARGET_NR_epoll_pwait 274 335 + #define TARGET_NR_epoll_create1 275 336 + 337 + #define TARGET_NR_inotify_init 276 338 + #define TARGET_NR_inotify_add_watch 277 339 + #define TARGET_NR_inotify_rm_watch 278 340 + #define TARGET_NR_inotify_init1 279 341 + 342 + #define TARGET_NR_getcpu 280 343 + #define TARGET_NR_kexec_load 281 344 + 345 + #define TARGET_NR_ioprio_set 282 346 + #define TARGET_NR_ioprio_get 283 347 + 348 + #define TARGET_NR_set_robust_list 284 349 + #define TARGET_NR_get_robust_list 285 350 + #define TARGET_NR_available286 286 351 + #define TARGET_NR_available287 287 352 + 353 + /* Relative File Operations */ 354 + 355 + #define TARGET_NR_openat 288 356 + #define TARGET_NR_mkdirat 289 357 + #define TARGET_NR_mknodat 290 358 + #define TARGET_NR_unlinkat 291 359 + #define TARGET_NR_renameat 292 360 + #define TARGET_NR_linkat 293 361 + #define TARGET_NR_symlinkat 294 362 + #define TARGET_NR_readlinkat 295 363 + #define TARGET_NR_utimensat 296 364 + #define TARGET_NR_fchownat 297 365 + #define TARGET_NR_futimesat 298 366 + #define TARGET_NR_fstatat64 299 367 + #define TARGET_NR_fchmodat 300 368 + #define TARGET_NR_faccessat 301 369 + #define TARGET_NR_available302 302 370 + #define TARGET_NR_available303 303 371 + 372 + #define TARGET_NR_signalfd 304 373 + /* 305 was TARGET_NR_timerfd */ 374 + #define TARGET_NR_eventfd 306 375 + #define TARGET_NR_recvmmsg 307 376 + 377 + #define TARGET_NR_setns 308 378 + #define TARGET_NR_signalfd4 309 379 + #define TARGET_NR_dup3 310 380 + #define TARGET_NR_pipe2 311 381 + 382 + #define TARGET_NR_timerfd_create 312 383 + #define TARGET_NR_timerfd_settime 313 384 + #define TARGET_NR_timerfd_gettime 314 385 + #define TARGET_NR_available315 315 386 + 387 + #define TARGET_NR_eventfd2 316 388 + #define TARGET_NR_preadv 317 389 + #define TARGET_NR_pwritev 318 390 + #define TARGET_NR_available319 319 391 + 392 + #define TARGET_NR_fanotify_init 320 393 + #define TARGET_NR_fanotify_mark 321 394 + #define TARGET_NR_process_vm_readv 322 395 + #define TARGET_NR_process_vm_writev 323 396 + 397 + #define TARGET_NR_name_to_handle_at 324 398 + #define TARGET_NR_open_by_handle_at 325 399 + #define TARGET_NR_sync_file_range2 326 400 + #define TARGET_NR_perf_event_open 327 401 + 402 + #define TARGET_NR_rt_tgsigqueueinfo 328 403 + #define TARGET_NR_clock_adjtime 329 404 + #define TARGET_NR_prlimit64 330 405 + #define TARGET_NR_kcmp 331 406 + 407 + #define TARGET_NR_finit_module 332 408 + 409 + #define TARGET_NR_accept4 333 410 + 411 + #define TARGET_NR_sched_setattr 334 412 + #define TARGET_NR_sched_getattr 335 413 + 414 + #define TARGET_NR_renameat2 336 415 + 416 + #define TARGET_NR_seccomp 337 417 + #define TARGET_NR_getrandom 338 418 + #define TARGET_NR_memfd_create 339 419 + #define TARGET_NR_bpf 340 420 + #define TARGET_NR_execveat 341 421 + 422 + #define TARGET_NR_userfaultfd 342 423 + #define TARGET_NR_membarrier 343 424 + #define TARGET_NR_mlock2 344 425 + #define TARGET_NR_copy_file_range 345 426 + #define TARGET_NR_preadv2 346 427 + #define TARGET_NR_pwritev2 347 428 + 429 + #define TARGET_NR_pkey_mprotect 348 430 + #define TARGET_NR_pkey_alloc 349 431 + #define TARGET_NR_pkey_free 350 432 + 433 + #define TARGET_NR_statx 351 434 + 435 + #define TARGET_NR_syscall_count 352 436 + 437 + #endif /* _XTENSA_UNISTD_H */

+22

linux-user/xtensa/target_cpu.h

··· 1 + /* 2 + * Xtensa-specific CPU ABI and functions for linux-user 3 + */ 4 + #ifndef XTENSA_TARGET_CPU_H 5 + #define XTENSA_TARGET_CPU_H 6 + 7 + static inline void cpu_clone_regs(CPUXtensaState *env, target_ulong newsp) 8 + { 9 + if (newsp) { 10 + env->regs[1] = newsp; 11 + env->sregs[WINDOW_BASE] = 0; 12 + env->sregs[WINDOW_START] = 0x1; 13 + } 14 + env->regs[2] = 0; 15 + } 16 + 17 + static inline void cpu_set_tls(CPUXtensaState *env, target_ulong newtls) 18 + { 19 + env->uregs[THREADPTR] = newtls; 20 + } 21 + 22 + #endif

+16

linux-user/xtensa/target_elf.h

··· 1 + /* 2 + * This program is free software; you can redistribute it and/or modify 3 + * it under the terms of the GNU General Public License version 2 as 4 + * published by the Free Software Foundation, or (at your option) any 5 + * later version. See the COPYING file in the top-level directory. 6 + */ 7 + 8 + #ifndef XTENSA_TARGET_ELF_H 9 + #define XTENSA_TARGET_ELF_H 10 + 11 + static inline const char *cpu_get_model(uint32_t eflags) 12 + { 13 + return XTENSA_DEFAULT_CPU_MODEL; 14 + } 15 + 16 + #endif

+28

linux-user/xtensa/target_signal.h

··· 1 + #ifndef XTENSA_TARGET_SIGNAL_H 2 + #define XTENSA_TARGET_SIGNAL_H 3 + 4 + #include "cpu.h" 5 + 6 + /* this struct defines a stack used during syscall handling */ 7 + 8 + typedef struct target_sigaltstack { 9 + abi_ulong ss_sp; 10 + abi_int ss_flags; 11 + abi_ulong ss_size; 12 + } target_stack_t; 13 + 14 + /* 15 + * sigaltstack controls 16 + */ 17 + #define TARGET_SS_ONSTACK 1 18 + #define TARGET_SS_DISABLE 2 19 + 20 + #define TARGET_MINSIGSTKSZ 2048 21 + #define TARGET_SIGSTKSZ 8192 22 + 23 + static inline abi_ulong get_sp_from_cpustate(CPUXtensaState *state) 24 + { 25 + return state->regs[1]; 26 + } 27 + 28 + #endif

+28

linux-user/xtensa/target_structs.h

··· 1 + #ifndef XTENSA_TARGET_STRUCTS_T 2 + #define XTENSA_TARGET_STRUCTS_T 3 + 4 + struct target_ipc_perm { 5 + abi_int __key; /* Key. */ 6 + abi_uint uid; /* Owner's user ID. */ 7 + abi_uint gid; /* Owner's group ID. */ 8 + abi_uint cuid; /* Creator's user ID. */ 9 + abi_uint cgid; /* Creator's group ID. */ 10 + abi_uint mode; /* Read/write permission. */ 11 + abi_ushort __seq; /* Sequence number. */ 12 + }; 13 + 14 + struct target_shmid_ds { 15 + struct target_ipc_perm shm_perm; /* operation permission struct */ 16 + abi_int shm_segsz; /* size of segment in bytes */ 17 + abi_long shm_atime; /* time of last shmat() */ 18 + abi_long shm_dtime; /* time of last shmdt() */ 19 + abi_long shm_ctime; /* time of last change by shmctl() */ 20 + abi_ushort shm_cpid; /* pid of creator */ 21 + abi_ushort shm_lpid; /* pid of last shmop */ 22 + abi_ushort shm_nattch; /* number of current attaches */ 23 + abi_ushort shm_unused; /* compatibility */ 24 + abi_ulong __unused2; 25 + abi_ulong __unused3; 26 + }; 27 + 28 + #endif

+49

linux-user/xtensa/target_syscall.h

··· 1 + #ifndef XTENSA_TARGET_SYSCALL_H 2 + #define XTENSA_TARGET_SYSCALL_H 3 + 4 + #define UNAME_MACHINE "xtensa" 5 + 6 + #define UNAME_MINIMUM_RELEASE "3.19" 7 + #define TARGET_CLONE_BACKWARDS 8 + 9 + #define MMAP_SHIFT TARGET_PAGE_BITS 10 + 11 + typedef uint32_t xtensa_reg_t; 12 + typedef struct { 13 + } xtregs_opt_t; /* TODO */ 14 + 15 + struct target_pt_regs { 16 + xtensa_reg_t pc; /* 4 */ 17 + xtensa_reg_t ps; /* 8 */ 18 + xtensa_reg_t depc; /* 12 */ 19 + xtensa_reg_t exccause; /* 16 */ 20 + xtensa_reg_t excvaddr; /* 20 */ 21 + xtensa_reg_t debugcause; /* 24 */ 22 + xtensa_reg_t wmask; /* 28 */ 23 + xtensa_reg_t lbeg; /* 32 */ 24 + xtensa_reg_t lend; /* 36 */ 25 + xtensa_reg_t lcount; /* 40 */ 26 + xtensa_reg_t sar; /* 44 */ 27 + xtensa_reg_t windowbase; /* 48 */ 28 + xtensa_reg_t windowstart; /* 52 */ 29 + xtensa_reg_t syscall; /* 56 */ 30 + xtensa_reg_t icountlevel; /* 60 */ 31 + xtensa_reg_t scompare1; /* 64 */ 32 + xtensa_reg_t threadptr; /* 68 */ 33 + 34 + /* Additional configurable registers that are used by the compiler. */ 35 + xtregs_opt_t xtregs_opt; 36 + 37 + /* Make sure the areg field is 16 bytes aligned. */ 38 + int align[0] __attribute__ ((aligned(16))); 39 + 40 + /* current register frame. 41 + * Note: The ESF for kernel exceptions ends after 16 registers! 42 + */ 43 + xtensa_reg_t areg[16]; 44 + }; 45 + 46 + #define TARGET_MLOCKALL_MCL_CURRENT 1 47 + #define TARGET_MLOCKALL_MCL_FUTURE 2 48 + 49 + #endif

+328

linux-user/xtensa/termbits.h

··· 1 + /* 2 + * include/asm-xtensa/termbits.h 3 + * 4 + * Copied from SH. 5 + * 6 + * This file is subject to the terms and conditions of the GNU General Public 7 + * License. See the file "COPYING" in the main directory of this archive 8 + * for more details. 9 + * 10 + * Copyright (C) 2001 - 2005 Tensilica Inc. 11 + */ 12 + 13 + #ifndef _XTENSA_TERMBITS_H 14 + #define _XTENSA_TERMBITS_H 15 + 16 + #include <linux/posix_types.h> 17 + 18 + typedef unsigned char cc_t; 19 + typedef unsigned int speed_t; 20 + typedef unsigned int tcflag_t; 21 + 22 + #define TARGET_NCCS 19 23 + struct target_termios { 24 + tcflag_t c_iflag; /* input mode flags */ 25 + tcflag_t c_oflag; /* output mode flags */ 26 + tcflag_t c_cflag; /* control mode flags */ 27 + tcflag_t c_lflag; /* local mode flags */ 28 + cc_t c_line; /* line discipline */ 29 + cc_t c_cc[TARGET_NCCS]; /* control characters */ 30 + }; 31 + 32 + struct target_termios2 { 33 + tcflag_t c_iflag; /* input mode flags */ 34 + tcflag_t c_oflag; /* output mode flags */ 35 + tcflag_t c_cflag; /* control mode flags */ 36 + tcflag_t c_lflag; /* local mode flags */ 37 + cc_t c_line; /* line discipline */ 38 + cc_t c_cc[TARGET_NCCS]; /* control characters */ 39 + speed_t c_ispeed; /* input speed */ 40 + speed_t c_ospeed; /* output speed */ 41 + }; 42 + 43 + struct target_ktermios { 44 + tcflag_t c_iflag; /* input mode flags */ 45 + tcflag_t c_oflag; /* output mode flags */ 46 + tcflag_t c_cflag; /* control mode flags */ 47 + tcflag_t c_lflag; /* local mode flags */ 48 + cc_t c_line; /* line discipline */ 49 + cc_t c_cc[TARGET_NCCS]; /* control characters */ 50 + speed_t c_ispeed; /* input speed */ 51 + speed_t c_ospeed; /* output speed */ 52 + }; 53 + 54 + /* c_cc characters */ 55 + 56 + #define TARGET_VINTR 0 57 + #define TARGET_VQUIT 1 58 + #define TARGET_VERASE 2 59 + #define TARGET_VKILL 3 60 + #define TARGET_VEOF 4 61 + #define TARGET_VTIME 5 62 + #define TARGET_VMIN 6 63 + #define TARGET_VSWTC 7 64 + #define TARGET_VSTART 8 65 + #define TARGET_VSTOP 9 66 + #define TARGET_VSUSP 10 67 + #define TARGET_VEOL 11 68 + #define TARGET_VREPRINT 12 69 + #define TARGET_VDISCARD 13 70 + #define TARGET_VWERASE 14 71 + #define TARGET_VLNEXT 15 72 + #define TARGET_VEOL2 16 73 + 74 + /* c_iflag bits */ 75 + 76 + #define TARGET_IGNBRK 0000001 77 + #define TARGET_BRKINT 0000002 78 + #define TARGET_IGNPAR 0000004 79 + #define TARGET_PARMRK 0000010 80 + #define TARGET_INPCK 0000020 81 + #define TARGET_ISTRIP 0000040 82 + #define TARGET_INLCR 0000100 83 + #define TARGET_IGNCR 0000200 84 + #define TARGET_ICRNL 0000400 85 + #define TARGET_IUCLC 0001000 86 + #define TARGET_IXON 0002000 87 + #define TARGET_IXANY 0004000 88 + #define TARGET_IXOFF 0010000 89 + #define TARGET_IMAXBEL 0020000 90 + #define TARGET_IUTF8 0040000 91 + 92 + /* c_oflag bits */ 93 + 94 + #define TARGET_OPOST 0000001 95 + #define TARGET_OLCUC 0000002 96 + #define TARGET_ONLCR 0000004 97 + #define TARGET_OCRNL 0000010 98 + #define TARGET_ONOCR 0000020 99 + #define TARGET_ONLRET 0000040 100 + #define TARGET_OFILL 0000100 101 + #define TARGET_OFDEL 0000200 102 + #define TARGET_NLDLY 0000400 103 + #define TARGET_NL0 0000000 104 + #define TARGET_NL1 0000400 105 + #define TARGET_CRDLY 0003000 106 + #define TARGET_CR0 0000000 107 + #define TARGET_CR1 0001000 108 + #define TARGET_CR2 0002000 109 + #define TARGET_CR3 0003000 110 + #define TARGET_TABDLY 0014000 111 + #define TARGET_TAB0 0000000 112 + #define TARGET_TAB1 0004000 113 + #define TARGET_TAB2 0010000 114 + #define TARGET_TAB3 0014000 115 + #define TARGET_XTABS 0014000 116 + #define TARGET_BSDLY 0020000 117 + #define TARGET_BS0 0000000 118 + #define TARGET_BS1 0020000 119 + #define TARGET_VTDLY 0040000 120 + #define TARGET_VT0 0000000 121 + #define TARGET_VT1 0040000 122 + #define TARGET_FFDLY 0100000 123 + #define TARGET_FF0 0000000 124 + #define TARGET_FF1 0100000 125 + 126 + /* c_cflag bit meaning */ 127 + 128 + #define TARGET_CBAUD 0010017 129 + #define TARGET_B0 0000000 /* hang up */ 130 + #define TARGET_B50 0000001 131 + #define TARGET_B75 0000002 132 + #define TARGET_B110 0000003 133 + #define TARGET_B134 0000004 134 + #define TARGET_B150 0000005 135 + #define TARGET_B200 0000006 136 + #define TARGET_B300 0000007 137 + #define TARGET_B600 0000010 138 + #define TARGET_B1200 0000011 139 + #define TARGET_B1800 0000012 140 + #define TARGET_B2400 0000013 141 + #define TARGET_B4800 0000014 142 + #define TARGET_B9600 0000015 143 + #define TARGET_B19200 0000016 144 + #define TARGET_B38400 0000017 145 + #define TARGET_EXTA B19200 146 + #define TARGET_EXTB B38400 147 + #define TARGET_CSIZE 0000060 148 + #define TARGET_CS5 0000000 149 + #define TARGET_CS6 0000020 150 + #define TARGET_CS7 0000040 151 + #define TARGET_CS8 0000060 152 + #define TARGET_CSTOPB 0000100 153 + #define TARGET_CREAD 0000200 154 + #define TARGET_PARENB 0000400 155 + #define TARGET_PARODD 0001000 156 + #define TARGET_HUPCL 0002000 157 + #define TARGET_CLOCAL 0004000 158 + #define TARGET_CBAUDEX 0010000 159 + #define TARGET_BOTHER 0010000 160 + #define TARGET_B57600 0010001 161 + #define TARGET_B115200 0010002 162 + #define TARGET_B230400 0010003 163 + #define TARGET_B460800 0010004 164 + #define TARGET_B500000 0010005 165 + #define TARGET_B576000 0010006 166 + #define TARGET_B921600 0010007 167 + #define TARGET_B1000000 0010010 168 + #define TARGET_B1152000 0010011 169 + #define TARGET_B1500000 0010012 170 + #define TARGET_B2000000 0010013 171 + #define TARGET_B2500000 0010014 172 + #define TARGET_B3000000 0010015 173 + #define TARGET_B3500000 0010016 174 + #define TARGET_B4000000 0010017 175 + #define TARGET_CIBAUD 002003600000 /* input baud rate */ 176 + #define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */ 177 + #define TARGET_CRTSCTS 020000000000 /* flow control */ 178 + 179 + #define TARGET_IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ 180 + 181 + /* c_lflag bits */ 182 + 183 + #define TARGET_ISIG 0000001 184 + #define TARGET_ICANON 0000002 185 + #define TARGET_XCASE 0000004 186 + #define TARGET_ECHO 0000010 187 + #define TARGET_ECHOE 0000020 188 + #define TARGET_ECHOK 0000040 189 + #define TARGET_ECHONL 0000100 190 + #define TARGET_NOFLSH 0000200 191 + #define TARGET_TOSTOP 0000400 192 + #define TARGET_ECHOCTL 0001000 193 + #define TARGET_ECHOPRT 0002000 194 + #define TARGET_ECHOKE 0004000 195 + #define TARGET_FLUSHO 0010000 196 + #define TARGET_PENDIN 0040000 197 + #define TARGET_IEXTEN 0100000 198 + 199 + /* tcflow() and TCXONC use these */ 200 + 201 + #define TARGET_TCOOFF 0 202 + #define TARGET_TCOON 1 203 + #define TARGET_TCIOFF 2 204 + #define TARGET_TCION 3 205 + 206 + /* tcflush() and TCFLSH use these */ 207 + 208 + #define TARGET_TCIFLUSH 0 209 + #define TARGET_TCOFLUSH 1 210 + #define TARGET_TCIOFLUSH 2 211 + 212 + /* tcsetattr uses these */ 213 + 214 + #define TARGET_TCSANOW 0 215 + #define TARGET_TCSADRAIN 1 216 + #define TARGET_TCSAFLUSH 2 217 + 218 + /* from arch/xtensa/include/uapi/asm/ioctls.h */ 219 + 220 + #define TARGET_FIOCLEX _IO('f', 1) 221 + #define TARGET_FIONCLEX _IO('f', 2) 222 + #define TARGET_FIOASYNC _IOW('f', 125, int) 223 + #define TARGET_FIONBIO _IOW('f', 126, int) 224 + #define TARGET_FIONREAD _IOR('f', 127, int) 225 + #define TARGET_TIOCINQ FIONREAD 226 + #define TARGET_FIOQSIZE _IOR('f', 128, loff_t) 227 + 228 + #define TARGET_TCGETS 0x5401 229 + #define TARGET_TCSETS 0x5402 230 + #define TARGET_TCSETSW 0x5403 231 + #define TARGET_TCSETSF 0x5404 232 + 233 + #define TARGET_TCGETA 0x80127417 /* _IOR('t', 23, struct termio) */ 234 + #define TARGET_TCSETA 0x40127418 /* _IOW('t', 24, struct termio) */ 235 + #define TARGET_TCSETAW 0x40127419 /* _IOW('t', 25, struct termio) */ 236 + #define TARGET_TCSETAF 0x4012741C /* _IOW('t', 28, struct termio) */ 237 + 238 + #define TARGET_TCSBRK _IO('t', 29) 239 + #define TARGET_TCXONC _IO('t', 30) 240 + #define TARGET_TCFLSH _IO('t', 31) 241 + 242 + #define TARGET_TIOCSWINSZ 0x40087467 /* _IOW('t', 103, struct winsize) */ 243 + #define TARGET_TIOCGWINSZ 0x80087468 /* _IOR('t', 104, struct winsize) */ 244 + #define TARGET_TIOCSTART _IO('t', 110) /* start output, like ^Q */ 245 + #define TARGET_TIOCSTOP _IO('t', 111) /* stop output, like ^S */ 246 + #define TARGET_TIOCOUTQ _IOR('t', 115, int) /* output queue size */ 247 + 248 + #define TARGET_TIOCSPGRP _IOW('t', 118, int) 249 + #define TARGET_TIOCGPGRP _IOR('t', 119, int) 250 + 251 + #define TARGET_TIOCEXCL _IO('T', 12) 252 + #define TARGET_TIOCNXCL _IO('T', 13) 253 + #define TARGET_TIOCSCTTY _IO('T', 14) 254 + 255 + #define TARGET_TIOCSTI _IOW('T', 18, char) 256 + #define TARGET_TIOCMGET _IOR('T', 21, unsigned int) 257 + #define TARGET_TIOCMBIS _IOW('T', 22, unsigned int) 258 + #define TARGET_TIOCMBIC _IOW('T', 23, unsigned int) 259 + #define TARGET_TIOCMSET _IOW('T', 24, unsigned int) 260 + # define TARGET_TIOCM_LE 0x001 261 + # define TARGET_TIOCM_DTR 0x002 262 + # define TARGET_TIOCM_RTS 0x004 263 + # define TARGET_TIOCM_ST 0x008 264 + # define TARGET_TIOCM_SR 0x010 265 + # define TARGET_TIOCM_CTS 0x020 266 + # define TARGET_TIOCM_CAR 0x040 267 + # define TARGET_TIOCM_RNG 0x080 268 + # define TARGET_TIOCM_DSR 0x100 269 + # define TARGET_TIOCM_CD TIOCM_CAR 270 + # define TARGET_TIOCM_RI TIOCM_RNG 271 + 272 + #define TARGET_TIOCGSOFTCAR _IOR('T', 25, unsigned int) 273 + #define TARGET_TIOCSSOFTCAR _IOW('T', 26, unsigned int) 274 + #define TARGET_TIOCLINUX _IOW('T', 28, char) 275 + #define TARGET_TIOCCONS _IO('T', 29) 276 + #define TARGET_TIOCGSERIAL 0x803C541E /*_IOR('T', 30, struct serial_struct)*/ 277 + #define TARGET_TIOCSSERIAL 0x403C541F /*_IOW('T', 31, struct serial_struct)*/ 278 + #define TARGET_TIOCPKT _IOW('T', 32, int) 279 + # define TARGET_TIOCPKT_DATA 0 280 + # define TARGET_TIOCPKT_FLUSHREAD 1 281 + # define TARGET_TIOCPKT_FLUSHWRITE 2 282 + # define TARGET_TIOCPKT_STOP 4 283 + # define TARGET_TIOCPKT_START 8 284 + # define TARGET_TIOCPKT_NOSTOP 16 285 + # define TARGET_TIOCPKT_DOSTOP 32 286 + # define TARGET_TIOCPKT_IOCTL 64 287 + 288 + 289 + #define TARGET_TIOCNOTTY _IO('T', 34) 290 + #define TARGET_TIOCSETD _IOW('T', 35, int) 291 + #define TARGET_TIOCGETD _IOR('T', 36, int) 292 + #define TARGET_TCSBRKP _IOW('T', 37, int) /* Needed for POSIX tcsendbreak()*/ 293 + #define TARGET_TIOCSBRK _IO('T', 39) /* BSD compatibility */ 294 + #define TARGET_TIOCCBRK _IO('T', 40) /* BSD compatibility */ 295 + #define TARGET_TIOCGSID _IOR('T', 41, pid_t) /* Return the session ID of FD*/ 296 + #define TARGET_TCGETS2 _IOR('T', 42, struct termios2) 297 + #define TARGET_TCSETS2 _IOW('T', 43, struct termios2) 298 + #define TARGET_TCSETSW2 _IOW('T', 44, struct termios2) 299 + #define TARGET_TCSETSF2 _IOW('T', 45, struct termios2) 300 + #define TARGET_TIOCGRS485 _IOR('T', 46, struct serial_rs485) 301 + #define TARGET_TIOCSRS485 _IOWR('T', 47, struct serial_rs485) 302 + #define TARGET_TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 303 + #define TARGET_TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 304 + #define TARGET_TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */ 305 + #define TARGET_TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ 306 + #define TARGET_TIOCVHANGUP _IO('T', 0x37) 307 + #define TARGET_TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */ 308 + #define TARGET_TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ 309 + #define TARGET_TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ 310 + #define TARGET_TIOCGPTPEER _IO('T', 0x41) /* Safely open the slave */ 311 + 312 + #define TARGET_TIOCSERCONFIG _IO('T', 83) 313 + #define TARGET_TIOCSERGWILD _IOR('T', 84, int) 314 + #define TARGET_TIOCSERSWILD _IOW('T', 85, int) 315 + #define TARGET_TIOCGLCKTRMIOS 0x5456 316 + #define TARGET_TIOCSLCKTRMIOS 0x5457 317 + #define TARGET_TIOCSERGSTRUCT 0x5458 /* For debugging only */ 318 + #define TARGET_TIOCSERGETLSR _IOR('T', 89, unsigned int) /* Get line status reg. */ 319 + /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ 320 + # define TARGET_TIOCSER_TEMT 0x01 /* Transmitter physically empty */ 321 + #define TARGET_TIOCSERGETMULTI 0x80a8545a /* Get multiport config */ 322 + /* _IOR('T', 90, struct serial_multiport_struct) */ 323 + #define TARGET_TIOCSERSETMULTI 0x40a8545b /* Set multiport config */ 324 + /* _IOW('T', 91, struct serial_multiport_struct) */ 325 + 326 + #define TARGET_TIOCMIWAIT _IO('T', 92) /* wait for a change on serial input line(s) */ 327 + #define TARGET_TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ 328 + #endif /* _XTENSA_TERMBITS_H */

+1 -2

target/xtensa/Makefile.objs

··· 1 - obj-y += xtensa-semi.o 2 1 obj-y += core-dc232b.o 3 2 obj-y += core-dc233c.o 4 3 obj-y += core-de212.o 5 4 obj-y += core-fsf.o 6 5 obj-y += core-sample_controller.o 7 - obj-$(CONFIG_SOFTMMU) += monitor.o 6 + obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o 8 7 obj-y += xtensa-isa.o 9 8 obj-y += translate.o op_helper.o helper.o cpu.o 10 9 obj-y += gdbstub.o

+22 -4

target/xtensa/cpu.c

··· 45 45 46 46 static bool xtensa_cpu_has_work(CPUState *cs) 47 47 { 48 + #ifndef CONFIG_USER_ONLY 48 49 XtensaCPU *cpu = XTENSA_CPU(cs); 49 50 50 51 return !cpu->env.runstall && cpu->env.pending_irq_level; 52 + #else 53 + return true; 54 + #endif 51 55 } 52 56 53 57 /* CPUClass::reset() */ ··· 62 66 env->exception_taken = 0; 63 67 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; 64 68 env->sregs[LITBASE] &= ~1; 69 + #ifndef CONFIG_USER_ONLY 65 70 env->sregs[PS] = xtensa_option_enabled(env->config, 66 71 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 72 + env->pending_irq_level = 0; 73 + #else 74 + env->sregs[PS] = 75 + (xtensa_option_enabled(env->config, 76 + XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) | 77 + PS_UM | (3 << PS_RING_SHIFT); 78 + #endif 67 79 env->sregs[VECBASE] = env->config->vecbase; 68 80 env->sregs[IBREAKENABLE] = 0; 69 81 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; ··· 73 85 env->sregs[CONFIGID0] = env->config->configid[0]; 74 86 env->sregs[CONFIGID1] = env->config->configid[1]; 75 87 76 - env->pending_irq_level = 0; 88 + #ifndef CONFIG_USER_ONLY 77 89 reset_mmu(env); 78 90 s->halted = env->runstall; 91 + #endif 79 92 } 80 93 81 94 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) ··· 104 117 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 105 118 { 106 119 CPUState *cs = CPU(dev); 107 - XtensaCPU *cpu = XTENSA_CPU(dev); 108 120 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 109 121 Error *local_err = NULL; 110 122 111 - xtensa_irq_init(&cpu->env); 123 + #ifndef CONFIG_USER_ONLY 124 + xtensa_irq_init(&XTENSA_CPU(dev)->env); 125 + #endif 112 126 113 127 cpu_exec_realizefn(cs, &local_err); 114 128 if (local_err != NULL) { ··· 133 147 cs->env_ptr = env; 134 148 env->config = xcc->config; 135 149 150 + #ifndef CONFIG_USER_ONLY 136 151 env->address_space_er = g_malloc(sizeof(*env->address_space_er)); 137 152 env->system_er = g_malloc(sizeof(*env->system_er)); 138 153 memory_region_init_io(env->system_er, NULL, NULL, env, "er", 139 154 UINT64_C(0x100000000)); 140 155 address_space_init(env->address_space_er, env->system_er, "ER"); 156 + #endif 141 157 } 142 158 143 159 static const VMStateDescription vmstate_xtensa_cpu = { ··· 166 182 cc->gdb_read_register = xtensa_cpu_gdb_read_register; 167 183 cc->gdb_write_register = xtensa_cpu_gdb_write_register; 168 184 cc->gdb_stop_before_watchpoint = true; 169 - #ifndef CONFIG_USER_ONLY 185 + #ifdef CONFIG_USER_ONLY 186 + cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault; 187 + #else 170 188 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; 171 189 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; 172 190 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;

+41 -19

target/xtensa/cpu.h

··· 31 31 #define ALIGNED_ONLY 32 32 #define TARGET_LONG_BITS 32 33 33 34 + /* Xtensa processors have a weak memory model */ 35 + #define TCG_GUEST_DEFAULT_MO (0) 36 + 34 37 #define CPUArchState struct CPUXtensaState 35 38 36 39 #include "qemu-common.h" ··· 41 44 #define NB_MMU_MODES 4 42 45 43 46 #define TARGET_PHYS_ADDR_SPACE_BITS 32 47 + #ifdef CONFIG_USER_ONLY 48 + #define TARGET_VIRT_ADDR_SPACE_BITS 30 49 + #else 44 50 #define TARGET_VIRT_ADDR_SPACE_BITS 32 51 + #endif 45 52 #define TARGET_PAGE_BITS 12 46 53 47 54 enum { ··· 173 180 174 181 #define PS_OWB 0xf00 175 182 #define PS_OWB_SHIFT 8 183 + #define PS_OWB_LEN 4 176 184 177 185 #define PS_CALLINC 0x30000 178 186 #define PS_CALLINC_SHIFT 16 ··· 310 318 311 319 typedef struct XtensaGdbReg { 312 320 int targno; 321 + unsigned flags; 313 322 int type; 314 323 int group; 315 324 unsigned size; ··· 434 443 } fregs[16]; 435 444 float_status fp_status; 436 445 446 + #ifndef CONFIG_USER_ONLY 437 447 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 438 448 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 439 449 unsigned autorefill_idx; ··· 446 456 uint64_t time_base; 447 457 uint64_t ccount_time; 448 458 uint32_t ccount_base; 459 + #endif 449 460 450 461 int exception_taken; 451 462 int yield_needed; ··· 480 491 481 492 #define ENV_OFFSET offsetof(XtensaCPU, env) 482 493 494 + 495 + int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, 496 + int mmu_idx); 483 497 void xtensa_cpu_do_interrupt(CPUState *cpu); 484 498 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 485 499 void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, ··· 527 541 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); 528 542 void xtensa_sync_window_from_phys(CPUXtensaState *env); 529 543 void xtensa_sync_phys_from_window(CPUXtensaState *env); 530 - uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way); 531 - void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 532 - uint32_t *vpn, uint32_t wi, uint32_t *ei); 533 - int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 534 - uint32_t *pwi, uint32_t *pei, uint8_t *pring); 535 - void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 536 - xtensa_tlb_entry *entry, bool dtlb, 537 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 538 - void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 539 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 540 - int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 541 - uint32_t vaddr, int is_write, int mmu_idx, 542 - uint32_t *paddr, uint32_t *page_size, unsigned *access); 543 - void reset_mmu(CPUXtensaState *env); 544 - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); 544 + void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); 545 + void xtensa_restore_owb(CPUXtensaState *env); 545 546 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); 546 - static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 547 - { 548 - return env->system_er; 549 - } 550 547 551 548 static inline void xtensa_select_static_vectors(CPUXtensaState *env, 552 549 unsigned n) ··· 600 597 } 601 598 } 602 599 600 + #ifndef CONFIG_USER_ONLY 601 + uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 602 + bool dtlb, uint32_t way); 603 + void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 604 + uint32_t *vpn, uint32_t wi, uint32_t *ei); 605 + int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 606 + uint32_t *pwi, uint32_t *pei, uint8_t *pring); 607 + void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 608 + xtensa_tlb_entry *entry, bool dtlb, 609 + unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 610 + void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 611 + unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 612 + int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 613 + uint32_t vaddr, int is_write, int mmu_idx, 614 + uint32_t *paddr, uint32_t *page_size, unsigned *access); 615 + void reset_mmu(CPUXtensaState *env); 616 + void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); 617 + 618 + static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 619 + { 620 + return env->system_er; 621 + } 622 + 603 623 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, 604 624 bool dtlb, unsigned wi, unsigned ei) 605 625 { ··· 607 627 env->dtlb[wi] + ei : 608 628 env->itlb[wi] + ei; 609 629 } 630 + #endif 610 631 611 632 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) 612 633 { ··· 619 640 #define MMU_MODE1_SUFFIX _ring1 620 641 #define MMU_MODE2_SUFFIX _ring2 621 642 #define MMU_MODE3_SUFFIX _ring3 643 + #define MMU_USER_IDX 3 622 644 623 645 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 624 646 {

+12 -2

target/xtensa/gdbstub.c

··· 28 28 XtensaCPU *cpu = XTENSA_CPU(cs); 29 29 CPUXtensaState *env = &cpu->env; 30 30 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; 31 + #ifdef CONFIG_USER_ONLY 32 + int num_regs = env->config->gdb_regmap.num_core_regs; 33 + #else 34 + int num_regs = env->config->gdb_regmap.num_regs; 35 + #endif 31 36 unsigned i; 32 37 33 - if (n < 0 || n >= env->config->gdb_regmap.num_regs) { 38 + if (n < 0 || n >= num_regs) { 34 39 return 0; 35 40 } 36 41 ··· 81 86 CPUXtensaState *env = &cpu->env; 82 87 uint32_t tmp; 83 88 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; 89 + #ifdef CONFIG_USER_ONLY 90 + int num_regs = env->config->gdb_regmap.num_core_regs; 91 + #else 92 + int num_regs = env->config->gdb_regmap.num_regs; 93 + #endif 84 94 85 - if (n < 0 || n >= env->config->gdb_regmap.num_regs) { 95 + if (n < 0 || n >= num_regs) { 86 96 return 0; 87 97 } 88 98

+51 -8

target/xtensa/helper.c

··· 88 88 89 89 void xtensa_finalize_config(XtensaConfig *config) 90 90 { 91 - unsigned i, n = 0; 92 - 93 91 if (config->isa_internal) { 94 92 init_libisa(config); 95 93 } 96 - if (config->gdb_regmap.num_regs) { 97 - return; 98 - } 99 94 100 - for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) { 101 - n += (config->gdb_regmap.reg[i].type != 6); 95 + if (config->gdb_regmap.num_regs == 0 || 96 + config->gdb_regmap.num_core_regs == 0) { 97 + unsigned i; 98 + unsigned n_regs = 0; 99 + unsigned n_core_regs = 0; 100 + 101 + for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) { 102 + if (config->gdb_regmap.reg[i].type != 6) { 103 + ++n_regs; 104 + if ((config->gdb_regmap.reg[i].flags & 0x1) == 0) { 105 + ++n_core_regs; 106 + } 107 + } 108 + } 109 + if (config->gdb_regmap.num_regs == 0) { 110 + config->gdb_regmap.num_regs = n_regs; 111 + } 112 + if (config->gdb_regmap.num_core_regs == 0) { 113 + config->gdb_regmap.num_core_regs = n_core_regs; 114 + } 102 115 } 103 - config->gdb_regmap.num_regs = n; 104 116 } 105 117 106 118 void xtensa_register_core(XtensaConfigList *node) ··· 161 173 162 174 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 163 175 { 176 + #ifndef CONFIG_USER_ONLY 164 177 XtensaCPU *cpu = XTENSA_CPU(cs); 165 178 uint32_t paddr; 166 179 uint32_t page_size; ··· 175 188 return paddr; 176 189 } 177 190 return ~0; 191 + #else 192 + return addr; 193 + #endif 178 194 } 195 + 196 + #ifndef CONFIG_USER_ONLY 179 197 180 198 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) 181 199 { ··· 286 304 } 287 305 check_interrupts(env); 288 306 } 307 + #else 308 + void xtensa_cpu_do_interrupt(CPUState *cs) 309 + { 310 + } 311 + #endif 289 312 290 313 bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 291 314 { ··· 296 319 } 297 320 return false; 298 321 } 322 + 323 + #ifdef CONFIG_USER_ONLY 324 + 325 + int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, 326 + int mmu_idx) 327 + { 328 + XtensaCPU *cpu = XTENSA_CPU(cs); 329 + CPUXtensaState *env = &cpu->env; 330 + 331 + qemu_log_mask(CPU_LOG_INT, 332 + "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", 333 + __func__, rw, address, size); 334 + env->sregs[EXCVADDR] = address; 335 + env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE; 336 + cs->exception_index = EXC_USER; 337 + return 1; 338 + } 339 + 340 + #else 299 341 300 342 static void reset_tlb_mmu_all_ways(CPUXtensaState *env, 301 343 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) ··· 757 799 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); 758 800 } 759 801 } 802 + #endif

+4

target/xtensa/helper.h

··· 12 12 DEF_HELPER_2(movsp, void, env, i32) 13 13 DEF_HELPER_2(wsr_lbeg, void, env, i32) 14 14 DEF_HELPER_2(wsr_lend, void, env, i32) 15 + #ifndef CONFIG_USER_ONLY 15 16 DEF_HELPER_1(simcall, void, env) 17 + #endif 16 18 DEF_HELPER_1(dump_state, void, env) 17 19 20 + #ifndef CONFIG_USER_ONLY 18 21 DEF_HELPER_3(waiti, void, env, i32, i32) 19 22 DEF_HELPER_1(update_ccount, void, env) 20 23 DEF_HELPER_2(wsr_ccount, void, env, i32) ··· 35 38 DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32) 36 39 DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32) 37 40 DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32) 41 + #endif 38 42 39 43 DEF_HELPER_2(wur_fcr, void, env, i32) 40 44 DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_NO_RWG_SE, f32, f32)

+41 -9

target/xtensa/op_helper.c

··· 36 36 #include "qemu/timer.h" 37 37 #include "fpu/softfloat.h" 38 38 39 + #ifdef CONFIG_USER_ONLY 40 + /* tb_invalidate_phys_range */ 41 + #include "accel/tcg/translate-all.h" 42 + #endif 43 + 44 + #ifndef CONFIG_USER_ONLY 45 + 39 46 void xtensa_cpu_do_unaligned_access(CPUState *cs, 40 47 vaddr addr, MMUAccessType access_type, 41 48 int mmu_idx, uintptr_t retaddr) ··· 101 108 tb_invalidate_phys_addr(&address_space_memory, paddr); 102 109 } 103 110 } 111 + 112 + #else 113 + 114 + static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) 115 + { 116 + mmap_lock(); 117 + tb_invalidate_phys_range(vaddr, vaddr + 1); 118 + mmap_unlock(); 119 + } 120 + 121 + #endif 104 122 105 123 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) 106 124 { ··· 219 237 copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); 220 238 } 221 239 222 - static void rotate_window_abs(CPUXtensaState *env, uint32_t position) 240 + static void xtensa_rotate_window_abs(CPUXtensaState *env, uint32_t position) 223 241 { 224 242 xtensa_sync_phys_from_window(env); 225 243 env->sregs[WINDOW_BASE] = windowbase_bound(position, env); 226 244 xtensa_sync_window_from_phys(env); 227 245 } 228 246 229 - static void rotate_window(CPUXtensaState *env, uint32_t delta) 247 + void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta) 230 248 { 231 - rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); 249 + xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); 232 250 } 233 251 234 252 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) 235 253 { 236 - rotate_window_abs(env, v); 254 + xtensa_rotate_window_abs(env, v); 237 255 } 238 256 239 257 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) ··· 251 269 HELPER(window_check)(env, pc, callinc); 252 270 } 253 271 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm; 254 - rotate_window(env, callinc); 272 + xtensa_rotate_window(env, callinc); 255 273 env->sregs[WINDOW_START] |= 256 274 windowstart_bit(env->sregs[WINDOW_BASE], env); 257 275 } ··· 266 284 267 285 assert(n <= w); 268 286 269 - rotate_window(env, n); 287 + xtensa_rotate_window(env, n); 270 288 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | 271 289 (windowbase << PS_OWB_SHIFT) | PS_EXCM; 272 290 env->sregs[EPC1] = env->pc = pc; ··· 311 329 312 330 ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); 313 331 314 - rotate_window(env, -n); 332 + xtensa_rotate_window(env, -n); 315 333 if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) { 316 334 env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env); 317 335 } else { ··· 334 352 335 353 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) 336 354 { 337 - rotate_window(env, imm4); 355 + xtensa_rotate_window(env, imm4); 356 + } 357 + 358 + void xtensa_restore_owb(CPUXtensaState *env) 359 + { 360 + xtensa_rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); 338 361 } 339 362 340 363 void HELPER(restore_owb)(CPUXtensaState *env) 341 364 { 342 - rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT); 365 + xtensa_restore_owb(env); 343 366 } 344 367 345 368 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) ··· 375 398 376 399 cpu_dump_state(CPU(cpu), stderr, fprintf, 0); 377 400 } 401 + 402 + #ifndef CONFIG_USER_ONLY 378 403 379 404 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) 380 405 { ··· 888 913 } 889 914 env->sregs[DBREAKC + i] = v; 890 915 } 916 + #endif 891 917 892 918 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) 893 919 { ··· 1025 1051 1026 1052 uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr) 1027 1053 { 1054 + #ifndef CONFIG_USER_ONLY 1028 1055 return address_space_ldl(env->address_space_er, addr, 1029 1056 MEMTXATTRS_UNSPECIFIED, NULL); 1057 + #else 1058 + return 0; 1059 + #endif 1030 1060 } 1031 1061 1032 1062 void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr) 1033 1063 { 1064 + #ifndef CONFIG_USER_ONLY 1034 1065 address_space_stl(env->address_space_er, addr, data, 1035 1066 MEMTXATTRS_UNSPECIFIED, NULL); 1067 + #endif 1036 1068 }

+8 -3

target/xtensa/overlay_tool.h

··· 25 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 26 */ 27 27 28 - #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \ 29 - a1, a2, a3, a4, a5, a6) \ 30 - { .targno = (no), .type = (typ), .group = (grp), .size = (sz) }, 28 + #define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \ 29 + a1, a2, a3, a4, a5, a6) { \ 30 + .targno = (no), \ 31 + .flags = (fl), \ 32 + .type = (typ), \ 33 + .group = (grp), \ 34 + .size = (sz), \ 35 + }, 31 36 #define XTREG_END { .targno = -1 }, 32 37 33 38 #ifndef XCHAL_HAVE_DEPBITS

+76 -23

target/xtensa/translate.c

··· 345 345 346 346 static bool gen_check_privilege(DisasContext *dc) 347 347 { 348 - if (dc->cring) { 349 - gen_exception_cause(dc, PRIVILEGED_CAUSE); 350 - dc->is_jmp = DISAS_UPDATE; 351 - return false; 348 + #ifndef CONFIG_USER_ONLY 349 + if (!dc->cring) { 350 + return true; 352 351 } 353 - return true; 352 + #endif 353 + gen_exception_cause(dc, PRIVILEGED_CAUSE); 354 + dc->is_jmp = DISAS_UPDATE; 355 + return false; 354 356 } 355 357 356 358 static bool gen_check_cpenable(DisasContext *dc, unsigned cp) ··· 498 500 return true; 499 501 } 500 502 503 + #ifndef CONFIG_USER_ONLY 501 504 static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) 502 505 { 503 506 if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { ··· 519 522 tcg_gen_andi_i32(d, d, 0xfffffffc); 520 523 return false; 521 524 } 525 + #endif 522 526 523 527 static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 524 528 { 525 529 static bool (* const rsr_handler[256])(DisasContext *dc, 526 530 TCGv_i32 d, uint32_t sr) = { 531 + #ifndef CONFIG_USER_ONLY 527 532 [CCOUNT] = gen_rsr_ccount, 528 533 [INTSET] = gen_rsr_ccount, 529 534 [PTEVADDR] = gen_rsr_ptevaddr, 535 + #endif 530 536 }; 531 537 532 538 if (rsr_handler[sr]) { ··· 582 588 return false; 583 589 } 584 590 591 + #ifndef CONFIG_USER_ONLY 585 592 static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) 586 593 { 587 594 gen_helper_wsr_windowbase(cpu_env, v); ··· 797 804 } 798 805 return ret; 799 806 } 807 + #else 808 + static void gen_check_interrupts(DisasContext *dc) 809 + { 810 + } 811 + #endif 800 812 801 813 static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) 802 814 { ··· 808 820 [BR] = gen_wsr_br, 809 821 [LITBASE] = gen_wsr_litbase, 810 822 [ACCHI] = gen_wsr_acchi, 823 + #ifndef CONFIG_USER_ONLY 811 824 [WINDOW_BASE] = gen_wsr_windowbase, 812 825 [WINDOW_START] = gen_wsr_windowstart, 813 826 [PTEVADDR] = gen_wsr_ptevaddr, ··· 834 847 [CCOMPARE] = gen_wsr_ccompare, 835 848 [CCOMPARE + 1] = gen_wsr_ccompare, 836 849 [CCOMPARE + 2] = gen_wsr_ccompare, 850 + #endif 837 851 }; 838 852 839 853 if (wsr_handler[sr]) { ··· 878 892 } 879 893 } 880 894 895 + #ifndef CONFIG_USER_ONLY 881 896 static void gen_waiti(DisasContext *dc, uint32_t imm4) 882 897 { 883 898 TCGv_i32 pc = tcg_const_i32(dc->next_pc); ··· 894 909 tcg_temp_free(intlevel); 895 910 gen_jumpi_check_loop_end(dc, 0); 896 911 } 912 + #endif 897 913 898 914 static bool gen_window_check1(DisasContext *dc, unsigned r1) 899 915 { ··· 1215 1231 (i % 4) == 3 ? '\n' : ' '); 1216 1232 } 1217 1233 1234 + xtensa_sync_phys_from_window(env); 1218 1235 cpu_fprintf(f, "\n"); 1219 1236 1220 1237 for (i = 0; i < env->config->nareg; ++i) { 1221 - cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i], 1222 - (i % 4) == 3 ? '\n' : ' '); 1238 + cpu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]); 1239 + if (i % 4 == 3) { 1240 + bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0; 1241 + bool cw = env->sregs[WINDOW_BASE] == i / 4; 1242 + 1243 + cpu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' '); 1244 + } 1223 1245 } 1224 1246 1225 1247 if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { ··· 1590 1612 { 1591 1613 if ((!par[0] || gen_check_privilege(dc)) && 1592 1614 gen_window_check1(dc, arg[0]) && par[1]) { 1615 + #ifndef CONFIG_USER_ONLY 1593 1616 TCGv_i32 addr = tcg_temp_new_i32(); 1594 1617 1595 1618 tcg_gen_movi_i32(cpu_pc, dc->pc); 1596 1619 tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); 1597 1620 gen_helper_itlb_hit_test(cpu_env, addr); 1598 1621 tcg_temp_free(addr); 1622 + #endif 1599 1623 } 1600 1624 } 1601 1625 ··· 1604 1628 { 1605 1629 if (gen_check_privilege(dc) && 1606 1630 gen_window_check1(dc, arg[0])) { 1631 + #ifndef CONFIG_USER_ONLY 1607 1632 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1608 1633 1609 1634 gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); 1610 1635 /* This could change memory mapping, so exit tb */ 1611 1636 gen_jumpi_check_loop_end(dc, -1); 1612 1637 tcg_temp_free(dtlb); 1638 + #endif 1613 1639 } 1614 1640 } 1615 1641 ··· 1658 1684 gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); 1659 1685 } 1660 1686 if (par[2]) { 1687 + if (par[1]) { 1688 + tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); 1689 + } 1661 1690 tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); 1662 1691 } else { 1663 1692 tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); 1693 + if (par[1]) { 1694 + tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); 1695 + } 1664 1696 } 1665 1697 tcg_temp_free(addr); 1666 1698 } ··· 1817 1849 } 1818 1850 } 1819 1851 1852 + static void translate_memw(DisasContext *dc, const uint32_t arg[], 1853 + const uint32_t par[]) 1854 + { 1855 + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); 1856 + } 1857 + 1820 1858 static void translate_minmax(DisasContext *dc, const uint32_t arg[], 1821 1859 const uint32_t par[]) 1822 1860 { ··· 1967 2005 { 1968 2006 if (gen_check_privilege(dc) && 1969 2007 gen_window_check2(dc, arg[0], arg[1])) { 2008 + #ifndef CONFIG_USER_ONLY 1970 2009 TCGv_i32 dtlb = tcg_const_i32(par[0]); 1971 2010 1972 2011 tcg_gen_movi_i32(cpu_pc, dc->pc); 1973 2012 gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); 1974 2013 tcg_temp_free(dtlb); 2014 + #endif 1975 2015 } 1976 2016 } 1977 2017 ··· 2155 2195 { 2156 2196 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, 2157 2197 TCGv_i32 a2) = { 2198 + #ifndef CONFIG_USER_ONLY 2158 2199 gen_helper_rtlb0, 2159 2200 gen_helper_rtlb1, 2201 + #endif 2160 2202 }; 2161 2203 2162 2204 if (gen_check_privilege(dc) && ··· 2187 2229 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); 2188 2230 } 2189 2231 2232 + #ifdef CONFIG_USER_ONLY 2233 + static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) 2234 + { 2235 + } 2236 + #else 2237 + static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) 2238 + { 2239 + TCGv_i32 tpc = tcg_const_i32(dc->pc); 2240 + 2241 + gen_helper_check_atomctl(cpu_env, tpc, addr); 2242 + tcg_temp_free(tpc); 2243 + } 2244 + #endif 2245 + 2190 2246 static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], 2191 2247 const uint32_t par[]) 2192 2248 { 2193 2249 if (gen_window_check2(dc, arg[0], arg[1])) { 2194 - TCGLabel *label = gen_new_label(); 2195 2250 TCGv_i32 tmp = tcg_temp_local_new_i32(); 2196 2251 TCGv_i32 addr = tcg_temp_local_new_i32(); 2197 - TCGv_i32 tpc; 2198 2252 2199 2253 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); 2200 2254 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); 2201 2255 gen_load_store_alignment(dc, 2, addr, true); 2202 - 2203 - tpc = tcg_const_i32(dc->pc); 2204 - gen_helper_check_atomctl(cpu_env, tpc, addr); 2205 - tcg_gen_qemu_ld32u(cpu_R[arg[0]], addr, dc->cring); 2206 - tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[arg[0]], 2207 - cpu_SR[SCOMPARE1], label); 2208 - 2209 - tcg_gen_qemu_st32(tmp, addr, dc->cring); 2210 - 2211 - gen_set_label(label); 2212 - tcg_temp_free(tpc); 2256 + gen_check_atomctl(dc, addr); 2257 + tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1], 2258 + tmp, dc->cring, MO_32); 2213 2259 tcg_temp_free(addr); 2214 2260 tcg_temp_free(tmp); 2215 2261 } ··· 2261 2307 static void translate_simcall(DisasContext *dc, const uint32_t arg[], 2262 2308 const uint32_t par[]) 2263 2309 { 2310 + #ifndef CONFIG_USER_ONLY 2264 2311 if (semihosting_enabled()) { 2265 2312 if (gen_check_privilege(dc)) { 2266 2313 gen_helper_simcall(cpu_env); 2267 2314 } 2268 - } else { 2315 + } else 2316 + #endif 2317 + { 2269 2318 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); 2270 2319 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); 2271 2320 } ··· 2448 2497 const uint32_t par[]) 2449 2498 { 2450 2499 if (gen_check_privilege(dc)) { 2500 + #ifndef CONFIG_USER_ONLY 2451 2501 gen_waiti(dc, arg[0]); 2502 + #endif 2452 2503 } 2453 2504 } 2454 2505 ··· 2457 2508 { 2458 2509 if (gen_check_privilege(dc) && 2459 2510 gen_window_check2(dc, arg[0], arg[1])) { 2511 + #ifndef CONFIG_USER_ONLY 2460 2512 TCGv_i32 dtlb = tcg_const_i32(par[0]); 2461 2513 2462 2514 gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); 2463 2515 /* This could change memory mapping, so exit tb */ 2464 2516 gen_jumpi_check_loop_end(dc, -1); 2465 2517 tcg_temp_free(dtlb); 2518 + #endif 2466 2519 } 2467 2520 } 2468 2521 ··· 2822 2875 .translate = translate_extui, 2823 2876 }, { 2824 2877 .name = "extw", 2825 - .translate = translate_nop, 2878 + .translate = translate_memw, 2826 2879 }, { 2827 2880 .name = "hwwdtlba", 2828 2881 .translate = translate_ill, ··· 2939 2992 .par = (const uint32_t[]){TCG_COND_GEU}, 2940 2993 }, { 2941 2994 .name = "memw", 2942 - .translate = translate_nop, 2995 + .translate = translate_memw, 2943 2996 }, { 2944 2997 .name = "min", 2945 2998 .translate = translate_minmax,