jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/arm: Implement the IRG instruction
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Richard Henderson
and committed by
Peter Maydell
da54941f
81ae05fa
+98
+1
target/arm/Makefile.objs
+1
target/arm/Makefile.objs
+2
target/arm/helper-a64.h
+2
target/arm/helper-a64.h
+5
target/arm/internals.h
+5
target/arm/internals.h
+72
target/arm/mte_helper.c
+72
target/arm/mte_helper.c
···
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/*
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* ARM v8.5-MemTag Operations
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*
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* Copyright (c) 2020 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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+
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static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)
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{
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if (exclude == 0xffff) {
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return 0;
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}
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if (offset == 0) {
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while (exclude & (1 << tag)) {
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tag = (tag + 1) & 15;
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}
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} else {
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do {
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do {
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tag = (tag + 1) & 15;
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} while (exclude & (1 << tag));
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} while (--offset > 0);
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}
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return tag;
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}
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uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
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{
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int rtag;
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/*
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* Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if
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* GCR_EL1.RRND==0, always producing deterministic results.
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*/
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uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16);
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int start = extract32(env->cp15.rgsr_el1, 0, 4);
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int seed = extract32(env->cp15.rgsr_el1, 8, 16);
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int offset, i;
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/* RandomTag */
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for (i = offset = 0; i < 4; ++i) {
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/* NextRandomTagBit */
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int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^
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extract32(seed, 2, 1) ^ extract32(seed, 0, 1));
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seed = (top << 15) | (seed >> 1);
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offset |= top << i;
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}
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rtag = choose_nonexcluded_tag(start, offset, exclude);
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env->cp15.rgsr_el1 = rtag | (seed << 8);
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return address_with_allocation_tag(rn, rtag);
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}
+18
target/arm/translate-a64.c
+18
target/arm/translate-a64.c
···
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return clean;
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}
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/* Insert a zero tag into src, with the result at dst. */
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static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src)
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{
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tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4));
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}
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typedef struct DisasCompare64 {
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TCGCond cond;
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TCGv_i64 value;
···
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break;
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case 3: /* SDIV */
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handle_div(s, true, sf, rm, rn, rd);
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break;
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case 4: /* IRG */
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if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
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goto do_unallocated;
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}
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if (s->ata) {
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gen_helper_irg(cpu_reg_sp(s, rd), cpu_env,
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cpu_reg_sp(s, rn), cpu_reg(s, rm));
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} else {
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gen_address_with_allocation_tag0(cpu_reg_sp(s, rd),
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cpu_reg_sp(s, rn));
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}
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break;
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case 8: /* LSLV */
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handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);