sm501: Convert debug printfs to traces

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: caf97bf0c84a440896ddf020e84c312fa5c15076.1592686588.git.balaton@eik.bme.hu
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>

authored by

BALATON Zoltan and committed by

Gerd Hoffmann 5 years ago d8327a68 f018edc3

+25 -37

2 changed files

expand all

display

sm501.c

trace-events

+13 -37

hw/display/sm501.c

··· 39 39 #include "qemu/range.h" 40 40 #include "ui/pixel_ops.h" 41 41 #include "qemu/bswap.h" 42 - 43 - /*#define DEBUG_SM501*/ 44 - /*#define DEBUG_BITBLT*/ 45 - 46 - #ifdef DEBUG_SM501 47 - #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) 48 - #else 49 - #define SM501_DPRINTF(fmt, ...) do {} while (0) 50 - #endif 42 + #include "trace.h" 51 43 52 44 #define MMIO_BASE_OFFSET 0x3e00000 53 45 #define MMIO_SIZE 0x200000 ··· 871 863 { 872 864 SM501State *s = (SM501State *)opaque; 873 865 uint32_t ret = 0; 874 - SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr); 875 866 876 867 switch (addr) { 877 868 case SM501_SYSTEM_CONTROL: ··· 923 914 qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config" 924 915 "register read. addr=%" HWADDR_PRIx "\n", addr); 925 916 } 926 - 917 + trace_sm501_system_config_read(addr, ret); 927 918 return ret; 928 919 } 929 920 ··· 931 922 uint64_t value, unsigned size) 932 923 { 933 924 SM501State *s = (SM501State *)opaque; 934 - SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", 935 - (uint32_t)addr, (uint32_t)value); 936 925 926 + trace_sm501_system_config_write((uint32_t)addr, (uint32_t)value); 937 927 switch (addr) { 938 928 case SM501_SYSTEM_CONTROL: 939 929 s->system_control &= 0x10DB0000; ··· 1019 1009 qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read." 1020 1010 " addr=0x%" HWADDR_PRIx "\n", addr); 1021 1011 } 1022 - 1023 - SM501_DPRINTF("sm501 i2c regs : read addr=%" HWADDR_PRIx " val=%x\n", 1024 - addr, ret); 1012 + trace_sm501_i2c_read((uint32_t)addr, ret); 1025 1013 return ret; 1026 1014 } 1027 1015 ··· 1029 1017 unsigned size) 1030 1018 { 1031 1019 SM501State *s = (SM501State *)opaque; 1032 - SM501_DPRINTF("sm501 i2c regs : write addr=%" HWADDR_PRIx 1033 - " val=%" PRIx64 "\n", addr, value); 1034 1020 1021 + trace_sm501_i2c_write((uint32_t)addr, (uint32_t)value); 1035 1022 switch (addr) { 1036 1023 case SM501_I2C_BYTE_COUNT: 1037 1024 s->i2c_byte_count = value & 0xf; ··· 1045 1032 s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0); 1046 1033 if (!res) { 1047 1034 int i; 1048 - SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x%x\n", 1049 - s->i2c_byte_count + 1, s->i2c_addr >> 1); 1050 1035 for (i = 0; i <= s->i2c_byte_count; i++) { 1051 1036 res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i], 1052 1037 !(s->i2c_addr & 1)); 1053 1038 if (res) { 1054 - SM501_DPRINTF("sm501 i2c : transfer failed" 1055 - " i=%d, res=%d\n", i, res); 1056 1039 s->i2c_status |= SM501_I2C_STATUS_ERROR; 1057 1040 return; 1058 1041 } 1059 1042 } 1060 1043 if (i) { 1061 - SM501_DPRINTF("sm501 i2c : transferred %d bytes\n", i); 1062 1044 s->i2c_status = SM501_I2C_STATUS_COMPLETE; 1063 1045 } 1064 1046 } 1065 1047 } else { 1066 - SM501_DPRINTF("sm501 i2c : end transfer\n"); 1067 1048 i2c_end_transfer(s->i2c_bus); 1068 1049 s->i2c_status &= ~SM501_I2C_STATUS_ERROR; 1069 1050 } ··· 1103 1084 static uint32_t sm501_palette_read(void *opaque, hwaddr addr) 1104 1085 { 1105 1086 SM501State *s = (SM501State *)opaque; 1106 - SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); 1087 + 1088 + trace_sm501_palette_read((uint32_t)addr); 1107 1089 1108 1090 /* TODO : consider BYTE/WORD access */ 1109 1091 /* TODO : consider endian */ ··· 1116 1098 uint32_t value) 1117 1099 { 1118 1100 SM501State *s = (SM501State *)opaque; 1119 - SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", 1120 - (int)addr, value); 1101 + 1102 + trace_sm501_palette_write((uint32_t)addr, value); 1121 1103 1122 1104 /* TODO : consider BYTE/WORD access */ 1123 1105 /* TODO : consider endian */ ··· 1132 1114 { 1133 1115 SM501State *s = (SM501State *)opaque; 1134 1116 uint32_t ret = 0; 1135 - SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr); 1136 1117 1137 1118 switch (addr) { 1138 1119 ··· 1237 1218 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1238 1219 "read. addr=%" HWADDR_PRIx "\n", addr); 1239 1220 } 1240 - 1221 + trace_sm501_disp_ctrl_read((uint32_t)addr, ret); 1241 1222 return ret; 1242 1223 } 1243 1224 ··· 1245 1226 uint64_t value, unsigned size) 1246 1227 { 1247 1228 SM501State *s = (SM501State *)opaque; 1248 - SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", 1249 - (unsigned)addr, (unsigned)value); 1250 1229 1230 + trace_sm501_disp_ctrl_write((uint32_t)addr, (uint32_t)value); 1251 1231 switch (addr) { 1252 1232 case SM501_DC_PANEL_CONTROL: 1253 1233 s->dc_panel_control = value & 0x0FFF73FF; ··· 1392 1372 { 1393 1373 SM501State *s = (SM501State *)opaque; 1394 1374 uint32_t ret = 0; 1395 - SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr); 1396 1375 1397 1376 switch (addr) { 1398 1377 case SM501_2D_SOURCE: ··· 1462 1441 qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register " 1463 1442 "read. addr=%" HWADDR_PRIx "\n", addr); 1464 1443 } 1465 - 1444 + trace_sm501_2d_engine_read((uint32_t)addr, ret); 1466 1445 return ret; 1467 1446 } 1468 1447 ··· 1470 1449 uint64_t value, unsigned size) 1471 1450 { 1472 1451 SM501State *s = (SM501State *)opaque; 1473 - SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", 1474 - (unsigned)addr, (unsigned)value); 1475 1452 1453 + trace_sm501_2d_engine_write((uint32_t)addr, (uint32_t)value); 1476 1454 switch (addr) { 1477 1455 case SM501_2D_SOURCE: 1478 1456 s->twoD_source = value; ··· 1830 1808 uint32_t local_mem_bytes) 1831 1809 { 1832 1810 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes); 1833 - SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s), 1834 - s->local_mem_size_index); 1835 1811 1836 1812 /* local memory */ 1837 1813 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",

+12

hw/display/trace-events

··· 161 161 # dpcd.c 162 162 dpcd_read(uint32_t addr, uint8_t val) "read addr:0x%"PRIx32" val:0x%02x" 163 163 dpcd_write(uint32_t addr, uint8_t val) "write addr:0x%"PRIx32" val:0x%02x" 164 + 165 + # sm501.c 166 + sm501_system_config_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 167 + sm501_system_config_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 168 + sm501_i2c_read(uint32_t addr, uint8_t val) "addr=0x%x, val=0x%x" 169 + sm501_i2c_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 170 + sm501_palette_read(uint32_t addr) "addr=0x%x" 171 + sm501_palette_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 172 + sm501_disp_ctrl_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 173 + sm501_disp_ctrl_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 174 + sm501_2d_engine_read(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x" 175 + sm501_2d_engine_write(uint32_t addr, uint32_t val) "addr=0x%x, val=0x%x"