jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/i386/pc: Extract e820 memory layout code
Suggested-by: Samuel Ortiz <sameo@linux.intel.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190818225414.22590-3-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
authored by
Philippe Mathieu-Daudé
and committed by
Paolo Bonzini
d6d059ca
42d400ac
+104
-72
+1
-1
hw/i386/Makefile.objs
+1
-1
hw/i386/Makefile.objs
+59
hw/i386/e820_memory_layout.c
+59
hw/i386/e820_memory_layout.c
···
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/*
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* QEMU BIOS e820 routines
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "qemu/osdep.h"
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#include "qemu/bswap.h"
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#include "e820_memory_layout.h"
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static size_t e820_entries;
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struct e820_table e820_reserve;
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struct e820_entry *e820_table;
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int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
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{
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int index = le32_to_cpu(e820_reserve.count);
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struct e820_entry *entry;
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if (type != E820_RAM) {
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/* old FW_CFG_E820_TABLE entry -- reservations only */
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if (index >= E820_NR_ENTRIES) {
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return -EBUSY;
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}
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entry = &e820_reserve.entry[index++];
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entry->address = cpu_to_le64(address);
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entry->length = cpu_to_le64(length);
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entry->type = cpu_to_le32(type);
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e820_reserve.count = cpu_to_le32(index);
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}
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/* new "etc/e820" file -- include ram too */
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e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
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e820_table[e820_entries].address = cpu_to_le64(address);
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e820_table[e820_entries].length = cpu_to_le64(length);
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e820_table[e820_entries].type = cpu_to_le32(type);
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e820_entries++;
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return e820_entries;
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}
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int e820_get_num_entries(void)
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{
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return e820_entries;
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}
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bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
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{
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if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
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*address = le64_to_cpu(e820_table[idx].address);
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*length = le64_to_cpu(e820_table[idx].length);
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return true;
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}
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return false;
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}
+42
hw/i386/e820_memory_layout.h
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hw/i386/e820_memory_layout.h
···
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/*
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* QEMU BIOS e820 routines
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef HW_I386_E820_H
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#define HW_I386_E820_H
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/* e820 types */
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#define E820_RAM 1
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#define E820_RESERVED 2
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#define E820_ACPI 3
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#define E820_NVS 4
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#define E820_UNUSABLE 5
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#define E820_NR_ENTRIES 16
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struct e820_entry {
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uint64_t address;
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uint64_t length;
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uint32_t type;
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} QEMU_PACKED __attribute((__aligned__(4)));
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struct e820_table {
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uint32_t count;
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struct e820_entry entry[E820_NR_ENTRIES];
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} QEMU_PACKED __attribute((__aligned__(4)));
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extern struct e820_table e820_reserve;
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extern struct e820_entry *e820_table;
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int e820_add_entry(uint64_t address, uint64_t length, uint32_t type);
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int e820_get_num_entries(void);
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bool e820_get_entry(int index, uint32_t type,
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uint64_t *address, uint64_t *length);
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#endif
+1
-60
hw/i386/pc.c
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-60
hw/i386/pc.c
···
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#include "sysemu/replay.h"
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#include "qapi/qmp/qerror.h"
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#include "config-devices.h"
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#include "e820_memory_layout.h"
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/* debug PC/ISA interrupts */
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//#define DEBUG_IRQ
···
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#define DPRINTF(fmt, ...)
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#endif
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#define E820_NR_ENTRIES 16
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struct e820_entry {
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uint64_t address;
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uint64_t length;
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uint32_t type;
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} QEMU_PACKED __attribute((__aligned__(4)));
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struct e820_table {
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uint32_t count;
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struct e820_entry entry[E820_NR_ENTRIES];
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} QEMU_PACKED __attribute((__aligned__(4)));
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static struct e820_table e820_reserve;
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static struct e820_entry *e820_table;
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static unsigned e820_entries;
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struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
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/* Physical Address of PVH entry point read from kernel ELF NOTE */
···
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/* XXX: send to all CPUs ? */
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/* XXX: add logic to handle multiple A20 line sources */
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x86_cpu_set_a20(cpu, level);
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}
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int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
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{
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int index = le32_to_cpu(e820_reserve.count);
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struct e820_entry *entry;
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if (type != E820_RAM) {
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/* old FW_CFG_E820_TABLE entry -- reservations only */
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if (index >= E820_NR_ENTRIES) {
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return -EBUSY;
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}
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entry = &e820_reserve.entry[index++];
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entry->address = cpu_to_le64(address);
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entry->length = cpu_to_le64(length);
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entry->type = cpu_to_le32(type);
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e820_reserve.count = cpu_to_le32(index);
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}
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/* new "etc/e820" file -- include ram too */
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e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
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e820_table[e820_entries].address = cpu_to_le64(address);
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e820_table[e820_entries].length = cpu_to_le64(length);
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e820_table[e820_entries].type = cpu_to_le32(type);
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e820_entries++;
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return e820_entries;
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}
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int e820_get_num_entries(void)
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{
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return e820_entries;
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}
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bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
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{
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if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
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*address = le64_to_cpu(e820_table[idx].address);
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*length = le64_to_cpu(e820_table[idx].length);
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return true;
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}
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return false;
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}
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/* Calculates initial APIC ID for a specific CPU index
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include/hw/i386/pc.h
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include/hw/i386/pc.h
···
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void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
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const CPUArchIdList *apic_ids, GArray *entry);
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/* e820 types */
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#define E820_RAM 1
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#define E820_RESERVED 2
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#define E820_ACPI 3
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#define E820_NVS 4
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#define E820_UNUSABLE 5
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int e820_add_entry(uint64_t, uint64_t, uint32_t);
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int e820_get_num_entries(void);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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extern GlobalProperty pc_compat_4_1[];
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extern const size_t pc_compat_4_1_len;
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