+1 -1

docs/pcie_pci_bridge.txt

··· 110 110 Implementation 111 111 ============== 112 112 The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI Express 113 113 - features as a PCI Express device (is_express=1). 113 113 + features as a PCI Express device. 114 114

-1

hw/block/nvme.c

··· 1360 1360 pc->vendor_id = PCI_VENDOR_ID_INTEL; 1361 1361 pc->device_id = 0x5845; 1362 1362 pc->revision = 2; 1363 1363 - pc->is_express = 1; 1364 1363 1365 1364 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1366 1365 dc->desc = "Non-Volatile Memory Express";

-1

hw/net/e1000e.c

··· 675 675 c->revision = 0; 676 676 c->romfile = "efi-e1000e.rom"; 677 677 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 678 678 - c->is_express = 1; 679 678 680 679 dc->desc = "Intel 82574L GbE Controller"; 681 680 dc->reset = e1000e_qdev_reset;

-1

hw/pci-bridge/pcie_pci_bridge.c

··· 170 170 DeviceClass *dc = DEVICE_CLASS(klass); 171 171 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 172 172 173 173 - k->is_express = 1; 174 173 k->is_bridge = 1; 175 174 k->vendor_id = PCI_VENDOR_ID_REDHAT; 176 175 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;

-1

hw/pci-bridge/pcie_root_port.c

··· 145 145 DeviceClass *dc = DEVICE_CLASS(klass); 146 146 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 147 147 148 148 - k->is_express = 1; 149 148 k->is_bridge = 1; 150 149 k->config_write = rp_write_config; 151 150 k->realize = rp_realize;

-1

hw/pci-bridge/xio3130_downstream.c

··· 178 178 DeviceClass *dc = DEVICE_CLASS(klass); 179 179 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 180 180 181 181 - k->is_express = 1; 182 181 k->is_bridge = 1; 183 182 k->config_write = xio3130_downstream_write_config; 184 183 k->realize = xio3130_downstream_realize;

-1

hw/pci-bridge/xio3130_upstream.c

··· 149 149 DeviceClass *dc = DEVICE_CLASS(klass); 150 150 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 151 151 152 152 - k->is_express = 1; 153 152 k->is_bridge = 1; 154 153 k->config_write = xio3130_upstream_write_config; 155 154 k->realize = xio3130_upstream_realize;

-1

hw/pci-host/xilinx-pcie.c

··· 297 297 k->device_id = 0x7021; 298 298 k->revision = 0; 299 299 k->class_id = PCI_CLASS_BRIDGE_HOST; 300 300 - k->is_express = true; 301 300 k->is_bridge = true; 302 301 k->realize = xilinx_pcie_root_realize; 303 302 k->exit = pci_bridge_exitfn;

+6 -2

hw/pci/pci.c

··· 2005 2005 { 2006 2006 PCIDevice *pci_dev = (PCIDevice *)qdev; 2007 2007 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2008 2008 + ObjectClass *klass = OBJECT_CLASS(pc); 2008 2009 Error *local_err = NULL; 2009 2010 bool is_default_rom; 2010 2011 2011 2011 - /* initialize cap_present for pci_is_express() and pci_config_size() */ 2012 2012 - if (pc->is_express) { 2012 2012 + /* initialize cap_present for pci_is_express() and pci_config_size(), 2013 2013 + * Note that hybrid PCIs are not set automatically and need to manage 2014 2014 + * QEMU_PCI_CAP_EXPRESS manually */ 2015 2015 + if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2016 2016 + !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2013 2017 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2014 2018 } 2015 2019

-4

hw/scsi/megasas.c

··· 2447 2447 uint16_t subsystem_id; 2448 2448 int ioport_bar; 2449 2449 int mmio_bar; 2450 2450 - bool is_express; 2451 2450 int osts; 2452 2451 const VMStateDescription *vmsd; 2453 2452 Property *props; ··· 2465 2464 .ioport_bar = 2, 2466 2465 .mmio_bar = 0, 2467 2466 .osts = MFI_1078_RM | 1, 2468 2468 - .is_express = false, 2469 2467 .vmsd = &vmstate_megasas_gen1, 2470 2468 .props = megasas_properties_gen1, 2471 2469 .interfaces = (InterfaceInfo[]) { ··· 2482 2480 .ioport_bar = 0, 2483 2481 .mmio_bar = 1, 2484 2482 .osts = MFI_GEN2_RM, 2485 2485 - .is_express = true, 2486 2483 .vmsd = &vmstate_megasas_gen2, 2487 2484 .props = megasas_properties_gen2, 2488 2485 .interfaces = (InterfaceInfo[]) { ··· 2506 2503 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; 2507 2504 pc->subsystem_id = info->subsystem_id; 2508 2505 pc->class_id = PCI_CLASS_STORAGE_RAID; 2509 2509 - pc->is_express = info->is_express; 2510 2506 e->mmio_bar = info->mmio_bar; 2511 2507 e->ioport_bar = info->ioport_bar; 2512 2508 e->osts = info->osts;

+8 -1

hw/usb/hcd-xhci.c

··· 3649 3649 DEFINE_PROP_END_OF_LIST(), 3650 3650 }; 3651 3651 3652 3652 + static void xhci_instance_init(Object *obj) 3653 3653 + { 3654 3654 + /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 3655 3655 + * line, therefore, no need to wait to realize like other devices */ 3656 3656 + PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; 3657 3657 + } 3658 3658 + 3652 3659 static void xhci_class_init(ObjectClass *klass, void *data) 3653 3660 { 3654 3661 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); ··· 3661 3668 k->realize = usb_xhci_realize; 3662 3669 k->exit = usb_xhci_exit; 3663 3670 k->class_id = PCI_CLASS_SERIAL_USB; 3664 3664 - k->is_express = 1; 3665 3671 } 3666 3672 3667 3673 static const TypeInfo xhci_info = { ··· 3669 3675 .parent = TYPE_PCI_DEVICE, 3670 3676 .instance_size = sizeof(XHCIState), 3671 3677 .class_init = xhci_class_init, 3678 3678 + .instance_init = xhci_instance_init, 3672 3679 .abstract = true, 3673 3680 .interfaces = (InterfaceInfo[]) { 3674 3681 { INTERFACE_PCIE_DEVICE },

+4 -1

hw/vfio/pci.c

··· 3113 3113 vdev->host.function = ~0U; 3114 3114 3115 3115 vdev->nv_gpudirect_clique = 0xFF; 3116 3116 + 3117 3117 + /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 3118 3118 + * line, therefore, no need to wait to realize like other devices */ 3119 3119 + pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 3116 3120 } 3117 3121 3118 3122 static Property vfio_pci_dev_properties[] = { ··· 3171 3175 pdc->exit = vfio_exitfn; 3172 3176 pdc->config_read = vfio_pci_read_config; 3173 3177 pdc->config_write = vfio_pci_write_config; 3174 3174 - pdc->is_express = 1; /* We might be */ 3175 3178 } 3176 3179 3177 3180 static const TypeInfo vfio_pci_dev_info = {

+8 -1

hw/xen/xen_pt.c

··· 937 937 DEFINE_PROP_END_OF_LIST(), 938 938 }; 939 939 940 940 + static void xen_pci_passthrough_instance_init(Object *obj) 941 941 + { 942 942 + /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 943 943 + * line, therefore, no need to wait to realize like other devices */ 944 944 + PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; 945 945 + } 946 946 + 940 947 static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data) 941 948 { 942 949 DeviceClass *dc = DEVICE_CLASS(klass); ··· 946 953 k->exit = xen_pt_unregister_device; 947 954 k->config_read = xen_pt_pci_read_config; 948 955 k->config_write = xen_pt_pci_write_config; 949 949 - k->is_express = 1; /* We might be */ 950 956 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 951 957 dc->desc = "Assign an host PCI device with Xen"; 952 958 dc->props = xen_pci_passthrough_properties; ··· 965 971 .instance_size = sizeof(XenPCIPassthroughState), 966 972 .instance_finalize = xen_pci_passthrough_finalize, 967 973 .class_init = xen_pci_passthrough_class_init, 974 974 + .instance_init = xen_pci_passthrough_instance_init, 968 975 .interfaces = (InterfaceInfo[]) { 969 976 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 970 977 { INTERFACE_PCIE_DEVICE },

-3

include/hw/pci/pci.h

··· 236 236 */ 237 237 int is_bridge; 238 238 239 239 - /* pcie stuff */ 240 240 - int is_express; /* is this device pci express? */ 241 241 - 242 239 /* rom bar */ 243 240 const char *romfile; 244 241 } PCIDeviceClass;