jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/xtensa: regenerate and re-import test_mmuhifi_c3 core
Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in
it. Fix that by regenerating test_mmuhifi_c3 core overlay and
re-importing it.
Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core")
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
+3154
-3001
+1
-2
target/xtensa/core-test_mmuhifi_c3.c
+1
-2
target/xtensa/core-test_mmuhifi_c3.c
···
27
27
28
28
#include "qemu/osdep.h"
29
29
#include "cpu.h"
30
-
#include "exec/exec-all.h"
31
30
#include "exec/gdbstub.h"
31
+
#include "qemu-common.h"
32
32
#include "qemu/host-utils.h"
33
33
34
34
#include "core-test_mmuhifi_c3/core-isa.h"
···
39
39
40
40
static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
41
41
.name = "test_mmuhifi_c3",
42
-
.options = XTENSA_OPTIONS,
43
42
.gdb_regmap = {
44
43
.reg = {
45
44
#include "core-test_mmuhifi_c3/gdb-config.inc.c"
+103
-13
target/xtensa/core-test_mmuhifi_c3/core-isa.h
+103
-13
target/xtensa/core-test_mmuhifi_c3/core-isa.h
···
1
1
/*
2
-
* Xtensa processor core configuration information.
3
-
*
4
-
* This file is subject to the terms and conditions of version 2.1 of the GNU
5
-
* Lesser General Public License as published by the Free Software Foundation.
2
+
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3
+
* processor CORE configuration
6
4
*
7
-
* Copyright (c) 1999-2009 Tensilica Inc.
5
+
* See <xtensa/config/core.h>, which includes this file, for more details.
8
6
*/
9
7
8
+
/* Xtensa processor core configuration information.
9
+
10
+
Copyright (c) 1999-2019 Tensilica Inc.
11
+
12
+
Permission is hereby granted, free of charge, to any person obtaining
13
+
a copy of this software and associated documentation files (the
14
+
"Software"), to deal in the Software without restriction, including
15
+
without limitation the rights to use, copy, modify, merge, publish,
16
+
distribute, sublicense, and/or sell copies of the Software, and to
17
+
permit persons to whom the Software is furnished to do so, subject to
18
+
the following conditions:
19
+
20
+
The above copyright notice and this permission notice shall be included
21
+
in all copies or substantial portions of the Software.
22
+
23
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26
+
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27
+
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28
+
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29
+
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
30
+
10
31
#ifndef XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H
11
32
#define XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H
33
+
12
34
13
35
/****************************************************************************
14
36
Parameters Useful for Any Code, USER or PRIVILEGED
···
32
54
#define XCHAL_HAVE_DEBUG 1 /* debug option */
33
55
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
34
56
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57
+
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
35
58
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
36
59
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
37
60
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
···
59
82
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
60
83
#define XCHAL_HAVE_PRID 1 /* processor ID register */
61
84
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
85
+
#define XCHAL_HAVE_MX 1 /* MX core (Tensilica internal) */
62
86
#define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */
63
87
#define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */
88
+
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
89
+
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
90
+
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
64
91
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
65
92
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
66
93
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
67
94
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
68
95
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
69
96
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
70
-
#define XCHAL_HAVE_FP 0 /* floating point pkg */
97
+
#define XCHAL_HAVE_FP 0 /* single prec floating point */
98
+
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
99
+
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
100
+
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
101
+
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
71
102
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
103
+
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
104
+
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
105
+
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
106
+
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
72
107
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
73
108
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
74
109
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
75
110
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
111
+
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
76
112
#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
113
+
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
114
+
#define XCHAL_HAVE_HIFI_MINI 0
77
115
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
116
+
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
117
+
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
118
+
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
119
+
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
120
+
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
121
+
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
122
+
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
123
+
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
124
+
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
125
+
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
126
+
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
127
+
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
78
128
79
129
80
130
/*----------------------------------------------------------------------
81
131
MISC
82
132
----------------------------------------------------------------------*/
83
133
134
+
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
84
135
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
85
136
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
86
137
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
138
+
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
139
+
(1 = 5-stage, 2 = 7-stage) */
87
140
/* In T1050, applies to selected core load and store instructions (see ISA): */
88
141
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
89
142
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
90
143
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
91
144
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
92
145
93
-
#define XCHAL_SW_VERSION 800000 /* sw version of this header */
146
+
#define XCHAL_SW_VERSION 1000006 /* sw version of this header */
94
147
95
148
#define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name
96
149
(CoreID) set in the Xtensa
97
150
Processor Generator */
98
151
99
-
#define XCHAL_CORE_DESCRIPTION "test_mmuhifi_c3"
100
152
#define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */
101
153
102
154
/*
···
136
188
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
137
189
#define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */
138
190
191
+
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
192
+
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
193
+
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
194
+
139
195
140
196
141
197
···
172
228
#define XCHAL_ICACHE_ACCESS_SIZE 8
173
229
#define XCHAL_DCACHE_ACCESS_SIZE 8
174
230
231
+
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
232
+
175
233
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
176
234
#define XCHAL_CA_BITS 4
177
235
···
186
244
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
187
245
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
188
246
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
247
+
248
+
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
189
249
190
250
191
251
/*----------------------------------------------------------------------
···
261
321
#define XCHAL_INTTYPE_MASK_TIMER 0x00000140
262
322
#define XCHAL_INTTYPE_MASK_NMI 0x00000000
263
323
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
324
+
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
264
325
265
326
/* Interrupt numbers assigned to specific interrupt sources: */
266
327
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
···
273
334
274
335
275
336
/*
276
-
* External interrupt vectors/levels.
337
+
* External interrupt mapping.
277
338
* These macros describe how Xtensa processor interrupt numbers
278
339
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
279
340
* map to external BInterrupt<n> pins, for those interrupts
···
281
342
* See the Xtensa processor databook for more details.
282
343
*/
283
344
284
-
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
345
+
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
285
346
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
286
347
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
287
348
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
···
291
352
#define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */
292
353
#define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */
293
354
#define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */
355
+
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
356
+
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
357
+
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
358
+
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
359
+
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
360
+
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
361
+
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
362
+
#define XCHAL_INT9_EXTNUM 6 /* (intlevel 1) */
363
+
#define XCHAL_INT10_EXTNUM 7 /* (intlevel 1) */
364
+
#define XCHAL_INT11_EXTNUM 8 /* (intlevel 1) */
294
365
295
366
296
367
/*----------------------------------------------------------------------
···
300
371
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
301
372
number: 1 == XEA1 (old)
302
373
2 == XEA2 (new)
303
-
0 == XEAX (extern) */
374
+
0 == XEAX (extern) or TX */
304
375
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
305
376
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
306
377
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
307
378
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
379
+
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
380
+
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
308
381
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
309
382
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
310
383
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
···
344
417
345
418
346
419
/*----------------------------------------------------------------------
347
-
DEBUG
420
+
DEBUG MODULE
348
421
----------------------------------------------------------------------*/
349
422
423
+
/* Misc */
424
+
#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
425
+
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
426
+
#define XCHAL_HAVE_DEBUG_JTAG 0 /* JTAG to debug module */
427
+
428
+
/* On-Chip Debug (OCD) */
350
429
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
351
430
#define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */
352
431
#define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */
353
-
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
432
+
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
433
+
#define XCHAL_HAVE_OCD_LS32DDR 0 /* L32DDR/S32DDR (faster OCD) */
434
+
435
+
/* TRAX (in core) */
436
+
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
437
+
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
438
+
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
439
+
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
440
+
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
441
+
442
+
/* Perf counters */
443
+
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
354
444
355
445
356
446
/*----------------------------------------------------------------------
+97
-17
target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
+97
-17
target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
···
1
1
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
2
2
3
-
Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3
+
Copyright (c) 2003-2019 Tensilica Inc.
4
4
5
-
This file is part of GDB.
5
+
Permission is hereby granted, free of charge, to any person obtaining
6
+
a copy of this software and associated documentation files (the
7
+
"Software"), to deal in the Software without restriction, including
8
+
without limitation the rights to use, copy, modify, merge, publish,
9
+
distribute, sublicense, and/or sell copies of the Software, and to
10
+
permit persons to whom the Software is furnished to do so, subject to
11
+
the following conditions:
6
12
7
-
This program is free software; you can redistribute it and/or modify
8
-
it under the terms of the GNU General Public License as published by
9
-
the Free Software Foundation; either version 3 of the License, or
10
-
(at your option) any later version.
13
+
The above copyright notice and this permission notice shall be included
14
+
in all copies or substantial portions of the Software.
11
15
12
-
This program is distributed in the hope that it will be useful,
13
-
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
-
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
-
GNU General Public License for more details.
16
-
17
-
You should have received a copy of the GNU General Public License
18
-
along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
-
20
-
/* idx ofs bi sz al targno flags cp typ group name */
16
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19
+
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20
+
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21
+
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22
+
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
21
23
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
22
24
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
23
25
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
···
58
60
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
59
61
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
60
62
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
61
-
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
62
-
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
63
+
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
64
+
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
63
65
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
64
66
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
65
67
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
···
137
139
XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
138
140
XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
139
141
XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
142
+
XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
143
+
0,0,&xtensa_mask0,0,0,0)
144
+
XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
145
+
0,0,&xtensa_mask1,0,0,0)
146
+
XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
147
+
0,0,&xtensa_mask2,0,0,0)
148
+
XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
149
+
0,0,&xtensa_mask3,0,0,0)
150
+
XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
151
+
0,0,&xtensa_mask4,0,0,0)
152
+
XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
153
+
0,0,&xtensa_mask5,0,0,0)
154
+
XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
155
+
0,0,&xtensa_mask6,0,0,0)
156
+
XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
157
+
0,0,&xtensa_mask7,0,0,0)
158
+
XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
159
+
0,0,&xtensa_mask8,0,0,0)
160
+
XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
161
+
0,0,&xtensa_mask9,0,0,0)
162
+
XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
163
+
0,0,&xtensa_mask10,0,0,0)
164
+
XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
165
+
0,0,&xtensa_mask11,0,0,0)
166
+
XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
167
+
0,0,&xtensa_mask12,0,0,0)
168
+
XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
169
+
0,0,&xtensa_mask13,0,0,0)
170
+
XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
171
+
0,0,&xtensa_mask14,0,0,0)
172
+
XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
173
+
0,0,&xtensa_mask15,0,0,0)
174
+
XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
175
+
0,0,&xtensa_mask16,0,0,0)
176
+
XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
177
+
0,0,&xtensa_mask17,0,0,0)
178
+
XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
179
+
0,0,&xtensa_mask18,0,0,0)
180
+
XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
181
+
0,0,&xtensa_mask19,0,0,0)
182
+
XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
183
+
0,0,&xtensa_mask20,0,0,0)
184
+
XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
185
+
0,0,&xtensa_mask21,0,0,0)
186
+
XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
187
+
0,0,&xtensa_mask22,0,0,0)
188
+
XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
189
+
0,0,&xtensa_mask23,0,0,0)
190
+
XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
191
+
0,0,&xtensa_mask24,0,0,0)
192
+
XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
193
+
0,0,&xtensa_mask25,0,0,0)
194
+
XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
195
+
0,0,&xtensa_mask26,0,0,0)
196
+
XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
197
+
0,0,&xtensa_mask27,0,0,0)
198
+
XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
199
+
0,0,&xtensa_mask28,0,0,0)
200
+
XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
201
+
0,0,&xtensa_mask29,0,0,0)
202
+
XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
203
+
0,0,&xtensa_mask30,0,0,0)
204
+
XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
205
+
0,0,&xtensa_mask31,0,0,0)
206
+
XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
207
+
0,0,&xtensa_mask32,0,0,0)
208
+
XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
209
+
0,0,&xtensa_mask33,0,0,0)
210
+
XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
211
+
0,0,&xtensa_mask34,0,0,0)
212
+
XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
213
+
0,0,&xtensa_mask35,0,0,0)
214
+
XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
215
+
0,0,&xtensa_mask36,0,0,0)
216
+
XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
217
+
0,0,&xtensa_mask37,0,0,0)
218
+
XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
219
+
0,0,&xtensa_mask38,0,0,0)
140
220
XTREG_END
+2953
-2969
target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
+2953
-2969
target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
···
1
1
/* Xtensa configuration-specific ISA information.
2
-
Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
3
2
4
-
This file is part of BFD, the Binary File Descriptor library.
3
+
Copyright (c) 2003-2019 Tensilica Inc.
5
4
6
-
This program is free software; you can redistribute it and/or
7
-
modify it under the terms of the GNU General Public License as
8
-
published by the Free Software Foundation; either version 3 of the
9
-
License, or (at your option) any later version.
5
+
Permission is hereby granted, free of charge, to any person obtaining
6
+
a copy of this software and associated documentation files (the
7
+
"Software"), to deal in the Software without restriction, including
8
+
without limitation the rights to use, copy, modify, merge, publish,
9
+
distribute, sublicense, and/or sell copies of the Software, and to
10
+
permit persons to whom the Software is furnished to do so, subject to
11
+
the following conditions:
10
12
11
-
This program is distributed in the hope that it will be useful,
12
-
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
-
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14
-
General Public License for more details.
13
+
The above copyright notice and this permission notice shall be included
14
+
in all copies or substantial portions of the Software.
15
15
16
-
You should have received a copy of the GNU General Public License
17
-
along with this program; if not, write to the Free Software
18
-
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
19
-
02110-1301, USA. */
16
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19
+
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20
+
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21
+
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22
+
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
20
23
21
-
#include "qemu/osdep.h"
22
24
#include "xtensa-isa.h"
23
25
#include "xtensa-isa-internal.h"
24
26
···
32
34
{ "BR", 4, 0 },
33
35
{ "PTEVADDR", 83, 0 },
34
36
{ "DDR", 104, 0 },
35
-
{ "176", 176, 0 },
36
-
{ "208", 208, 0 },
37
+
{ "CONFIGID0", 176, 0 },
38
+
{ "CONFIGID1", 208, 0 },
37
39
{ "INTERRUPT", 226, 0 },
38
40
{ "INTCLEAR", 227, 0 },
39
41
{ "CCOUNT", 234, 0 },
···
8634
8636
}
8635
8637
8636
8638
static unsigned
8639
+
Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
8640
+
{
8641
+
unsigned tie_t = 0;
8642
+
tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
8643
+
return tie_t;
8644
+
}
8645
+
8646
+
static void
8647
+
Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8648
+
{
8649
+
uint32 tie_t;
8650
+
tie_t = (val << 28) >> 28;
8651
+
insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
8652
+
}
8653
+
8654
+
static unsigned
8655
+
Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
8656
+
{
8657
+
unsigned tie_t = 0;
8658
+
tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
8659
+
return tie_t;
8660
+
}
8661
+
8662
+
static void
8663
+
Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
8664
+
{
8665
+
uint32 tie_t;
8666
+
tie_t = (val << 28) >> 28;
8667
+
insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
8668
+
}
8669
+
8670
+
static unsigned
8637
8671
Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
8638
8672
{
8639
8673
unsigned tie_t = 0;
···
8794
8828
FIELD_ae_r20,
8795
8829
FIELD_ae_r10,
8796
8830
FIELD_ae_s20,
8831
+
FIELD_ae_fld_ohba,
8832
+
FIELD_ae_fld_ohba2,
8797
8833
FIELD_op0_s3,
8798
8834
FIELD_ftsf12,
8799
8835
FIELD_ftsf13,
···
9184
9220
INTERFACE_RMPINT_In
9185
9221
};
9186
9222
9187
-
9223
+
9188
9224
/* Constant tables. */
9189
9225
9190
9226
/* constant table ai4c */
···
9254
9290
/* Instruction operands. */
9255
9291
9256
9292
static int
9257
-
Operand_soffsetx4_decode (uint32 *valp)
9293
+
OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
9258
9294
{
9259
-
unsigned soffsetx4_0, offset_0;
9260
-
offset_0 = *valp & 0x3ffff;
9261
-
soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
9262
-
*valp = soffsetx4_0;
9295
+
unsigned soffsetx4_out_0;
9296
+
unsigned soffsetx4_in_0;
9297
+
soffsetx4_in_0 = *valp & 0x3ffff;
9298
+
soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
9299
+
*valp = soffsetx4_out_0;
9263
9300
return 0;
9264
9301
}
9265
9302
9266
9303
static int
9267
-
Operand_soffsetx4_encode (uint32 *valp)
9304
+
OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
9268
9305
{
9269
-
unsigned offset_0, soffsetx4_0;
9270
-
soffsetx4_0 = *valp;
9271
-
offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
9272
-
*valp = offset_0;
9306
+
unsigned soffsetx4_in_0;
9307
+
unsigned soffsetx4_out_0;
9308
+
soffsetx4_out_0 = *valp;
9309
+
soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
9310
+
*valp = soffsetx4_in_0;
9273
9311
return 0;
9274
9312
}
9275
9313
9276
9314
static int
9277
-
Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
9315
+
OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
9278
9316
{
9279
-
*valp -= (pc & ~0x3);
9317
+
unsigned uimm12x8_out_0;
9318
+
unsigned uimm12x8_in_0;
9319
+
uimm12x8_in_0 = *valp & 0xfff;
9320
+
uimm12x8_out_0 = uimm12x8_in_0 << 3;
9321
+
*valp = uimm12x8_out_0;
9280
9322
return 0;
9281
9323
}
9282
9324
9283
9325
static int
9284
-
Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
9326
+
OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
9285
9327
{
9286
-
*valp += (pc & ~0x3);
9328
+
unsigned uimm12x8_in_0;
9329
+
unsigned uimm12x8_out_0;
9330
+
uimm12x8_out_0 = *valp;
9331
+
uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
9332
+
*valp = uimm12x8_in_0;
9287
9333
return 0;
9288
9334
}
9289
9335
9290
9336
static int
9291
-
Operand_uimm12x8_decode (uint32 *valp)
9337
+
OperandSem_opnd_sem_simm4_decode (uint32 *valp)
9292
9338
{
9293
-
unsigned uimm12x8_0, imm12_0;
9294
-
imm12_0 = *valp & 0xfff;
9295
-
uimm12x8_0 = imm12_0 << 3;
9296
-
*valp = uimm12x8_0;
9339
+
unsigned simm4_out_0;
9340
+
unsigned simm4_in_0;
9341
+
simm4_in_0 = *valp & 0xf;
9342
+
simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
9343
+
*valp = simm4_out_0;
9297
9344
return 0;
9298
9345
}
9299
9346
9300
9347
static int
9301
-
Operand_uimm12x8_encode (uint32 *valp)
9348
+
OperandSem_opnd_sem_simm4_encode (uint32 *valp)
9302
9349
{
9303
-
unsigned imm12_0, uimm12x8_0;
9304
-
uimm12x8_0 = *valp;
9305
-
imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
9306
-
*valp = imm12_0;
9307
-
return 0;
9308
-
}
9309
-
9310
-
static int
9311
-
Operand_simm4_decode (uint32 *valp)
9312
-
{
9313
-
unsigned simm4_0, mn_0;
9314
-
mn_0 = *valp & 0xf;
9315
-
simm4_0 = ((int) mn_0 << 28) >> 28;
9316
-
*valp = simm4_0;
9317
-
return 0;
9318
-
}
9319
-
9320
-
static int
9321
-
Operand_simm4_encode (uint32 *valp)
9322
-
{
9323
-
unsigned mn_0, simm4_0;
9324
-
simm4_0 = *valp;
9325
-
mn_0 = (simm4_0 & 0xf);
9326
-
*valp = mn_0;
9327
-
return 0;
9328
-
}
9329
-
9330
-
static int
9331
-
Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
9332
-
{
9333
-
return 0;
9334
-
}
9335
-
9336
-
static int
9337
-
Operand_arr_encode (uint32 *valp)
9338
-
{
9339
-
int error;
9340
-
error = (*valp & ~0xf) != 0;
9341
-
return error;
9342
-
}
9343
-
9344
-
static int
9345
-
Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
9346
-
{
9350
+
unsigned simm4_in_0;
9351
+
unsigned simm4_out_0;
9352
+
simm4_out_0 = *valp;
9353
+
simm4_in_0 = (simm4_out_0 & 0xf);
9354
+
*valp = simm4_in_0;
9347
9355
return 0;
9348
9356
}
9349
9357
9350
9358
static int
9351
-
Operand_ars_encode (uint32 *valp)
9352
-
{
9353
-
int error;
9354
-
error = (*valp & ~0xf) != 0;
9355
-
return error;
9356
-
}
9357
-
9358
-
static int
9359
-
Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
9359
+
OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
9360
9360
{
9361
9361
return 0;
9362
9362
}
9363
9363
9364
9364
static int
9365
-
Operand_art_encode (uint32 *valp)
9365
+
OperandSem_opnd_sem_AR_encode (uint32 *valp)
9366
9366
{
9367
9367
int error;
9368
-
error = (*valp & ~0xf) != 0;
9368
+
error = (*valp >= 32);
9369
9369
return error;
9370
9370
}
9371
9371
9372
9372
static int
9373
-
Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
9373
+
OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
9374
9374
{
9375
9375
return 0;
9376
9376
}
9377
9377
9378
9378
static int
9379
-
Operand_ar0_encode (uint32 *valp)
9379
+
OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
9380
9380
{
9381
9381
int error;
9382
-
error = (*valp & ~0x1f) != 0;
9382
+
error = (*valp >= 32);
9383
9383
return error;
9384
9384
}
9385
9385
9386
9386
static int
9387
-
Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
9387
+
OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
9388
9388
{
9389
9389
return 0;
9390
9390
}
9391
9391
9392
9392
static int
9393
-
Operand_ar4_encode (uint32 *valp)
9393
+
OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
9394
9394
{
9395
9395
int error;
9396
-
error = (*valp & ~0x1f) != 0;
9396
+
error = (*valp >= 32);
9397
9397
return error;
9398
9398
}
9399
9399
9400
9400
static int
9401
-
Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
9401
+
OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
9402
9402
{
9403
9403
return 0;
9404
9404
}
9405
9405
9406
9406
static int
9407
-
Operand_ar8_encode (uint32 *valp)
9407
+
OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
9408
9408
{
9409
9409
int error;
9410
-
error = (*valp & ~0x1f) != 0;
9410
+
error = (*valp >= 32);
9411
9411
return error;
9412
9412
}
9413
9413
9414
9414
static int
9415
-
Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
9415
+
OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
9416
9416
{
9417
9417
return 0;
9418
9418
}
9419
9419
9420
9420
static int
9421
-
Operand_ar12_encode (uint32 *valp)
9421
+
OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
9422
9422
{
9423
9423
int error;
9424
-
error = (*valp & ~0x1f) != 0;
9424
+
error = (*valp >= 32);
9425
9425
return error;
9426
9426
}
9427
9427
9428
9428
static int
9429
-
Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
9429
+
OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
9430
9430
{
9431
9431
return 0;
9432
9432
}
9433
9433
9434
9434
static int
9435
-
Operand_ars_entry_encode (uint32 *valp)
9435
+
OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
9436
9436
{
9437
9437
int error;
9438
-
error = (*valp & ~0x1f) != 0;
9438
+
error = (*valp >= 32);
9439
9439
return error;
9440
9440
}
9441
9441
9442
9442
static int
9443
-
Operand_immrx4_decode (uint32 *valp)
9443
+
OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
9444
9444
{
9445
-
unsigned immrx4_0, r_0;
9446
-
r_0 = *valp & 0xf;
9447
-
immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
9448
-
*valp = immrx4_0;
9445
+
unsigned immrx4_out_0;
9446
+
unsigned immrx4_in_0;
9447
+
immrx4_in_0 = *valp & 0xf;
9448
+
immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
9449
+
*valp = immrx4_out_0;
9449
9450
return 0;
9450
9451
}
9451
9452
9452
9453
static int
9453
-
Operand_immrx4_encode (uint32 *valp)
9454
+
OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
9454
9455
{
9455
-
unsigned r_0, immrx4_0;
9456
-
immrx4_0 = *valp;
9457
-
r_0 = ((immrx4_0 >> 2) & 0xf);
9458
-
*valp = r_0;
9456
+
unsigned immrx4_in_0;
9457
+
unsigned immrx4_out_0;
9458
+
immrx4_out_0 = *valp;
9459
+
immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
9460
+
*valp = immrx4_in_0;
9459
9461
return 0;
9460
9462
}
9461
9463
9462
9464
static int
9463
-
Operand_lsi4x4_decode (uint32 *valp)
9465
+
OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
9464
9466
{
9465
-
unsigned lsi4x4_0, r_0;
9466
-
r_0 = *valp & 0xf;
9467
-
lsi4x4_0 = r_0 << 2;
9468
-
*valp = lsi4x4_0;
9467
+
unsigned lsi4x4_out_0;
9468
+
unsigned lsi4x4_in_0;
9469
+
lsi4x4_in_0 = *valp & 0xf;
9470
+
lsi4x4_out_0 = lsi4x4_in_0 << 2;
9471
+
*valp = lsi4x4_out_0;
9469
9472
return 0;
9470
9473
}
9471
9474
9472
9475
static int
9473
-
Operand_lsi4x4_encode (uint32 *valp)
9476
+
OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
9474
9477
{
9475
-
unsigned r_0, lsi4x4_0;
9476
-
lsi4x4_0 = *valp;
9477
-
r_0 = ((lsi4x4_0 >> 2) & 0xf);
9478
-
*valp = r_0;
9478
+
unsigned lsi4x4_in_0;
9479
+
unsigned lsi4x4_out_0;
9480
+
lsi4x4_out_0 = *valp;
9481
+
lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
9482
+
*valp = lsi4x4_in_0;
9479
9483
return 0;
9480
9484
}
9481
9485
9482
9486
static int
9483
-
Operand_simm7_decode (uint32 *valp)
9487
+
OperandSem_opnd_sem_simm7_decode (uint32 *valp)
9484
9488
{
9485
-
unsigned simm7_0, imm7_0;
9486
-
imm7_0 = *valp & 0x7f;
9487
-
simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
9488
-
*valp = simm7_0;
9489
+
unsigned simm7_out_0;
9490
+
unsigned simm7_in_0;
9491
+
simm7_in_0 = *valp & 0x7f;
9492
+
simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
9493
+
*valp = simm7_out_0;
9489
9494
return 0;
9490
9495
}
9491
9496
9492
9497
static int
9493
-
Operand_simm7_encode (uint32 *valp)
9498
+
OperandSem_opnd_sem_simm7_encode (uint32 *valp)
9494
9499
{
9495
-
unsigned imm7_0, simm7_0;
9496
-
simm7_0 = *valp;
9497
-
imm7_0 = (simm7_0 & 0x7f);
9498
-
*valp = imm7_0;
9500
+
unsigned simm7_in_0;
9501
+
unsigned simm7_out_0;
9502
+
simm7_out_0 = *valp;
9503
+
simm7_in_0 = (simm7_out_0 & 0x7f);
9504
+
*valp = simm7_in_0;
9499
9505
return 0;
9500
9506
}
9501
9507
9502
9508
static int
9503
-
Operand_uimm6_decode (uint32 *valp)
9509
+
OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
9504
9510
{
9505
-
unsigned uimm6_0, imm6_0;
9506
-
imm6_0 = *valp & 0x3f;
9507
-
uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
9508
-
*valp = uimm6_0;
9511
+
unsigned uimm6_out_0;
9512
+
unsigned uimm6_in_0;
9513
+
uimm6_in_0 = *valp & 0x3f;
9514
+
uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
9515
+
*valp = uimm6_out_0;
9509
9516
return 0;
9510
9517
}
9511
9518
9512
9519
static int
9513
-
Operand_uimm6_encode (uint32 *valp)
9520
+
OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
9514
9521
{
9515
-
unsigned imm6_0, uimm6_0;
9516
-
uimm6_0 = *valp;
9517
-
imm6_0 = (uimm6_0 - 0x4) & 0x3f;
9518
-
*valp = imm6_0;
9522
+
unsigned uimm6_in_0;
9523
+
unsigned uimm6_out_0;
9524
+
uimm6_out_0 = *valp;
9525
+
uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
9526
+
*valp = uimm6_in_0;
9519
9527
return 0;
9520
9528
}
9521
9529
9522
9530
static int
9523
-
Operand_uimm6_ator (uint32 *valp, uint32 pc)
9531
+
OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
9524
9532
{
9525
-
*valp -= pc;
9533
+
unsigned ai4const_out_0;
9534
+
unsigned ai4const_in_0;
9535
+
ai4const_in_0 = *valp & 0xf;
9536
+
ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
9537
+
*valp = ai4const_out_0;
9526
9538
return 0;
9527
9539
}
9528
9540
9529
9541
static int
9530
-
Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
9542
+
OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
9531
9543
{
9532
-
*valp += pc;
9533
-
return 0;
9534
-
}
9535
-
9536
-
static int
9537
-
Operand_ai4const_decode (uint32 *valp)
9538
-
{
9539
-
unsigned ai4const_0, t_0;
9540
-
t_0 = *valp & 0xf;
9541
-
ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
9542
-
*valp = ai4const_0;
9543
-
return 0;
9544
-
}
9545
-
9546
-
static int
9547
-
Operand_ai4const_encode (uint32 *valp)
9548
-
{
9549
-
unsigned t_0, ai4const_0;
9550
-
ai4const_0 = *valp;
9551
-
switch (ai4const_0)
9544
+
unsigned ai4const_in_0;
9545
+
unsigned ai4const_out_0;
9546
+
ai4const_out_0 = *valp;
9547
+
switch (ai4const_out_0)
9552
9548
{
9553
-
case 0xffffffff: t_0 = 0; break;
9554
-
case 0x1: t_0 = 0x1; break;
9555
-
case 0x2: t_0 = 0x2; break;
9556
-
case 0x3: t_0 = 0x3; break;
9557
-
case 0x4: t_0 = 0x4; break;
9558
-
case 0x5: t_0 = 0x5; break;
9559
-
case 0x6: t_0 = 0x6; break;
9560
-
case 0x7: t_0 = 0x7; break;
9561
-
case 0x8: t_0 = 0x8; break;
9562
-
case 0x9: t_0 = 0x9; break;
9563
-
case 0xa: t_0 = 0xa; break;
9564
-
case 0xb: t_0 = 0xb; break;
9565
-
case 0xc: t_0 = 0xc; break;
9566
-
case 0xd: t_0 = 0xd; break;
9567
-
case 0xe: t_0 = 0xe; break;
9568
-
default: t_0 = 0xf; break;
9549
+
case 0xffffffff: ai4const_in_0 = 0; break;
9550
+
case 0x1: ai4const_in_0 = 0x1; break;
9551
+
case 0x2: ai4const_in_0 = 0x2; break;
9552
+
case 0x3: ai4const_in_0 = 0x3; break;
9553
+
case 0x4: ai4const_in_0 = 0x4; break;
9554
+
case 0x5: ai4const_in_0 = 0x5; break;
9555
+
case 0x6: ai4const_in_0 = 0x6; break;
9556
+
case 0x7: ai4const_in_0 = 0x7; break;
9557
+
case 0x8: ai4const_in_0 = 0x8; break;
9558
+
case 0x9: ai4const_in_0 = 0x9; break;
9559
+
case 0xa: ai4const_in_0 = 0xa; break;
9560
+
case 0xb: ai4const_in_0 = 0xb; break;
9561
+
case 0xc: ai4const_in_0 = 0xc; break;
9562
+
case 0xd: ai4const_in_0 = 0xd; break;
9563
+
case 0xe: ai4const_in_0 = 0xe; break;
9564
+
default: ai4const_in_0 = 0xf; break;
9569
9565
}
9570
-
*valp = t_0;
9566
+
*valp = ai4const_in_0;
9571
9567
return 0;
9572
9568
}
9573
9569
9574
9570
static int
9575
-
Operand_b4const_decode (uint32 *valp)
9571
+
OperandSem_opnd_sem_b4const_decode (uint32 *valp)
9576
9572
{
9577
-
unsigned b4const_0, r_0;
9578
-
r_0 = *valp & 0xf;
9579
-
b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
9580
-
*valp = b4const_0;
9573
+
unsigned b4const_out_0;
9574
+
unsigned b4const_in_0;
9575
+
b4const_in_0 = *valp & 0xf;
9576
+
b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
9577
+
*valp = b4const_out_0;
9581
9578
return 0;
9582
9579
}
9583
9580
9584
9581
static int
9585
-
Operand_b4const_encode (uint32 *valp)
9582
+
OperandSem_opnd_sem_b4const_encode (uint32 *valp)
9586
9583
{
9587
-
unsigned r_0, b4const_0;
9588
-
b4const_0 = *valp;
9589
-
switch (b4const_0)
9584
+
unsigned b4const_in_0;
9585
+
unsigned b4const_out_0;
9586
+
b4const_out_0 = *valp;
9587
+
switch (b4const_out_0)
9590
9588
{
9591
-
case 0xffffffff: r_0 = 0; break;
9592
-
case 0x1: r_0 = 0x1; break;
9593
-
case 0x2: r_0 = 0x2; break;
9594
-
case 0x3: r_0 = 0x3; break;
9595
-
case 0x4: r_0 = 0x4; break;
9596
-
case 0x5: r_0 = 0x5; break;
9597
-
case 0x6: r_0 = 0x6; break;
9598
-
case 0x7: r_0 = 0x7; break;
9599
-
case 0x8: r_0 = 0x8; break;
9600
-
case 0xa: r_0 = 0x9; break;
9601
-
case 0xc: r_0 = 0xa; break;
9602
-
case 0x10: r_0 = 0xb; break;
9603
-
case 0x20: r_0 = 0xc; break;
9604
-
case 0x40: r_0 = 0xd; break;
9605
-
case 0x80: r_0 = 0xe; break;
9606
-
default: r_0 = 0xf; break;
9589
+
case 0xffffffff: b4const_in_0 = 0; break;
9590
+
case 0x1: b4const_in_0 = 0x1; break;
9591
+
case 0x2: b4const_in_0 = 0x2; break;
9592
+
case 0x3: b4const_in_0 = 0x3; break;
9593
+
case 0x4: b4const_in_0 = 0x4; break;
9594
+
case 0x5: b4const_in_0 = 0x5; break;
9595
+
case 0x6: b4const_in_0 = 0x6; break;
9596
+
case 0x7: b4const_in_0 = 0x7; break;
9597
+
case 0x8: b4const_in_0 = 0x8; break;
9598
+
case 0xa: b4const_in_0 = 0x9; break;
9599
+
case 0xc: b4const_in_0 = 0xa; break;
9600
+
case 0x10: b4const_in_0 = 0xb; break;
9601
+
case 0x20: b4const_in_0 = 0xc; break;
9602
+
case 0x40: b4const_in_0 = 0xd; break;
9603
+
case 0x80: b4const_in_0 = 0xe; break;
9604
+
default: b4const_in_0 = 0xf; break;
9607
9605
}
9608
-
*valp = r_0;
9606
+
*valp = b4const_in_0;
9609
9607
return 0;
9610
9608
}
9611
9609
9612
9610
static int
9613
-
Operand_b4constu_decode (uint32 *valp)
9611
+
OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
9614
9612
{
9615
-
unsigned b4constu_0, r_0;
9616
-
r_0 = *valp & 0xf;
9617
-
b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
9618
-
*valp = b4constu_0;
9613
+
unsigned b4constu_out_0;
9614
+
unsigned b4constu_in_0;
9615
+
b4constu_in_0 = *valp & 0xf;
9616
+
b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
9617
+
*valp = b4constu_out_0;
9619
9618
return 0;
9620
9619
}
9621
9620
9622
9621
static int
9623
-
Operand_b4constu_encode (uint32 *valp)
9622
+
OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
9624
9623
{
9625
-
unsigned r_0, b4constu_0;
9626
-
b4constu_0 = *valp;
9627
-
switch (b4constu_0)
9624
+
unsigned b4constu_in_0;
9625
+
unsigned b4constu_out_0;
9626
+
b4constu_out_0 = *valp;
9627
+
switch (b4constu_out_0)
9628
9628
{
9629
-
case 0x8000: r_0 = 0; break;
9630
-
case 0x10000: r_0 = 0x1; break;
9631
-
case 0x2: r_0 = 0x2; break;
9632
-
case 0x3: r_0 = 0x3; break;
9633
-
case 0x4: r_0 = 0x4; break;
9634
-
case 0x5: r_0 = 0x5; break;
9635
-
case 0x6: r_0 = 0x6; break;
9636
-
case 0x7: r_0 = 0x7; break;
9637
-
case 0x8: r_0 = 0x8; break;
9638
-
case 0xa: r_0 = 0x9; break;
9639
-
case 0xc: r_0 = 0xa; break;
9640
-
case 0x10: r_0 = 0xb; break;
9641
-
case 0x20: r_0 = 0xc; break;
9642
-
case 0x40: r_0 = 0xd; break;
9643
-
case 0x80: r_0 = 0xe; break;
9644
-
default: r_0 = 0xf; break;
9629
+
case 0x8000: b4constu_in_0 = 0; break;
9630
+
case 0x10000: b4constu_in_0 = 0x1; break;
9631
+
case 0x2: b4constu_in_0 = 0x2; break;
9632
+
case 0x3: b4constu_in_0 = 0x3; break;
9633
+
case 0x4: b4constu_in_0 = 0x4; break;
9634
+
case 0x5: b4constu_in_0 = 0x5; break;
9635
+
case 0x6: b4constu_in_0 = 0x6; break;
9636
+
case 0x7: b4constu_in_0 = 0x7; break;
9637
+
case 0x8: b4constu_in_0 = 0x8; break;
9638
+
case 0xa: b4constu_in_0 = 0x9; break;
9639
+
case 0xc: b4constu_in_0 = 0xa; break;
9640
+
case 0x10: b4constu_in_0 = 0xb; break;
9641
+
case 0x20: b4constu_in_0 = 0xc; break;
9642
+
case 0x40: b4constu_in_0 = 0xd; break;
9643
+
case 0x80: b4constu_in_0 = 0xe; break;
9644
+
default: b4constu_in_0 = 0xf; break;
9645
9645
}
9646
-
*valp = r_0;
9646
+
*valp = b4constu_in_0;
9647
9647
return 0;
9648
9648
}
9649
9649
9650
9650
static int
9651
-
Operand_uimm8_decode (uint32 *valp)
9651
+
OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
9652
9652
{
9653
-
unsigned uimm8_0, imm8_0;
9654
-
imm8_0 = *valp & 0xff;
9655
-
uimm8_0 = imm8_0;
9656
-
*valp = uimm8_0;
9653
+
unsigned uimm8_out_0;
9654
+
unsigned uimm8_in_0;
9655
+
uimm8_in_0 = *valp & 0xff;
9656
+
uimm8_out_0 = uimm8_in_0;
9657
+
*valp = uimm8_out_0;
9657
9658
return 0;
9658
9659
}
9659
9660
9660
9661
static int
9661
-
Operand_uimm8_encode (uint32 *valp)
9662
+
OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
9662
9663
{
9663
-
unsigned imm8_0, uimm8_0;
9664
-
uimm8_0 = *valp;
9665
-
imm8_0 = (uimm8_0 & 0xff);
9666
-
*valp = imm8_0;
9664
+
unsigned uimm8_in_0;
9665
+
unsigned uimm8_out_0;
9666
+
uimm8_out_0 = *valp;
9667
+
uimm8_in_0 = (uimm8_out_0 & 0xff);
9668
+
*valp = uimm8_in_0;
9667
9669
return 0;
9668
9670
}
9669
9671
9670
9672
static int
9671
-
Operand_uimm8x2_decode (uint32 *valp)
9673
+
OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
9672
9674
{
9673
-
unsigned uimm8x2_0, imm8_0;
9674
-
imm8_0 = *valp & 0xff;
9675
-
uimm8x2_0 = imm8_0 << 1;
9676
-
*valp = uimm8x2_0;
9675
+
unsigned uimm8x2_out_0;
9676
+
unsigned uimm8x2_in_0;
9677
+
uimm8x2_in_0 = *valp & 0xff;
9678
+
uimm8x2_out_0 = uimm8x2_in_0 << 1;
9679
+
*valp = uimm8x2_out_0;
9677
9680
return 0;
9678
9681
}
9679
9682
9680
9683
static int
9681
-
Operand_uimm8x2_encode (uint32 *valp)
9684
+
OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
9682
9685
{
9683
-
unsigned imm8_0, uimm8x2_0;
9684
-
uimm8x2_0 = *valp;
9685
-
imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
9686
-
*valp = imm8_0;
9686
+
unsigned uimm8x2_in_0;
9687
+
unsigned uimm8x2_out_0;
9688
+
uimm8x2_out_0 = *valp;
9689
+
uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
9690
+
*valp = uimm8x2_in_0;
9687
9691
return 0;
9688
9692
}
9689
9693
9690
9694
static int
9691
-
Operand_uimm8x4_decode (uint32 *valp)
9695
+
OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
9692
9696
{
9693
-
unsigned uimm8x4_0, imm8_0;
9694
-
imm8_0 = *valp & 0xff;
9695
-
uimm8x4_0 = imm8_0 << 2;
9696
-
*valp = uimm8x4_0;
9697
+
unsigned uimm8x4_out_0;
9698
+
unsigned uimm8x4_in_0;
9699
+
uimm8x4_in_0 = *valp & 0xff;
9700
+
uimm8x4_out_0 = uimm8x4_in_0 << 2;
9701
+
*valp = uimm8x4_out_0;
9697
9702
return 0;
9698
9703
}
9699
9704
9700
9705
static int
9701
-
Operand_uimm8x4_encode (uint32 *valp)
9706
+
OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
9702
9707
{
9703
-
unsigned imm8_0, uimm8x4_0;
9704
-
uimm8x4_0 = *valp;
9705
-
imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
9706
-
*valp = imm8_0;
9708
+
unsigned uimm8x4_in_0;
9709
+
unsigned uimm8x4_out_0;
9710
+
uimm8x4_out_0 = *valp;
9711
+
uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
9712
+
*valp = uimm8x4_in_0;
9707
9713
return 0;
9708
9714
}
9709
9715
9710
9716
static int
9711
-
Operand_uimm4x16_decode (uint32 *valp)
9717
+
OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
9712
9718
{
9713
-
unsigned uimm4x16_0, op2_0;
9714
-
op2_0 = *valp & 0xf;
9715
-
uimm4x16_0 = op2_0 << 4;
9716
-
*valp = uimm4x16_0;
9719
+
unsigned uimm4x16_out_0;
9720
+
unsigned uimm4x16_in_0;
9721
+
uimm4x16_in_0 = *valp & 0xf;
9722
+
uimm4x16_out_0 = uimm4x16_in_0 << 4;
9723
+
*valp = uimm4x16_out_0;
9717
9724
return 0;
9718
9725
}
9719
9726
9720
9727
static int
9721
-
Operand_uimm4x16_encode (uint32 *valp)
9728
+
OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
9722
9729
{
9723
-
unsigned op2_0, uimm4x16_0;
9724
-
uimm4x16_0 = *valp;
9725
-
op2_0 = ((uimm4x16_0 >> 4) & 0xf);
9726
-
*valp = op2_0;
9730
+
unsigned uimm4x16_in_0;
9731
+
unsigned uimm4x16_out_0;
9732
+
uimm4x16_out_0 = *valp;
9733
+
uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
9734
+
*valp = uimm4x16_in_0;
9727
9735
return 0;
9728
9736
}
9729
9737
9730
9738
static int
9731
-
Operand_simm8_decode (uint32 *valp)
9739
+
OperandSem_opnd_sem_simm8_decode (uint32 *valp)
9732
9740
{
9733
-
unsigned simm8_0, imm8_0;
9734
-
imm8_0 = *valp & 0xff;
9735
-
simm8_0 = ((int) imm8_0 << 24) >> 24;
9736
-
*valp = simm8_0;
9741
+
unsigned simm8_out_0;
9742
+
unsigned simm8_in_0;
9743
+
simm8_in_0 = *valp & 0xff;
9744
+
simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
9745
+
*valp = simm8_out_0;
9737
9746
return 0;
9738
9747
}
9739
9748
9740
9749
static int
9741
-
Operand_simm8_encode (uint32 *valp)
9750
+
OperandSem_opnd_sem_simm8_encode (uint32 *valp)
9742
9751
{
9743
-
unsigned imm8_0, simm8_0;
9744
-
simm8_0 = *valp;
9745
-
imm8_0 = (simm8_0 & 0xff);
9746
-
*valp = imm8_0;
9752
+
unsigned simm8_in_0;
9753
+
unsigned simm8_out_0;
9754
+
simm8_out_0 = *valp;
9755
+
simm8_in_0 = (simm8_out_0 & 0xff);
9756
+
*valp = simm8_in_0;
9747
9757
return 0;
9748
9758
}
9749
9759
9750
9760
static int
9751
-
Operand_simm8x256_decode (uint32 *valp)
9761
+
OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
9752
9762
{
9753
-
unsigned simm8x256_0, imm8_0;
9754
-
imm8_0 = *valp & 0xff;
9755
-
simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
9756
-
*valp = simm8x256_0;
9763
+
unsigned simm8x256_out_0;
9764
+
unsigned simm8x256_in_0;
9765
+
simm8x256_in_0 = *valp & 0xff;
9766
+
simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
9767
+
*valp = simm8x256_out_0;
9757
9768
return 0;
9758
9769
}
9759
9770
9760
9771
static int
9761
-
Operand_simm8x256_encode (uint32 *valp)
9772
+
OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
9762
9773
{
9763
-
unsigned imm8_0, simm8x256_0;
9764
-
simm8x256_0 = *valp;
9765
-
imm8_0 = ((simm8x256_0 >> 8) & 0xff);
9766
-
*valp = imm8_0;
9774
+
unsigned simm8x256_in_0;
9775
+
unsigned simm8x256_out_0;
9776
+
simm8x256_out_0 = *valp;
9777
+
simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
9778
+
*valp = simm8x256_in_0;
9767
9779
return 0;
9768
9780
}
9769
9781
9770
9782
static int
9771
-
Operand_simm12b_decode (uint32 *valp)
9783
+
OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
9772
9784
{
9773
-
unsigned simm12b_0, imm12b_0;
9774
-
imm12b_0 = *valp & 0xfff;
9775
-
simm12b_0 = ((int) imm12b_0 << 20) >> 20;
9776
-
*valp = simm12b_0;
9785
+
unsigned simm12b_out_0;
9786
+
unsigned simm12b_in_0;
9787
+
simm12b_in_0 = *valp & 0xfff;
9788
+
simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
9789
+
*valp = simm12b_out_0;
9777
9790
return 0;
9778
9791
}
9779
9792
9780
9793
static int
9781
-
Operand_simm12b_encode (uint32 *valp)
9794
+
OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
9782
9795
{
9783
-
unsigned imm12b_0, simm12b_0;
9784
-
simm12b_0 = *valp;
9785
-
imm12b_0 = (simm12b_0 & 0xfff);
9786
-
*valp = imm12b_0;
9796
+
unsigned simm12b_in_0;
9797
+
unsigned simm12b_out_0;
9798
+
simm12b_out_0 = *valp;
9799
+
simm12b_in_0 = (simm12b_out_0 & 0xfff);
9800
+
*valp = simm12b_in_0;
9787
9801
return 0;
9788
9802
}
9789
9803
9790
9804
static int
9791
-
Operand_msalp32_decode (uint32 *valp)
9805
+
OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
9792
9806
{
9793
-
unsigned msalp32_0, sal_0;
9794
-
sal_0 = *valp & 0x1f;
9795
-
msalp32_0 = 0x20 - sal_0;
9796
-
*valp = msalp32_0;
9807
+
unsigned msalp32_out_0;
9808
+
unsigned msalp32_in_0;
9809
+
msalp32_in_0 = *valp & 0x1f;
9810
+
msalp32_out_0 = 0x20 - msalp32_in_0;
9811
+
*valp = msalp32_out_0;
9797
9812
return 0;
9798
9813
}
9799
9814
9800
9815
static int
9801
-
Operand_msalp32_encode (uint32 *valp)
9816
+
OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
9802
9817
{
9803
-
unsigned sal_0, msalp32_0;
9804
-
msalp32_0 = *valp;
9805
-
sal_0 = (0x20 - msalp32_0) & 0x1f;
9806
-
*valp = sal_0;
9818
+
unsigned msalp32_in_0;
9819
+
unsigned msalp32_out_0;
9820
+
msalp32_out_0 = *valp;
9821
+
msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
9822
+
*valp = msalp32_in_0;
9807
9823
return 0;
9808
9824
}
9809
9825
9810
9826
static int
9811
-
Operand_op2p1_decode (uint32 *valp)
9827
+
OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
9812
9828
{
9813
-
unsigned op2p1_0, op2_0;
9814
-
op2_0 = *valp & 0xf;
9815
-
op2p1_0 = op2_0 + 0x1;
9816
-
*valp = op2p1_0;
9829
+
unsigned op2p1_out_0;
9830
+
unsigned op2p1_in_0;
9831
+
op2p1_in_0 = *valp & 0xf;
9832
+
op2p1_out_0 = op2p1_in_0 + 0x1;
9833
+
*valp = op2p1_out_0;
9817
9834
return 0;
9818
9835
}
9819
9836
9820
9837
static int
9821
-
Operand_op2p1_encode (uint32 *valp)
9838
+
OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
9822
9839
{
9823
-
unsigned op2_0, op2p1_0;
9824
-
op2p1_0 = *valp;
9825
-
op2_0 = (op2p1_0 - 0x1) & 0xf;
9826
-
*valp = op2_0;
9840
+
unsigned op2p1_in_0;
9841
+
unsigned op2p1_out_0;
9842
+
op2p1_out_0 = *valp;
9843
+
op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
9844
+
*valp = op2p1_in_0;
9827
9845
return 0;
9828
9846
}
9829
9847
9830
9848
static int
9831
-
Operand_label8_decode (uint32 *valp)
9849
+
OperandSem_opnd_sem_label8_decode (uint32 *valp)
9832
9850
{
9833
-
unsigned label8_0, imm8_0;
9834
-
imm8_0 = *valp & 0xff;
9835
-
label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
9836
-
*valp = label8_0;
9851
+
unsigned label8_out_0;
9852
+
unsigned label8_in_0;
9853
+
label8_in_0 = *valp & 0xff;
9854
+
label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
9855
+
*valp = label8_out_0;
9837
9856
return 0;
9838
9857
}
9839
9858
9840
9859
static int
9841
-
Operand_label8_encode (uint32 *valp)
9860
+
OperandSem_opnd_sem_label8_encode (uint32 *valp)
9842
9861
{
9843
-
unsigned imm8_0, label8_0;
9844
-
label8_0 = *valp;
9845
-
imm8_0 = (label8_0 - 0x4) & 0xff;
9846
-
*valp = imm8_0;
9862
+
unsigned label8_in_0;
9863
+
unsigned label8_out_0;
9864
+
label8_out_0 = *valp;
9865
+
label8_in_0 = (label8_out_0 - 0x4) & 0xff;
9866
+
*valp = label8_in_0;
9847
9867
return 0;
9848
9868
}
9849
9869
9850
9870
static int
9851
-
Operand_label8_ator (uint32 *valp, uint32 pc)
9871
+
OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
9852
9872
{
9853
-
*valp -= pc;
9873
+
unsigned ulabel8_out_0;
9874
+
unsigned ulabel8_in_0;
9875
+
ulabel8_in_0 = *valp & 0xff;
9876
+
ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
9877
+
*valp = ulabel8_out_0;
9854
9878
return 0;
9855
9879
}
9856
9880
9857
9881
static int
9858
-
Operand_label8_rtoa (uint32 *valp, uint32 pc)
9882
+
OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
9859
9883
{
9860
-
*valp += pc;
9884
+
unsigned ulabel8_in_0;
9885
+
unsigned ulabel8_out_0;
9886
+
ulabel8_out_0 = *valp;
9887
+
ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
9888
+
*valp = ulabel8_in_0;
9861
9889
return 0;
9862
9890
}
9863
9891
9864
9892
static int
9865
-
Operand_ulabel8_decode (uint32 *valp)
9893
+
OperandSem_opnd_sem_label12_decode (uint32 *valp)
9866
9894
{
9867
-
unsigned ulabel8_0, imm8_0;
9868
-
imm8_0 = *valp & 0xff;
9869
-
ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
9870
-
*valp = ulabel8_0;
9895
+
unsigned label12_out_0;
9896
+
unsigned label12_in_0;
9897
+
label12_in_0 = *valp & 0xfff;
9898
+
label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
9899
+
*valp = label12_out_0;
9871
9900
return 0;
9872
9901
}
9873
9902
9874
9903
static int
9875
-
Operand_ulabel8_encode (uint32 *valp)
9904
+
OperandSem_opnd_sem_label12_encode (uint32 *valp)
9876
9905
{
9877
-
unsigned imm8_0, ulabel8_0;
9878
-
ulabel8_0 = *valp;
9879
-
imm8_0 = (ulabel8_0 - 0x4) & 0xff;
9880
-
*valp = imm8_0;
9906
+
unsigned label12_in_0;
9907
+
unsigned label12_out_0;
9908
+
label12_out_0 = *valp;
9909
+
label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
9910
+
*valp = label12_in_0;
9881
9911
return 0;
9882
9912
}
9883
9913
9884
9914
static int
9885
-
Operand_ulabel8_ator (uint32 *valp, uint32 pc)
9915
+
OperandSem_opnd_sem_soffset_decode (uint32 *valp)
9886
9916
{
9887
-
*valp -= pc;
9917
+
unsigned soffset_out_0;
9918
+
unsigned soffset_in_0;
9919
+
soffset_in_0 = *valp & 0x3ffff;
9920
+
soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
9921
+
*valp = soffset_out_0;
9888
9922
return 0;
9889
9923
}
9890
9924
9891
9925
static int
9892
-
Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
9926
+
OperandSem_opnd_sem_soffset_encode (uint32 *valp)
9893
9927
{
9894
-
*valp += pc;
9928
+
unsigned soffset_in_0;
9929
+
unsigned soffset_out_0;
9930
+
soffset_out_0 = *valp;
9931
+
soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
9932
+
*valp = soffset_in_0;
9895
9933
return 0;
9896
9934
}
9897
9935
9898
9936
static int
9899
-
Operand_label12_decode (uint32 *valp)
9937
+
OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
9900
9938
{
9901
-
unsigned label12_0, imm12_0;
9902
-
imm12_0 = *valp & 0xfff;
9903
-
label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
9904
-
*valp = label12_0;
9939
+
unsigned uimm16x4_out_0;
9940
+
unsigned uimm16x4_in_0;
9941
+
uimm16x4_in_0 = *valp & 0xffff;
9942
+
uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
9943
+
*valp = uimm16x4_out_0;
9905
9944
return 0;
9906
9945
}
9907
9946
9908
9947
static int
9909
-
Operand_label12_encode (uint32 *valp)
9948
+
OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
9910
9949
{
9911
-
unsigned imm12_0, label12_0;
9912
-
label12_0 = *valp;
9913
-
imm12_0 = (label12_0 - 0x4) & 0xfff;
9914
-
*valp = imm12_0;
9950
+
unsigned uimm16x4_in_0;
9951
+
unsigned uimm16x4_out_0;
9952
+
uimm16x4_out_0 = *valp;
9953
+
uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
9954
+
*valp = uimm16x4_in_0;
9915
9955
return 0;
9916
9956
}
9917
9957
9918
9958
static int
9919
-
Operand_label12_ator (uint32 *valp, uint32 pc)
9959
+
OperandSem_opnd_sem_bbi_decode (uint32 *valp)
9920
9960
{
9921
-
*valp -= pc;
9961
+
unsigned bbi_out_0;
9962
+
unsigned bbi_in_0;
9963
+
bbi_in_0 = *valp & 0x1f;
9964
+
bbi_out_0 = (0 << 5) | bbi_in_0;
9965
+
*valp = bbi_out_0;
9922
9966
return 0;
9923
9967
}
9924
9968
9925
9969
static int
9926
-
Operand_label12_rtoa (uint32 *valp, uint32 pc)
9970
+
OperandSem_opnd_sem_bbi_encode (uint32 *valp)
9927
9971
{
9928
-
*valp += pc;
9972
+
unsigned bbi_in_0;
9973
+
unsigned bbi_out_0;
9974
+
bbi_out_0 = *valp;
9975
+
bbi_in_0 = (bbi_out_0 & 0x1f);
9976
+
*valp = bbi_in_0;
9929
9977
return 0;
9930
9978
}
9931
9979
9932
9980
static int
9933
-
Operand_soffset_decode (uint32 *valp)
9981
+
OperandSem_opnd_sem_s_decode (uint32 *valp)
9934
9982
{
9935
-
unsigned soffset_0, offset_0;
9936
-
offset_0 = *valp & 0x3ffff;
9937
-
soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
9938
-
*valp = soffset_0;
9983
+
unsigned s_out_0;
9984
+
unsigned s_in_0;
9985
+
s_in_0 = *valp & 0xf;
9986
+
s_out_0 = (0 << 4) | s_in_0;
9987
+
*valp = s_out_0;
9939
9988
return 0;
9940
9989
}
9941
9990
9942
9991
static int
9943
-
Operand_soffset_encode (uint32 *valp)
9992
+
OperandSem_opnd_sem_s_encode (uint32 *valp)
9944
9993
{
9945
-
unsigned offset_0, soffset_0;
9946
-
soffset_0 = *valp;
9947
-
offset_0 = (soffset_0 - 0x4) & 0x3ffff;
9948
-
*valp = offset_0;
9994
+
unsigned s_in_0;
9995
+
unsigned s_out_0;
9996
+
s_out_0 = *valp;
9997
+
s_in_0 = (s_out_0 & 0xf);
9998
+
*valp = s_in_0;
9949
9999
return 0;
9950
10000
}
9951
10001
9952
10002
static int
9953
-
Operand_soffset_ator (uint32 *valp, uint32 pc)
10003
+
OperandSem_opnd_sem_immt_decode (uint32 *valp)
9954
10004
{
9955
-
*valp -= pc;
10005
+
unsigned immt_out_0;
10006
+
unsigned immt_in_0;
10007
+
immt_in_0 = *valp & 0xf;
10008
+
immt_out_0 = immt_in_0;
10009
+
*valp = immt_out_0;
9956
10010
return 0;
9957
10011
}
9958
10012
9959
10013
static int
9960
-
Operand_soffset_rtoa (uint32 *valp, uint32 pc)
10014
+
OperandSem_opnd_sem_immt_encode (uint32 *valp)
9961
10015
{
9962
-
*valp += pc;
9963
-
return 0;
9964
-
}
9965
-
9966
-
static int
9967
-
Operand_uimm16x4_decode (uint32 *valp)
9968
-
{
9969
-
unsigned uimm16x4_0, imm16_0;
9970
-
imm16_0 = *valp & 0xffff;
9971
-
uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
9972
-
*valp = uimm16x4_0;
10016
+
unsigned immt_in_0;
10017
+
unsigned immt_out_0;
10018
+
immt_out_0 = *valp;
10019
+
immt_in_0 = immt_out_0 & 0xf;
10020
+
*valp = immt_in_0;
9973
10021
return 0;
9974
10022
}
9975
10023
9976
10024
static int
9977
-
Operand_uimm16x4_encode (uint32 *valp)
10025
+
OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
9978
10026
{
9979
-
unsigned imm16_0, uimm16x4_0;
9980
-
uimm16x4_0 = *valp;
9981
-
imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
9982
-
*valp = imm16_0;
9983
10027
return 0;
9984
10028
}
9985
10029
9986
10030
static int
9987
-
Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
9988
-
{
9989
-
*valp -= ((pc + 3) & ~0x3);
9990
-
return 0;
9991
-
}
9992
-
9993
-
static int
9994
-
Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
9995
-
{
9996
-
*valp += ((pc + 3) & ~0x3);
9997
-
return 0;
9998
-
}
9999
-
10000
-
static int
10001
-
Operand_immt_decode (uint32 *valp)
10002
-
{
10003
-
unsigned immt_0, t_0;
10004
-
t_0 = *valp & 0xf;
10005
-
immt_0 = t_0;
10006
-
*valp = immt_0;
10007
-
return 0;
10008
-
}
10009
-
10010
-
static int
10011
-
Operand_immt_encode (uint32 *valp)
10012
-
{
10013
-
unsigned t_0, immt_0;
10014
-
immt_0 = *valp;
10015
-
t_0 = immt_0 & 0xf;
10016
-
*valp = t_0;
10017
-
return 0;
10018
-
}
10019
-
10020
-
static int
10021
-
Operand_imms_decode (uint32 *valp)
10022
-
{
10023
-
unsigned imms_0, s_0;
10024
-
s_0 = *valp & 0xf;
10025
-
imms_0 = s_0;
10026
-
*valp = imms_0;
10027
-
return 0;
10028
-
}
10029
-
10030
-
static int
10031
-
Operand_imms_encode (uint32 *valp)
10032
-
{
10033
-
unsigned s_0, imms_0;
10034
-
imms_0 = *valp;
10035
-
s_0 = imms_0 & 0xf;
10036
-
*valp = s_0;
10037
-
return 0;
10038
-
}
10039
-
10040
-
static int
10041
-
Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
10042
-
{
10043
-
return 0;
10044
-
}
10045
-
10046
-
static int
10047
-
Operand_bt_encode (uint32 *valp)
10031
+
OperandSem_opnd_sem_BR_encode (uint32 *valp)
10048
10032
{
10049
10033
int error;
10050
-
error = (*valp & ~0xf) != 0;
10034
+
error = (*valp >= 16);
10051
10035
return error;
10052
10036
}
10053
10037
10054
10038
static int
10055
-
Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
10056
-
{
10057
-
return 0;
10058
-
}
10059
-
10060
-
static int
10061
-
Operand_bs_encode (uint32 *valp)
10062
-
{
10063
-
int error;
10064
-
error = (*valp & ~0xf) != 0;
10065
-
return error;
10066
-
}
10067
-
10068
-
static int
10069
-
Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
10070
-
{
10071
-
return 0;
10072
-
}
10073
-
10074
-
static int
10075
-
Operand_br_encode (uint32 *valp)
10076
-
{
10077
-
int error;
10078
-
error = (*valp & ~0xf) != 0;
10079
-
return error;
10080
-
}
10081
-
10082
-
static int
10083
-
Operand_bt2_decode (uint32 *valp)
10039
+
OperandSem_opnd_sem_BR2_decode (uint32 *valp)
10084
10040
{
10085
10041
*valp = *valp << 1;
10086
10042
return 0;
10087
10043
}
10088
10044
10089
10045
static int
10090
-
Operand_bt2_encode (uint32 *valp)
10046
+
OperandSem_opnd_sem_BR2_encode (uint32 *valp)
10091
10047
{
10092
10048
int error;
10093
-
error = (*valp & ~(0x7 << 1)) != 0;
10049
+
error = (*valp >= 16) || ((*valp & 1) != 0);
10094
10050
*valp = *valp >> 1;
10095
10051
return error;
10096
10052
}
10097
10053
10098
10054
static int
10099
-
Operand_bs2_decode (uint32 *valp)
10100
-
{
10101
-
*valp = *valp << 1;
10102
-
return 0;
10103
-
}
10104
-
10105
-
static int
10106
-
Operand_bs2_encode (uint32 *valp)
10107
-
{
10108
-
int error;
10109
-
error = (*valp & ~(0x7 << 1)) != 0;
10110
-
*valp = *valp >> 1;
10111
-
return error;
10112
-
}
10113
-
10114
-
static int
10115
-
Operand_br2_decode (uint32 *valp)
10116
-
{
10117
-
*valp = *valp << 1;
10118
-
return 0;
10119
-
}
10120
-
10121
-
static int
10122
-
Operand_br2_encode (uint32 *valp)
10123
-
{
10124
-
int error;
10125
-
error = (*valp & ~(0x7 << 1)) != 0;
10126
-
*valp = *valp >> 1;
10127
-
return error;
10128
-
}
10129
-
10130
-
static int
10131
-
Operand_bt4_decode (uint32 *valp)
10132
-
{
10133
-
*valp = *valp << 2;
10134
-
return 0;
10135
-
}
10136
-
10137
-
static int
10138
-
Operand_bt4_encode (uint32 *valp)
10139
-
{
10140
-
int error;
10141
-
error = (*valp & ~(0x3 << 2)) != 0;
10142
-
*valp = *valp >> 2;
10143
-
return error;
10144
-
}
10145
-
10146
-
static int
10147
-
Operand_bs4_decode (uint32 *valp)
10055
+
OperandSem_opnd_sem_BR4_decode (uint32 *valp)
10148
10056
{
10149
10057
*valp = *valp << 2;
10150
10058
return 0;
10151
10059
}
10152
10060
10153
10061
static int
10154
-
Operand_bs4_encode (uint32 *valp)
10062
+
OperandSem_opnd_sem_BR4_encode (uint32 *valp)
10155
10063
{
10156
10064
int error;
10157
-
error = (*valp & ~(0x3 << 2)) != 0;
10065
+
error = (*valp >= 16) || ((*valp & 3) != 0);
10158
10066
*valp = *valp >> 2;
10159
10067
return error;
10160
10068
}
10161
10069
10162
10070
static int
10163
-
Operand_br4_decode (uint32 *valp)
10164
-
{
10165
-
*valp = *valp << 2;
10166
-
return 0;
10167
-
}
10168
-
10169
-
static int
10170
-
Operand_br4_encode (uint32 *valp)
10171
-
{
10172
-
int error;
10173
-
error = (*valp & ~(0x3 << 2)) != 0;
10174
-
*valp = *valp >> 2;
10175
-
return error;
10176
-
}
10177
-
10178
-
static int
10179
-
Operand_bt8_decode (uint32 *valp)
10071
+
OperandSem_opnd_sem_BR8_decode (uint32 *valp)
10180
10072
{
10181
10073
*valp = *valp << 3;
10182
10074
return 0;
10183
10075
}
10184
10076
10185
10077
static int
10186
-
Operand_bt8_encode (uint32 *valp)
10078
+
OperandSem_opnd_sem_BR8_encode (uint32 *valp)
10187
10079
{
10188
10080
int error;
10189
-
error = (*valp & ~(0x1 << 3)) != 0;
10081
+
error = (*valp >= 16) || ((*valp & 7) != 0);
10190
10082
*valp = *valp >> 3;
10191
10083
return error;
10192
10084
}
10193
10085
10194
10086
static int
10195
-
Operand_bs8_decode (uint32 *valp)
10087
+
OperandSem_opnd_sem_BR16_decode (uint32 *valp)
10196
10088
{
10197
-
*valp = *valp << 3;
10089
+
*valp = *valp << 4;
10198
10090
return 0;
10199
10091
}
10200
10092
10201
10093
static int
10202
-
Operand_bs8_encode (uint32 *valp)
10094
+
OperandSem_opnd_sem_BR16_encode (uint32 *valp)
10203
10095
{
10204
10096
int error;
10205
-
error = (*valp & ~(0x1 << 3)) != 0;
10206
-
*valp = *valp >> 3;
10097
+
error = (*valp >= 16) || ((*valp & 15) != 0);
10098
+
*valp = *valp >> 4;
10207
10099
return error;
10208
10100
}
10209
10101
10210
10102
static int
10211
-
Operand_br8_decode (uint32 *valp)
10103
+
OperandSem_opnd_sem_tp7_decode (uint32 *valp)
10212
10104
{
10213
-
*valp = *valp << 3;
10105
+
unsigned tp7_out_0;
10106
+
unsigned tp7_in_0;
10107
+
tp7_in_0 = *valp & 0xf;
10108
+
tp7_out_0 = tp7_in_0 + 0x7;
10109
+
*valp = tp7_out_0;
10214
10110
return 0;
10215
10111
}
10216
10112
10217
10113
static int
10218
-
Operand_br8_encode (uint32 *valp)
10114
+
OperandSem_opnd_sem_tp7_encode (uint32 *valp)
10219
10115
{
10220
-
int error;
10221
-
error = (*valp & ~(0x1 << 3)) != 0;
10222
-
*valp = *valp >> 3;
10223
-
return error;
10116
+
unsigned tp7_in_0;
10117
+
unsigned tp7_out_0;
10118
+
tp7_out_0 = *valp;
10119
+
tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
10120
+
*valp = tp7_in_0;
10121
+
return 0;
10224
10122
}
10225
10123
10226
10124
static int
10227
-
Operand_bt16_decode (uint32 *valp)
10125
+
OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
10228
10126
{
10229
-
*valp = *valp << 4;
10127
+
unsigned xt_wbr15_label_out_0;
10128
+
unsigned xt_wbr15_label_in_0;
10129
+
xt_wbr15_label_in_0 = *valp & 0x7fff;
10130
+
xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
10131
+
*valp = xt_wbr15_label_out_0;
10230
10132
return 0;
10231
10133
}
10232
10134
10233
10135
static int
10234
-
Operand_bt16_encode (uint32 *valp)
10136
+
OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
10235
10137
{
10236
-
int error;
10237
-
error = (*valp & ~(0 << 4)) != 0;
10238
-
*valp = *valp >> 4;
10239
-
return error;
10138
+
unsigned xt_wbr15_label_in_0;
10139
+
unsigned xt_wbr15_label_out_0;
10140
+
xt_wbr15_label_out_0 = *valp;
10141
+
xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
10142
+
*valp = xt_wbr15_label_in_0;
10143
+
return 0;
10240
10144
}
10241
10145
10242
10146
static int
10243
-
Operand_bs16_decode (uint32 *valp)
10147
+
OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
10244
10148
{
10245
-
*valp = *valp << 4;
10149
+
unsigned ae_samt32_out_0;
10150
+
unsigned ae_samt32_in_0;
10151
+
ae_samt32_in_0 = *valp & 0x1f;
10152
+
ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
10153
+
*valp = ae_samt32_out_0;
10246
10154
return 0;
10247
10155
}
10248
10156
10249
10157
static int
10250
-
Operand_bs16_encode (uint32 *valp)
10158
+
OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
10251
10159
{
10252
-
int error;
10253
-
error = (*valp & ~(0 << 4)) != 0;
10254
-
*valp = *valp >> 4;
10255
-
return error;
10160
+
unsigned ae_samt32_in_0;
10161
+
unsigned ae_samt32_out_0;
10162
+
ae_samt32_out_0 = *valp;
10163
+
ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
10164
+
*valp = ae_samt32_in_0;
10165
+
return 0;
10256
10166
}
10257
10167
10258
10168
static int
10259
-
Operand_br16_decode (uint32 *valp)
10169
+
OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10260
10170
{
10261
-
*valp = *valp << 4;
10262
10171
return 0;
10263
10172
}
10264
10173
10265
10174
static int
10266
-
Operand_br16_encode (uint32 *valp)
10175
+
OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
10267
10176
{
10268
10177
int error;
10269
-
error = (*valp & ~(0 << 4)) != 0;
10270
-
*valp = *valp >> 4;
10178
+
error = (*valp >= 8);
10271
10179
return error;
10272
10180
}
10273
10181
10274
10182
static int
10275
-
Operand_brall_decode (uint32 *valp)
10183
+
OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
10276
10184
{
10277
-
*valp = *valp << 4;
10278
10185
return 0;
10279
10186
}
10280
10187
10281
10188
static int
10282
-
Operand_brall_encode (uint32 *valp)
10189
+
OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
10283
10190
{
10284
10191
int error;
10285
-
error = (*valp & ~(0 << 4)) != 0;
10286
-
*valp = *valp >> 4;
10192
+
error = (*valp >= 4);
10287
10193
return error;
10288
10194
}
10289
10195
10290
10196
static int
10291
-
Operand_tp7_decode (uint32 *valp)
10197
+
OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
10292
10198
{
10293
-
unsigned tp7_0, t_0;
10294
-
t_0 = *valp & 0xf;
10295
-
tp7_0 = t_0 + 0x7;
10296
-
*valp = tp7_0;
10199
+
unsigned ae_lsimm16_out_0;
10200
+
unsigned ae_lsimm16_in_0;
10201
+
ae_lsimm16_in_0 = *valp & 0xf;
10202
+
ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
10203
+
*valp = ae_lsimm16_out_0;
10297
10204
return 0;
10298
10205
}
10299
10206
10300
10207
static int
10301
-
Operand_tp7_encode (uint32 *valp)
10208
+
OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
10302
10209
{
10303
-
unsigned t_0, tp7_0;
10304
-
tp7_0 = *valp;
10305
-
t_0 = (tp7_0 - 0x7) & 0xf;
10306
-
*valp = t_0;
10210
+
unsigned ae_lsimm16_in_0;
10211
+
unsigned ae_lsimm16_out_0;
10212
+
ae_lsimm16_out_0 = *valp;
10213
+
ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
10214
+
*valp = ae_lsimm16_in_0;
10307
10215
return 0;
10308
10216
}
10309
10217
10310
10218
static int
10311
-
Operand_xt_wbr15_label_decode (uint32 *valp)
10219
+
OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
10312
10220
{
10313
-
unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
10314
-
xt_wbr15_imm_0 = *valp & 0x7fff;
10315
-
xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
10316
-
*valp = xt_wbr15_label_0;
10221
+
unsigned ae_lsimm32_out_0;
10222
+
unsigned ae_lsimm32_in_0;
10223
+
ae_lsimm32_in_0 = *valp & 0xf;
10224
+
ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
10225
+
*valp = ae_lsimm32_out_0;
10317
10226
return 0;
10318
10227
}
10319
10228
10320
10229
static int
10321
-
Operand_xt_wbr15_label_encode (uint32 *valp)
10230
+
OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
10322
10231
{
10323
-
unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
10324
-
xt_wbr15_label_0 = *valp;
10325
-
xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
10326
-
*valp = xt_wbr15_imm_0;
10232
+
unsigned ae_lsimm32_in_0;
10233
+
unsigned ae_lsimm32_out_0;
10234
+
ae_lsimm32_out_0 = *valp;
10235
+
ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
10236
+
*valp = ae_lsimm32_in_0;
10327
10237
return 0;
10328
10238
}
10329
10239
10330
10240
static int
10331
-
Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
10241
+
OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
10332
10242
{
10333
-
*valp -= pc;
10243
+
unsigned ae_lsimm64_out_0;
10244
+
unsigned ae_lsimm64_in_0;
10245
+
ae_lsimm64_in_0 = *valp & 0xf;
10246
+
ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
10247
+
*valp = ae_lsimm64_out_0;
10334
10248
return 0;
10335
10249
}
10336
10250
10337
10251
static int
10338
-
Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
10252
+
OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
10339
10253
{
10340
-
*valp += pc;
10254
+
unsigned ae_lsimm64_in_0;
10255
+
unsigned ae_lsimm64_out_0;
10256
+
ae_lsimm64_out_0 = *valp;
10257
+
ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
10258
+
*valp = ae_lsimm64_in_0;
10341
10259
return 0;
10342
10260
}
10343
10261
10344
10262
static int
10345
-
Operand_xt_wbr18_label_decode (uint32 *valp)
10263
+
OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
10346
10264
{
10347
-
unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
10348
-
xt_wbr18_imm_0 = *valp & 0x3ffff;
10349
-
xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
10350
-
*valp = xt_wbr18_label_0;
10265
+
unsigned ae_samt64_out_0;
10266
+
unsigned ae_samt64_in_0;
10267
+
ae_samt64_in_0 = *valp & 0x3f;
10268
+
ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
10269
+
*valp = ae_samt64_out_0;
10351
10270
return 0;
10352
10271
}
10353
10272
10354
10273
static int
10355
-
Operand_xt_wbr18_label_encode (uint32 *valp)
10274
+
OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
10356
10275
{
10357
-
unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
10358
-
xt_wbr18_label_0 = *valp;
10359
-
xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
10360
-
*valp = xt_wbr18_imm_0;
10276
+
unsigned ae_samt64_in_0;
10277
+
unsigned ae_samt64_out_0;
10278
+
ae_samt64_out_0 = *valp;
10279
+
ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
10280
+
*valp = ae_samt64_in_0;
10361
10281
return 0;
10362
10282
}
10363
10283
10364
10284
static int
10365
-
Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
10285
+
OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
10366
10286
{
10367
-
*valp -= pc;
10287
+
unsigned ae_ohba_out_0;
10288
+
unsigned ae_ohba_in_0;
10289
+
ae_ohba_in_0 = *valp & 0xf;
10290
+
ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
10291
+
*valp = ae_ohba_out_0;
10368
10292
return 0;
10369
10293
}
10370
10294
10371
10295
static int
10372
-
Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
10296
+
OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
10373
10297
{
10374
-
*valp += pc;
10298
+
unsigned ae_ohba_in_0;
10299
+
unsigned ae_ohba_out_0;
10300
+
ae_ohba_out_0 = *valp;
10301
+
ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
10302
+
*valp = ae_ohba_in_0;
10375
10303
return 0;
10376
10304
}
10377
10305
10378
10306
static int
10379
-
Operand_ae_samt32_decode (uint32 *valp)
10307
+
Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
10380
10308
{
10381
-
unsigned ae_samt32_0, ftsf14_0;
10382
-
ftsf14_0 = *valp & 0x1f;
10383
-
ae_samt32_0 = (0 << 5) | ftsf14_0;
10384
-
*valp = ae_samt32_0;
10309
+
*valp -= (pc & ~0x3);
10385
10310
return 0;
10386
10311
}
10387
10312
10388
10313
static int
10389
-
Operand_ae_samt32_encode (uint32 *valp)
10314
+
Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
10390
10315
{
10391
-
unsigned ftsf14_0, ae_samt32_0;
10392
-
ae_samt32_0 = *valp;
10393
-
ftsf14_0 = (ae_samt32_0 & 0x1f);
10394
-
*valp = ftsf14_0;
10316
+
*valp += (pc & ~0x3);
10395
10317
return 0;
10396
10318
}
10397
10319
10398
10320
static int
10399
-
Operand_pr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
10321
+
Operand_uimm6_ator (uint32 *valp, uint32 pc)
10400
10322
{
10323
+
*valp -= pc;
10401
10324
return 0;
10402
10325
}
10403
10326
10404
10327
static int
10405
-
Operand_pr0_encode (uint32 *valp)
10328
+
Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
10406
10329
{
10407
-
int error;
10408
-
error = (*valp & ~0x7) != 0;
10409
-
return error;
10410
-
}
10411
-
10412
-
static int
10413
-
Operand_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
10414
-
{
10330
+
*valp += pc;
10415
10331
return 0;
10416
10332
}
10417
10333
10418
10334
static int
10419
-
Operand_qr0_encode (uint32 *valp)
10335
+
Operand_label8_ator (uint32 *valp, uint32 pc)
10420
10336
{
10421
-
int error;
10422
-
error = (*valp & ~0x3) != 0;
10423
-
return error;
10424
-
}
10425
-
10426
-
static int
10427
-
Operand_ae_lsimm16_decode (uint32 *valp)
10428
-
{
10429
-
unsigned ae_lsimm16_0, t_0;
10430
-
t_0 = *valp & 0xf;
10431
-
ae_lsimm16_0 = (((int) t_0 << 28) >> 28) << 1;
10432
-
*valp = ae_lsimm16_0;
10337
+
*valp -= pc;
10433
10338
return 0;
10434
10339
}
10435
10340
10436
10341
static int
10437
-
Operand_ae_lsimm16_encode (uint32 *valp)
10342
+
Operand_label8_rtoa (uint32 *valp, uint32 pc)
10438
10343
{
10439
-
unsigned t_0, ae_lsimm16_0;
10440
-
ae_lsimm16_0 = *valp;
10441
-
t_0 = ((ae_lsimm16_0 >> 1) & 0xf);
10442
-
*valp = t_0;
10344
+
*valp += pc;
10443
10345
return 0;
10444
10346
}
10445
10347
10446
10348
static int
10447
-
Operand_ae_lsimm32_decode (uint32 *valp)
10349
+
Operand_ulabel8_ator (uint32 *valp, uint32 pc)
10448
10350
{
10449
-
unsigned ae_lsimm32_0, t_0;
10450
-
t_0 = *valp & 0xf;
10451
-
ae_lsimm32_0 = (((int) t_0 << 28) >> 28) << 2;
10452
-
*valp = ae_lsimm32_0;
10351
+
*valp -= pc;
10453
10352
return 0;
10454
10353
}
10455
10354
10456
10355
static int
10457
-
Operand_ae_lsimm32_encode (uint32 *valp)
10356
+
Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
10458
10357
{
10459
-
unsigned t_0, ae_lsimm32_0;
10460
-
ae_lsimm32_0 = *valp;
10461
-
t_0 = ((ae_lsimm32_0 >> 2) & 0xf);
10462
-
*valp = t_0;
10358
+
*valp += pc;
10463
10359
return 0;
10464
10360
}
10465
10361
10466
10362
static int
10467
-
Operand_ae_lsimm64_decode (uint32 *valp)
10363
+
Operand_label12_ator (uint32 *valp, uint32 pc)
10468
10364
{
10469
-
unsigned ae_lsimm64_0, t_0;
10470
-
t_0 = *valp & 0xf;
10471
-
ae_lsimm64_0 = (((int) t_0 << 28) >> 28) << 3;
10472
-
*valp = ae_lsimm64_0;
10365
+
*valp -= pc;
10473
10366
return 0;
10474
10367
}
10475
10368
10476
10369
static int
10477
-
Operand_ae_lsimm64_encode (uint32 *valp)
10370
+
Operand_label12_rtoa (uint32 *valp, uint32 pc)
10478
10371
{
10479
-
unsigned t_0, ae_lsimm64_0;
10480
-
ae_lsimm64_0 = *valp;
10481
-
t_0 = ((ae_lsimm64_0 >> 3) & 0xf);
10482
-
*valp = t_0;
10372
+
*valp += pc;
10483
10373
return 0;
10484
10374
}
10485
10375
10486
10376
static int
10487
-
Operand_ae_samt64_decode (uint32 *valp)
10377
+
Operand_soffset_ator (uint32 *valp, uint32 pc)
10488
10378
{
10489
-
unsigned ae_samt64_0, ae_samt_s_t_0;
10490
-
ae_samt_s_t_0 = *valp & 0x3f;
10491
-
ae_samt64_0 = (0 << 6) | ae_samt_s_t_0;
10492
-
*valp = ae_samt64_0;
10379
+
*valp -= pc;
10493
10380
return 0;
10494
10381
}
10495
10382
10496
10383
static int
10497
-
Operand_ae_samt64_encode (uint32 *valp)
10384
+
Operand_soffset_rtoa (uint32 *valp, uint32 pc)
10498
10385
{
10499
-
unsigned ae_samt_s_t_0, ae_samt64_0;
10500
-
ae_samt64_0 = *valp;
10501
-
ae_samt_s_t_0 = (ae_samt64_0 & 0x3f);
10502
-
*valp = ae_samt_s_t_0;
10386
+
*valp += pc;
10503
10387
return 0;
10504
10388
}
10505
10389
10506
10390
static int
10507
-
Operand_ae_ohba_decode (uint32 *valp)
10391
+
Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
10508
10392
{
10509
-
unsigned ae_ohba_0, op1_0;
10510
-
op1_0 = *valp & 0xf;
10511
-
ae_ohba_0 = (0 << 5) | (((((op1_0 & 0xf))) == 0) << 4) | ((op1_0 & 0xf));
10512
-
*valp = ae_ohba_0;
10393
+
*valp -= ((pc + 3) & ~0x3);
10513
10394
return 0;
10514
10395
}
10515
10396
10516
10397
static int
10517
-
Operand_ae_ohba_encode (uint32 *valp)
10398
+
Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
10518
10399
{
10519
-
unsigned op1_0, ae_ohba_0;
10520
-
ae_ohba_0 = *valp;
10521
-
op1_0 = (ae_ohba_0 & 0xf);
10522
-
*valp = op1_0;
10400
+
*valp += ((pc + 3) & ~0x3);
10523
10401
return 0;
10524
10402
}
10525
10403
10526
10404
static int
10527
-
Operand_pr_decode (uint32 *valp ATTRIBUTE_UNUSED)
10405
+
Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
10528
10406
{
10407
+
*valp -= pc;
10529
10408
return 0;
10530
10409
}
10531
10410
10532
10411
static int
10533
-
Operand_pr_encode (uint32 *valp)
10412
+
Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
10534
10413
{
10535
-
int error;
10536
-
error = (*valp & ~0x7) != 0;
10537
-
return error;
10538
-
}
10539
-
10540
-
static int
10541
-
Operand_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED)
10542
-
{
10414
+
*valp += pc;
10543
10415
return 0;
10544
10416
}
10545
10417
10546
10418
static int
10547
-
Operand_qr0_rw_encode (uint32 *valp)
10419
+
Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
10548
10420
{
10549
-
int error;
10550
-
error = (*valp & ~0x3) != 0;
10551
-
return error;
10552
-
}
10553
-
10554
-
static int
10555
-
Operand_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED)
10556
-
{
10421
+
*valp -= pc;
10557
10422
return 0;
10558
10423
}
10559
10424
10560
10425
static int
10561
-
Operand_qr1_w_encode (uint32 *valp)
10426
+
Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
10562
10427
{
10563
-
int error;
10564
-
error = (*valp & ~0x3) != 0;
10565
-
return error;
10566
-
}
10567
-
10568
-
static int
10569
-
Operand_ps_decode (uint32 *valp ATTRIBUTE_UNUSED)
10570
-
{
10428
+
*valp += pc;
10571
10429
return 0;
10572
10430
}
10573
10431
10574
-
static int
10575
-
Operand_ps_encode (uint32 *valp)
10576
-
{
10577
-
int error;
10578
-
error = (*valp & ~0x7) != 0;
10579
-
return error;
10580
-
}
10581
-
10582
10432
static xtensa_operand_internal operands[] = {
10583
10433
{ "soffsetx4", FIELD_offset, -1, 0,
10584
10434
XTENSA_OPERAND_IS_PCRELATIVE,
10585
-
Operand_soffsetx4_encode, Operand_soffsetx4_decode,
10435
+
OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
10586
10436
Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
10587
10437
{ "uimm12x8", FIELD_imm12, -1, 0,
10588
10438
0,
10589
-
Operand_uimm12x8_encode, Operand_uimm12x8_decode,
10439
+
OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
10590
10440
0, 0 },
10591
10441
{ "simm4", FIELD_mn, -1, 0,
10592
10442
0,
10593
-
Operand_simm4_encode, Operand_simm4_decode,
10443
+
OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
10594
10444
0, 0 },
10595
10445
{ "arr", FIELD_r, REGFILE_AR, 1,
10596
10446
XTENSA_OPERAND_IS_REGISTER,
10597
-
Operand_arr_encode, Operand_arr_decode,
10447
+
OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10598
10448
0, 0 },
10599
10449
{ "ars", FIELD_s, REGFILE_AR, 1,
10600
10450
XTENSA_OPERAND_IS_REGISTER,
10601
-
Operand_ars_encode, Operand_ars_decode,
10451
+
OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10602
10452
0, 0 },
10603
10453
{ "*ars_invisible", FIELD_s, REGFILE_AR, 1,
10604
10454
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10605
-
Operand_ars_encode, Operand_ars_decode,
10455
+
OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10606
10456
0, 0 },
10607
10457
{ "art", FIELD_t, REGFILE_AR, 1,
10608
10458
XTENSA_OPERAND_IS_REGISTER,
10609
-
Operand_art_encode, Operand_art_decode,
10459
+
OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
10610
10460
0, 0 },
10611
10461
{ "ar0", FIELD__ar0, REGFILE_AR, 1,
10612
10462
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10613
-
Operand_ar0_encode, Operand_ar0_decode,
10463
+
OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
10614
10464
0, 0 },
10615
10465
{ "ar4", FIELD__ar4, REGFILE_AR, 1,
10616
10466
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10617
-
Operand_ar4_encode, Operand_ar4_decode,
10467
+
OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
10618
10468
0, 0 },
10619
10469
{ "ar8", FIELD__ar8, REGFILE_AR, 1,
10620
10470
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10621
-
Operand_ar8_encode, Operand_ar8_decode,
10471
+
OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
10622
10472
0, 0 },
10623
10473
{ "ar12", FIELD__ar12, REGFILE_AR, 1,
10624
10474
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10625
-
Operand_ar12_encode, Operand_ar12_decode,
10475
+
OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
10626
10476
0, 0 },
10627
10477
{ "ars_entry", FIELD_s, REGFILE_AR, 1,
10628
10478
XTENSA_OPERAND_IS_REGISTER,
10629
-
Operand_ars_entry_encode, Operand_ars_entry_decode,
10479
+
OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
10630
10480
0, 0 },
10631
10481
{ "immrx4", FIELD_r, -1, 0,
10632
10482
0,
10633
-
Operand_immrx4_encode, Operand_immrx4_decode,
10483
+
OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
10634
10484
0, 0 },
10635
10485
{ "lsi4x4", FIELD_r, -1, 0,
10636
10486
0,
10637
-
Operand_lsi4x4_encode, Operand_lsi4x4_decode,
10487
+
OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
10638
10488
0, 0 },
10639
10489
{ "simm7", FIELD_imm7, -1, 0,
10640
10490
0,
10641
-
Operand_simm7_encode, Operand_simm7_decode,
10491
+
OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
10642
10492
0, 0 },
10643
10493
{ "uimm6", FIELD_imm6, -1, 0,
10644
10494
XTENSA_OPERAND_IS_PCRELATIVE,
10645
-
Operand_uimm6_encode, Operand_uimm6_decode,
10495
+
OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
10646
10496
Operand_uimm6_ator, Operand_uimm6_rtoa },
10647
10497
{ "ai4const", FIELD_t, -1, 0,
10648
10498
0,
10649
-
Operand_ai4const_encode, Operand_ai4const_decode,
10499
+
OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
10650
10500
0, 0 },
10651
10501
{ "b4const", FIELD_r, -1, 0,
10652
10502
0,
10653
-
Operand_b4const_encode, Operand_b4const_decode,
10503
+
OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
10654
10504
0, 0 },
10655
10505
{ "b4constu", FIELD_r, -1, 0,
10656
10506
0,
10657
-
Operand_b4constu_encode, Operand_b4constu_decode,
10507
+
OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
10658
10508
0, 0 },
10659
10509
{ "uimm8", FIELD_imm8, -1, 0,
10660
10510
0,
10661
-
Operand_uimm8_encode, Operand_uimm8_decode,
10511
+
OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
10662
10512
0, 0 },
10663
10513
{ "uimm8x2", FIELD_imm8, -1, 0,
10664
10514
0,
10665
-
Operand_uimm8x2_encode, Operand_uimm8x2_decode,
10515
+
OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
10666
10516
0, 0 },
10667
10517
{ "uimm8x4", FIELD_imm8, -1, 0,
10668
10518
0,
10669
-
Operand_uimm8x4_encode, Operand_uimm8x4_decode,
10519
+
OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
10670
10520
0, 0 },
10671
10521
{ "uimm4x16", FIELD_op2, -1, 0,
10672
10522
0,
10673
-
Operand_uimm4x16_encode, Operand_uimm4x16_decode,
10523
+
OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
10524
+
0, 0 },
10525
+
{ "uimmrx4", FIELD_r, -1, 0,
10526
+
0,
10527
+
OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
10674
10528
0, 0 },
10675
10529
{ "simm8", FIELD_imm8, -1, 0,
10676
10530
0,
10677
-
Operand_simm8_encode, Operand_simm8_decode,
10531
+
OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
10678
10532
0, 0 },
10679
10533
{ "simm8x256", FIELD_imm8, -1, 0,
10680
10534
0,
10681
-
Operand_simm8x256_encode, Operand_simm8x256_decode,
10535
+
OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
10682
10536
0, 0 },
10683
10537
{ "simm12b", FIELD_imm12b, -1, 0,
10684
10538
0,
10685
-
Operand_simm12b_encode, Operand_simm12b_decode,
10539
+
OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
10686
10540
0, 0 },
10687
10541
{ "msalp32", FIELD_sal, -1, 0,
10688
10542
0,
10689
-
Operand_msalp32_encode, Operand_msalp32_decode,
10543
+
OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
10690
10544
0, 0 },
10691
10545
{ "op2p1", FIELD_op2, -1, 0,
10692
10546
0,
10693
-
Operand_op2p1_encode, Operand_op2p1_decode,
10547
+
OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
10694
10548
0, 0 },
10695
10549
{ "label8", FIELD_imm8, -1, 0,
10696
10550
XTENSA_OPERAND_IS_PCRELATIVE,
10697
-
Operand_label8_encode, Operand_label8_decode,
10551
+
OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
10698
10552
Operand_label8_ator, Operand_label8_rtoa },
10699
10553
{ "ulabel8", FIELD_imm8, -1, 0,
10700
10554
XTENSA_OPERAND_IS_PCRELATIVE,
10701
-
Operand_ulabel8_encode, Operand_ulabel8_decode,
10555
+
OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
10702
10556
Operand_ulabel8_ator, Operand_ulabel8_rtoa },
10703
10557
{ "label12", FIELD_imm12, -1, 0,
10704
10558
XTENSA_OPERAND_IS_PCRELATIVE,
10705
-
Operand_label12_encode, Operand_label12_decode,
10559
+
OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
10706
10560
Operand_label12_ator, Operand_label12_rtoa },
10707
10561
{ "soffset", FIELD_offset, -1, 0,
10708
10562
XTENSA_OPERAND_IS_PCRELATIVE,
10709
-
Operand_soffset_encode, Operand_soffset_decode,
10563
+
OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
10710
10564
Operand_soffset_ator, Operand_soffset_rtoa },
10711
10565
{ "uimm16x4", FIELD_imm16, -1, 0,
10712
10566
XTENSA_OPERAND_IS_PCRELATIVE,
10713
-
Operand_uimm16x4_encode, Operand_uimm16x4_decode,
10567
+
OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
10714
10568
Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
10569
+
{ "bbi", FIELD_bbi, -1, 0,
10570
+
0,
10571
+
OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10572
+
0, 0 },
10573
+
{ "sae", FIELD_sae, -1, 0,
10574
+
0,
10575
+
OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10576
+
0, 0 },
10577
+
{ "sas", FIELD_sas, -1, 0,
10578
+
0,
10579
+
OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10580
+
0, 0 },
10581
+
{ "sargt", FIELD_sargt, -1, 0,
10582
+
0,
10583
+
OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
10584
+
0, 0 },
10585
+
{ "s", FIELD_s, -1, 0,
10586
+
0,
10587
+
OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
10588
+
0, 0 },
10715
10589
{ "immt", FIELD_t, -1, 0,
10716
10590
0,
10717
-
Operand_immt_encode, Operand_immt_decode,
10591
+
OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
10718
10592
0, 0 },
10719
10593
{ "imms", FIELD_s, -1, 0,
10720
10594
0,
10721
-
Operand_imms_encode, Operand_imms_decode,
10595
+
OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
10722
10596
0, 0 },
10723
10597
{ "bt", FIELD_t, REGFILE_BR, 1,
10724
10598
XTENSA_OPERAND_IS_REGISTER,
10725
-
Operand_bt_encode, Operand_bt_decode,
10599
+
OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10726
10600
0, 0 },
10727
10601
{ "bs", FIELD_s, REGFILE_BR, 1,
10728
10602
XTENSA_OPERAND_IS_REGISTER,
10729
-
Operand_bs_encode, Operand_bs_decode,
10603
+
OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10730
10604
0, 0 },
10731
10605
{ "br", FIELD_r, REGFILE_BR, 1,
10732
10606
XTENSA_OPERAND_IS_REGISTER,
10733
-
Operand_br_encode, Operand_br_decode,
10607
+
OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
10734
10608
0, 0 },
10735
10609
{ "bt2", FIELD_t2, REGFILE_BR, 2,
10736
10610
XTENSA_OPERAND_IS_REGISTER,
10737
-
Operand_bt2_encode, Operand_bt2_decode,
10611
+
OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10738
10612
0, 0 },
10739
10613
{ "bs2", FIELD_s2, REGFILE_BR, 2,
10740
10614
XTENSA_OPERAND_IS_REGISTER,
10741
-
Operand_bs2_encode, Operand_bs2_decode,
10615
+
OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10742
10616
0, 0 },
10743
10617
{ "br2", FIELD_r2, REGFILE_BR, 2,
10744
10618
XTENSA_OPERAND_IS_REGISTER,
10745
-
Operand_br2_encode, Operand_br2_decode,
10619
+
OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
10746
10620
0, 0 },
10747
10621
{ "bt4", FIELD_t4, REGFILE_BR, 4,
10748
10622
XTENSA_OPERAND_IS_REGISTER,
10749
-
Operand_bt4_encode, Operand_bt4_decode,
10623
+
OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10750
10624
0, 0 },
10751
10625
{ "bs4", FIELD_s4, REGFILE_BR, 4,
10752
10626
XTENSA_OPERAND_IS_REGISTER,
10753
-
Operand_bs4_encode, Operand_bs4_decode,
10627
+
OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10754
10628
0, 0 },
10755
10629
{ "br4", FIELD_r4, REGFILE_BR, 4,
10756
10630
XTENSA_OPERAND_IS_REGISTER,
10757
-
Operand_br4_encode, Operand_br4_decode,
10631
+
OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
10758
10632
0, 0 },
10759
10633
{ "bt8", FIELD_t8, REGFILE_BR, 8,
10760
10634
XTENSA_OPERAND_IS_REGISTER,
10761
-
Operand_bt8_encode, Operand_bt8_decode,
10635
+
OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10762
10636
0, 0 },
10763
10637
{ "bs8", FIELD_s8, REGFILE_BR, 8,
10764
10638
XTENSA_OPERAND_IS_REGISTER,
10765
-
Operand_bs8_encode, Operand_bs8_decode,
10639
+
OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10766
10640
0, 0 },
10767
10641
{ "br8", FIELD_r8, REGFILE_BR, 8,
10768
10642
XTENSA_OPERAND_IS_REGISTER,
10769
-
Operand_br8_encode, Operand_br8_decode,
10643
+
OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
10770
10644
0, 0 },
10771
10645
{ "bt16", FIELD__bt16, REGFILE_BR, 16,
10772
10646
XTENSA_OPERAND_IS_REGISTER,
10773
-
Operand_bt16_encode, Operand_bt16_decode,
10647
+
OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10774
10648
0, 0 },
10775
10649
{ "bs16", FIELD__bs16, REGFILE_BR, 16,
10776
10650
XTENSA_OPERAND_IS_REGISTER,
10777
-
Operand_bs16_encode, Operand_bs16_decode,
10651
+
OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10778
10652
0, 0 },
10779
10653
{ "br16", FIELD__br16, REGFILE_BR, 16,
10780
10654
XTENSA_OPERAND_IS_REGISTER,
10781
-
Operand_br16_encode, Operand_br16_decode,
10655
+
OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10782
10656
0, 0 },
10783
10657
{ "brall", FIELD__brall, REGFILE_BR, 16,
10784
10658
XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
10785
-
Operand_brall_encode, Operand_brall_decode,
10659
+
OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
10786
10660
0, 0 },
10787
10661
{ "tp7", FIELD_t, -1, 0,
10788
10662
0,
10789
-
Operand_tp7_encode, Operand_tp7_decode,
10663
+
OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
10790
10664
0, 0 },
10791
10665
{ "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
10792
10666
XTENSA_OPERAND_IS_PCRELATIVE,
10793
-
Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
10667
+
OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
10794
10668
Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
10795
10669
{ "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
10796
10670
XTENSA_OPERAND_IS_PCRELATIVE,
10797
-
Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
10671
+
OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
10798
10672
Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
10799
10673
{ "ae_samt32", FIELD_ftsf14, -1, 0,
10800
10674
0,
10801
-
Operand_ae_samt32_encode, Operand_ae_samt32_decode,
10675
+
OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
10802
10676
0, 0 },
10803
10677
{ "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
10804
10678
XTENSA_OPERAND_IS_REGISTER,
10805
-
Operand_pr0_encode, Operand_pr0_decode,
10679
+
OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10806
10680
0, 0 },
10807
10681
{ "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
10808
10682
XTENSA_OPERAND_IS_REGISTER,
10809
-
Operand_qr0_encode, Operand_qr0_decode,
10683
+
OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10684
+
0, 0 },
10685
+
{ "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
10686
+
XTENSA_OPERAND_IS_REGISTER,
10687
+
OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10810
10688
0, 0 },
10811
10689
{ "ae_lsimm16", FIELD_t, -1, 0,
10812
10690
0,
10813
-
Operand_ae_lsimm16_encode, Operand_ae_lsimm16_decode,
10691
+
OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
10814
10692
0, 0 },
10815
10693
{ "ae_lsimm32", FIELD_t, -1, 0,
10816
10694
0,
10817
-
Operand_ae_lsimm32_encode, Operand_ae_lsimm32_decode,
10695
+
OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
10818
10696
0, 0 },
10819
10697
{ "ae_lsimm64", FIELD_t, -1, 0,
10820
10698
0,
10821
-
Operand_ae_lsimm64_encode, Operand_ae_lsimm64_decode,
10699
+
OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
10822
10700
0, 0 },
10823
10701
{ "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
10824
10702
0,
10825
-
Operand_ae_samt64_encode, Operand_ae_samt64_decode,
10703
+
OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
10704
+
0, 0 },
10705
+
{ "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
10706
+
0,
10707
+
OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
10826
10708
0, 0 },
10827
-
{ "ae_ohba", FIELD_op1, -1, 0,
10709
+
{ "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
10828
10710
0,
10829
-
Operand_ae_ohba_encode, Operand_ae_ohba_decode,
10711
+
OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
10830
10712
0, 0 },
10831
10713
{ "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
10832
10714
XTENSA_OPERAND_IS_REGISTER,
10833
-
Operand_pr_encode, Operand_pr_decode,
10715
+
OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10716
+
0, 0 },
10717
+
{ "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
10718
+
XTENSA_OPERAND_IS_REGISTER,
10719
+
OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10834
10720
0, 0 },
10835
10721
{ "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
10836
10722
XTENSA_OPERAND_IS_REGISTER,
10837
-
Operand_qr0_rw_encode, Operand_qr0_rw_decode,
10723
+
OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10724
+
0, 0 },
10725
+
{ "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
10726
+
XTENSA_OPERAND_IS_REGISTER,
10727
+
OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10838
10728
0, 0 },
10839
10729
{ "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
10840
10730
XTENSA_OPERAND_IS_REGISTER,
10841
-
Operand_qr1_w_encode, Operand_qr1_w_decode,
10731
+
OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10732
+
0, 0 },
10733
+
{ "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
10734
+
XTENSA_OPERAND_IS_REGISTER,
10735
+
OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
10842
10736
0, 0 },
10843
10737
{ "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
10844
10738
XTENSA_OPERAND_IS_REGISTER,
10845
-
Operand_ps_encode, Operand_ps_decode,
10739
+
OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10740
+
0, 0 },
10741
+
{ "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
10742
+
XTENSA_OPERAND_IS_REGISTER,
10743
+
OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
10846
10744
0, 0 },
10847
10745
{ "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
10848
10746
{ "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
10849
-
{ "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
10850
10747
{ "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
10851
10748
{ "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
10852
-
{ "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
10853
10749
{ "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
10854
10750
{ "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
10855
10751
{ "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
···
10861
10757
{ "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
10862
10758
{ "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
10863
10759
{ "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
10864
-
{ "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
10865
10760
{ "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
10866
-
{ "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
10867
10761
{ "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
10868
-
{ "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
10869
10762
{ "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
10870
10763
{ "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
10871
10764
{ "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
···
10898
10791
{ "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
10899
10792
{ "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
10900
10793
{ "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
10794
+
{ "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
10795
+
{ "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
10901
10796
{ "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
10902
10797
{ "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
10903
10798
{ "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
···
11249
11144
OPERAND_uimm8x2,
11250
11145
OPERAND_uimm8x4,
11251
11146
OPERAND_uimm4x16,
11147
+
OPERAND_uimmrx4,
11252
11148
OPERAND_simm8,
11253
11149
OPERAND_simm8x256,
11254
11150
OPERAND_simm12b,
···
11259
11155
OPERAND_label12,
11260
11156
OPERAND_soffset,
11261
11157
OPERAND_uimm16x4,
11158
+
OPERAND_bbi,
11159
+
OPERAND_sae,
11160
+
OPERAND_sas,
11161
+
OPERAND_sargt,
11162
+
OPERAND_s,
11262
11163
OPERAND_immt,
11263
11164
OPERAND_imms,
11264
11165
OPERAND_bt,
···
11283
11184
OPERAND_ae_samt32,
11284
11185
OPERAND_pr0,
11285
11186
OPERAND_qr0,
11187
+
OPERAND_mac_qr0,
11286
11188
OPERAND_ae_lsimm16,
11287
11189
OPERAND_ae_lsimm32,
11288
11190
OPERAND_ae_lsimm64,
11289
11191
OPERAND_ae_samt64,
11290
11192
OPERAND_ae_ohba,
11193
+
OPERAND_ae_ohba2,
11291
11194
OPERAND_pr,
11195
+
OPERAND_cvt_pr,
11292
11196
OPERAND_qr0_rw,
11197
+
OPERAND_mac_qr0_rw,
11293
11198
OPERAND_qr1_w,
11199
+
OPERAND_mac_qr1_w,
11294
11200
OPERAND_ps,
11201
+
OPERAND_alupppb_ps,
11295
11202
OPERAND_t,
11296
11203
OPERAND_bbi4,
11297
-
OPERAND_bbi,
11298
11204
OPERAND_imm12,
11299
11205
OPERAND_imm8,
11300
-
OPERAND_s,
11301
11206
OPERAND_imm12b,
11302
11207
OPERAND_imm16,
11303
11208
OPERAND_m,
···
11309
11214
OPERAND_r,
11310
11215
OPERAND_sa4,
11311
11216
OPERAND_sae4,
11312
-
OPERAND_sae,
11313
11217
OPERAND_sal,
11314
-
OPERAND_sargt,
11315
11218
OPERAND_sas4,
11316
-
OPERAND_sas,
11317
11219
OPERAND_sr,
11318
11220
OPERAND_st,
11319
11221
OPERAND_thi3,
···
11346
11248
OPERAND_ae_r20,
11347
11249
OPERAND_ae_r10,
11348
11250
OPERAND_ae_s20,
11251
+
OPERAND_ae_fld_ohba,
11252
+
OPERAND_ae_fld_ohba2,
11349
11253
OPERAND_op0_s3,
11350
11254
OPERAND_ftsf12,
11351
11255
OPERAND_ftsf13,
···
12316
12220
{ { STATE_LITBEN }, 'm' }
12317
12221
};
12318
12222
12319
-
static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
12223
+
static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
12320
12224
{ { OPERAND_art }, 'o' }
12321
12225
};
12322
12226
12323
-
static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
12227
+
static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
12324
12228
{ { STATE_PSEXCM }, 'i' },
12325
12229
{ { STATE_PSRING }, 'i' }
12326
12230
};
12327
12231
12328
-
static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
12232
+
static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
12329
12233
{ { OPERAND_art }, 'i' }
12330
12234
};
12331
12235
12332
-
static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
12236
+
static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
12333
12237
{ { STATE_PSEXCM }, 'i' },
12334
12238
{ { STATE_PSRING }, 'i' }
12335
12239
};
12336
12240
12337
-
static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
12241
+
static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
12338
12242
{ { OPERAND_art }, 'o' }
12339
12243
};
12340
12244
12341
-
static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
12245
+
static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
12342
12246
{ { STATE_PSEXCM }, 'i' },
12343
12247
{ { STATE_PSRING }, 'i' }
12344
12248
};
···
14759
14663
14760
14664
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
14761
14665
{ { OPERAND_qr1_w }, 'o' },
14762
-
{ { OPERAND_pr }, 'i' }
14666
+
{ { OPERAND_cvt_pr }, 'i' }
14763
14667
};
14764
14668
14765
14669
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
···
14768
14672
14769
14673
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
14770
14674
{ { OPERAND_qr1_w }, 'o' },
14771
-
{ { OPERAND_pr }, 'i' }
14675
+
{ { OPERAND_cvt_pr }, 'i' }
14772
14676
};
14773
14677
14774
14678
static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
···
14918
14822
};
14919
14823
14920
14824
static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
14921
-
{ { OPERAND_ps }, 'o' },
14825
+
{ { OPERAND_alupppb_ps }, 'o' },
14922
14826
{ { OPERAND_pr }, 'i' },
14923
14827
{ { OPERAND_pr0 }, 'i' },
14924
14828
{ { OPERAND_bt2 }, 'o' }
···
14929
14833
};
14930
14834
14931
14835
static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
14932
-
{ { OPERAND_ps }, 'o' },
14836
+
{ { OPERAND_alupppb_ps }, 'o' },
14933
14837
{ { OPERAND_pr }, 'i' },
14934
14838
{ { OPERAND_pr0 }, 'i' },
14935
14839
{ { OPERAND_bt2 }, 'o' }
···
15458
15362
};
15459
15363
15460
15364
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
15461
-
{ { OPERAND_qr1_w }, 'o' },
15365
+
{ { OPERAND_mac_qr1_w }, 'o' },
15462
15366
{ { OPERAND_pr }, 'i' },
15463
15367
{ { OPERAND_pr0 }, 'i' }
15464
15368
};
···
15469
15373
};
15470
15374
15471
15375
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
15472
-
{ { OPERAND_qr1_w }, 'o' },
15376
+
{ { OPERAND_mac_qr1_w }, 'o' },
15473
15377
{ { OPERAND_pr }, 'i' },
15474
15378
{ { OPERAND_pr0 }, 'i' }
15475
15379
};
···
15479
15383
};
15480
15384
15481
15385
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
15482
-
{ { OPERAND_qr1_w }, 'o' },
15386
+
{ { OPERAND_mac_qr1_w }, 'o' },
15483
15387
{ { OPERAND_pr }, 'i' },
15484
15388
{ { OPERAND_pr0 }, 'i' }
15485
15389
};
···
15489
15393
};
15490
15394
15491
15395
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
15492
-
{ { OPERAND_qr1_w }, 'o' },
15396
+
{ { OPERAND_mac_qr1_w }, 'o' },
15493
15397
{ { OPERAND_pr }, 'i' },
15494
15398
{ { OPERAND_pr0 }, 'i' }
15495
15399
};
···
15500
15404
};
15501
15405
15502
15406
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
15503
-
{ { OPERAND_qr1_w }, 'o' },
15407
+
{ { OPERAND_mac_qr1_w }, 'o' },
15504
15408
{ { OPERAND_pr }, 'i' },
15505
15409
{ { OPERAND_pr0 }, 'i' }
15506
15410
};
···
15510
15414
};
15511
15415
15512
15416
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
15513
-
{ { OPERAND_qr1_w }, 'o' },
15417
+
{ { OPERAND_mac_qr1_w }, 'o' },
15514
15418
{ { OPERAND_pr }, 'i' },
15515
15419
{ { OPERAND_pr0 }, 'i' }
15516
15420
};
···
15520
15424
};
15521
15425
15522
15426
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
15523
-
{ { OPERAND_qr1_w }, 'o' },
15427
+
{ { OPERAND_mac_qr1_w }, 'o' },
15524
15428
{ { OPERAND_pr }, 'i' },
15525
15429
{ { OPERAND_pr0 }, 'i' }
15526
15430
};
···
15531
15435
};
15532
15436
15533
15437
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
15534
-
{ { OPERAND_qr1_w }, 'o' },
15438
+
{ { OPERAND_mac_qr1_w }, 'o' },
15535
15439
{ { OPERAND_pr }, 'i' },
15536
15440
{ { OPERAND_pr0 }, 'i' }
15537
15441
};
···
15541
15445
};
15542
15446
15543
15447
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
15544
-
{ { OPERAND_qr1_w }, 'o' },
15448
+
{ { OPERAND_mac_qr1_w }, 'o' },
15545
15449
{ { OPERAND_pr }, 'i' },
15546
15450
{ { OPERAND_pr0 }, 'i' }
15547
15451
};
···
15551
15455
};
15552
15456
15553
15457
static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
15554
-
{ { OPERAND_qr1_w }, 'o' },
15458
+
{ { OPERAND_mac_qr1_w }, 'o' },
15555
15459
{ { OPERAND_pr }, 'i' },
15556
15460
{ { OPERAND_pr0 }, 'i' }
15557
15461
};
···
15562
15466
};
15563
15467
15564
15468
static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
15565
-
{ { OPERAND_qr1_w }, 'o' },
15469
+
{ { OPERAND_mac_qr1_w }, 'o' },
15566
15470
{ { OPERAND_pr }, 'i' },
15567
15471
{ { OPERAND_pr0 }, 'i' }
15568
15472
};
···
15572
15476
};
15573
15477
15574
15478
static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
15575
-
{ { OPERAND_qr1_w }, 'o' },
15479
+
{ { OPERAND_mac_qr1_w }, 'o' },
15576
15480
{ { OPERAND_pr }, 'i' },
15577
15481
{ { OPERAND_pr0 }, 'i' }
15578
15482
};
···
15582
15486
};
15583
15487
15584
15488
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
15585
-
{ { OPERAND_qr1_w }, 'm' },
15489
+
{ { OPERAND_mac_qr1_w }, 'm' },
15586
15490
{ { OPERAND_pr }, 'i' },
15587
15491
{ { OPERAND_pr0 }, 'i' }
15588
15492
};
···
15593
15497
};
15594
15498
15595
15499
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
15596
-
{ { OPERAND_qr1_w }, 'm' },
15500
+
{ { OPERAND_mac_qr1_w }, 'm' },
15597
15501
{ { OPERAND_pr }, 'i' },
15598
15502
{ { OPERAND_pr0 }, 'i' }
15599
15503
};
···
15603
15507
};
15604
15508
15605
15509
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
15606
-
{ { OPERAND_qr1_w }, 'm' },
15510
+
{ { OPERAND_mac_qr1_w }, 'm' },
15607
15511
{ { OPERAND_pr }, 'i' },
15608
15512
{ { OPERAND_pr0 }, 'i' }
15609
15513
};
···
15613
15517
};
15614
15518
15615
15519
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
15616
-
{ { OPERAND_qr1_w }, 'm' },
15520
+
{ { OPERAND_mac_qr1_w }, 'm' },
15617
15521
{ { OPERAND_pr }, 'i' },
15618
15522
{ { OPERAND_pr0 }, 'i' }
15619
15523
};
···
15624
15528
};
15625
15529
15626
15530
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
15627
-
{ { OPERAND_qr1_w }, 'm' },
15531
+
{ { OPERAND_mac_qr1_w }, 'm' },
15628
15532
{ { OPERAND_pr }, 'i' },
15629
15533
{ { OPERAND_pr0 }, 'i' }
15630
15534
};
···
15634
15538
};
15635
15539
15636
15540
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
15637
-
{ { OPERAND_qr1_w }, 'm' },
15541
+
{ { OPERAND_mac_qr1_w }, 'm' },
15638
15542
{ { OPERAND_pr }, 'i' },
15639
15543
{ { OPERAND_pr0 }, 'i' }
15640
15544
};
···
15644
15548
};
15645
15549
15646
15550
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
15647
-
{ { OPERAND_qr1_w }, 'm' },
15551
+
{ { OPERAND_mac_qr1_w }, 'm' },
15648
15552
{ { OPERAND_pr }, 'i' },
15649
15553
{ { OPERAND_pr0 }, 'i' }
15650
15554
};
···
15655
15559
};
15656
15560
15657
15561
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
15658
-
{ { OPERAND_qr1_w }, 'm' },
15562
+
{ { OPERAND_mac_qr1_w }, 'm' },
15659
15563
{ { OPERAND_pr }, 'i' },
15660
15564
{ { OPERAND_pr0 }, 'i' }
15661
15565
};
···
15665
15569
};
15666
15570
15667
15571
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
15668
-
{ { OPERAND_qr1_w }, 'm' },
15572
+
{ { OPERAND_mac_qr1_w }, 'm' },
15669
15573
{ { OPERAND_pr }, 'i' },
15670
15574
{ { OPERAND_pr0 }, 'i' }
15671
15575
};
···
15675
15579
};
15676
15580
15677
15581
static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
15678
-
{ { OPERAND_qr1_w }, 'm' },
15582
+
{ { OPERAND_mac_qr1_w }, 'm' },
15679
15583
{ { OPERAND_pr }, 'i' },
15680
15584
{ { OPERAND_pr0 }, 'i' }
15681
15585
};
···
15686
15590
};
15687
15591
15688
15592
static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
15689
-
{ { OPERAND_qr1_w }, 'm' },
15593
+
{ { OPERAND_mac_qr1_w }, 'm' },
15690
15594
{ { OPERAND_pr }, 'i' },
15691
15595
{ { OPERAND_pr0 }, 'i' }
15692
15596
};
···
15696
15600
};
15697
15601
15698
15602
static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
15699
-
{ { OPERAND_qr1_w }, 'm' },
15603
+
{ { OPERAND_mac_qr1_w }, 'm' },
15700
15604
{ { OPERAND_pr }, 'i' },
15701
15605
{ { OPERAND_pr0 }, 'i' }
15702
15606
};
···
15706
15610
};
15707
15611
15708
15612
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
15709
-
{ { OPERAND_qr1_w }, 'm' },
15613
+
{ { OPERAND_mac_qr1_w }, 'm' },
15710
15614
{ { OPERAND_pr }, 'i' },
15711
15615
{ { OPERAND_pr0 }, 'i' }
15712
15616
};
···
15717
15621
};
15718
15622
15719
15623
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
15720
-
{ { OPERAND_qr1_w }, 'm' },
15624
+
{ { OPERAND_mac_qr1_w }, 'm' },
15721
15625
{ { OPERAND_pr }, 'i' },
15722
15626
{ { OPERAND_pr0 }, 'i' }
15723
15627
};
···
15727
15631
};
15728
15632
15729
15633
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
15730
-
{ { OPERAND_qr1_w }, 'm' },
15634
+
{ { OPERAND_mac_qr1_w }, 'm' },
15731
15635
{ { OPERAND_pr }, 'i' },
15732
15636
{ { OPERAND_pr0 }, 'i' }
15733
15637
};
···
15737
15641
};
15738
15642
15739
15643
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
15740
-
{ { OPERAND_qr1_w }, 'm' },
15644
+
{ { OPERAND_mac_qr1_w }, 'm' },
15741
15645
{ { OPERAND_pr }, 'i' },
15742
15646
{ { OPERAND_pr0 }, 'i' }
15743
15647
};
···
15748
15652
};
15749
15653
15750
15654
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
15751
-
{ { OPERAND_qr1_w }, 'm' },
15655
+
{ { OPERAND_mac_qr1_w }, 'm' },
15752
15656
{ { OPERAND_pr }, 'i' },
15753
15657
{ { OPERAND_pr0 }, 'i' }
15754
15658
};
···
15758
15662
};
15759
15663
15760
15664
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
15761
-
{ { OPERAND_qr1_w }, 'm' },
15665
+
{ { OPERAND_mac_qr1_w }, 'm' },
15762
15666
{ { OPERAND_pr }, 'i' },
15763
15667
{ { OPERAND_pr0 }, 'i' }
15764
15668
};
···
15768
15672
};
15769
15673
15770
15674
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
15771
-
{ { OPERAND_qr1_w }, 'm' },
15675
+
{ { OPERAND_mac_qr1_w }, 'm' },
15772
15676
{ { OPERAND_pr }, 'i' },
15773
15677
{ { OPERAND_pr0 }, 'i' }
15774
15678
};
···
15779
15683
};
15780
15684
15781
15685
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
15782
-
{ { OPERAND_qr1_w }, 'm' },
15686
+
{ { OPERAND_mac_qr1_w }, 'm' },
15783
15687
{ { OPERAND_pr }, 'i' },
15784
15688
{ { OPERAND_pr0 }, 'i' }
15785
15689
};
···
15789
15693
};
15790
15694
15791
15695
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
15792
-
{ { OPERAND_qr1_w }, 'm' },
15696
+
{ { OPERAND_mac_qr1_w }, 'm' },
15793
15697
{ { OPERAND_pr }, 'i' },
15794
15698
{ { OPERAND_pr0 }, 'i' }
15795
15699
};
···
15799
15703
};
15800
15704
15801
15705
static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
15802
-
{ { OPERAND_qr1_w }, 'm' },
15706
+
{ { OPERAND_mac_qr1_w }, 'm' },
15803
15707
{ { OPERAND_pr }, 'i' },
15804
15708
{ { OPERAND_pr0 }, 'i' }
15805
15709
};
···
15810
15714
};
15811
15715
15812
15716
static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
15813
-
{ { OPERAND_qr1_w }, 'm' },
15717
+
{ { OPERAND_mac_qr1_w }, 'm' },
15814
15718
{ { OPERAND_pr }, 'i' },
15815
15719
{ { OPERAND_pr0 }, 'i' }
15816
15720
};
···
15820
15724
};
15821
15725
15822
15726
static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
15823
-
{ { OPERAND_qr1_w }, 'm' },
15727
+
{ { OPERAND_mac_qr1_w }, 'm' },
15824
15728
{ { OPERAND_pr }, 'i' },
15825
15729
{ { OPERAND_pr0 }, 'i' }
15826
15730
};
···
15830
15734
};
15831
15735
15832
15736
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
15833
-
{ { OPERAND_qr1_w }, 'm' },
15737
+
{ { OPERAND_mac_qr1_w }, 'm' },
15834
15738
{ { OPERAND_pr }, 'i' },
15835
15739
{ { OPERAND_pr0 }, 'i' }
15836
15740
};
···
15841
15745
};
15842
15746
15843
15747
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
15844
-
{ { OPERAND_qr1_w }, 'm' },
15748
+
{ { OPERAND_mac_qr1_w }, 'm' },
15845
15749
{ { OPERAND_pr }, 'i' },
15846
15750
{ { OPERAND_pr0 }, 'i' }
15847
15751
};
···
15852
15756
};
15853
15757
15854
15758
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
15855
-
{ { OPERAND_qr1_w }, 'm' },
15759
+
{ { OPERAND_mac_qr1_w }, 'm' },
15856
15760
{ { OPERAND_pr }, 'i' },
15857
15761
{ { OPERAND_pr0 }, 'i' }
15858
15762
};
···
15863
15767
};
15864
15768
15865
15769
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
15866
-
{ { OPERAND_qr1_w }, 'm' },
15770
+
{ { OPERAND_mac_qr1_w }, 'm' },
15867
15771
{ { OPERAND_pr }, 'i' },
15868
15772
{ { OPERAND_pr0 }, 'i' }
15869
15773
};
···
15874
15778
};
15875
15779
15876
15780
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
15877
-
{ { OPERAND_qr1_w }, 'm' },
15781
+
{ { OPERAND_mac_qr1_w }, 'm' },
15878
15782
{ { OPERAND_pr }, 'i' },
15879
15783
{ { OPERAND_pr0 }, 'i' }
15880
15784
};
···
15885
15789
};
15886
15790
15887
15791
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
15888
-
{ { OPERAND_qr1_w }, 'm' },
15792
+
{ { OPERAND_mac_qr1_w }, 'm' },
15889
15793
{ { OPERAND_pr }, 'i' },
15890
15794
{ { OPERAND_pr0 }, 'i' }
15891
15795
};
···
15896
15800
};
15897
15801
15898
15802
static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
15899
-
{ { OPERAND_qr1_w }, 'm' },
15803
+
{ { OPERAND_mac_qr1_w }, 'm' },
15900
15804
{ { OPERAND_pr }, 'i' },
15901
15805
{ { OPERAND_pr0 }, 'i' }
15902
15806
};
···
15907
15811
};
15908
15812
15909
15813
static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
15910
-
{ { OPERAND_qr1_w }, 'm' },
15814
+
{ { OPERAND_mac_qr1_w }, 'm' },
15911
15815
{ { OPERAND_pr }, 'i' },
15912
15816
{ { OPERAND_pr0 }, 'i' }
15913
15817
};
···
15918
15822
};
15919
15823
15920
15824
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
15921
-
{ { OPERAND_qr1_w }, 'm' },
15825
+
{ { OPERAND_mac_qr1_w }, 'm' },
15922
15826
{ { OPERAND_pr }, 'i' },
15923
15827
{ { OPERAND_pr0 }, 'i' }
15924
15828
};
···
15929
15833
};
15930
15834
15931
15835
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
15932
-
{ { OPERAND_qr1_w }, 'm' },
15836
+
{ { OPERAND_mac_qr1_w }, 'm' },
15933
15837
{ { OPERAND_pr }, 'i' },
15934
15838
{ { OPERAND_pr0 }, 'i' }
15935
15839
};
···
15940
15844
};
15941
15845
15942
15846
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
15943
-
{ { OPERAND_qr1_w }, 'm' },
15847
+
{ { OPERAND_mac_qr1_w }, 'm' },
15944
15848
{ { OPERAND_pr }, 'i' },
15945
15849
{ { OPERAND_pr0 }, 'i' }
15946
15850
};
···
15951
15855
};
15952
15856
15953
15857
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
15954
-
{ { OPERAND_qr1_w }, 'm' },
15858
+
{ { OPERAND_mac_qr1_w }, 'm' },
15955
15859
{ { OPERAND_pr }, 'i' },
15956
15860
{ { OPERAND_pr0 }, 'i' }
15957
15861
};
···
15962
15866
};
15963
15867
15964
15868
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
15965
-
{ { OPERAND_qr1_w }, 'm' },
15869
+
{ { OPERAND_mac_qr1_w }, 'm' },
15966
15870
{ { OPERAND_pr }, 'i' },
15967
15871
{ { OPERAND_pr0 }, 'i' }
15968
15872
};
···
15973
15877
};
15974
15878
15975
15879
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
15976
-
{ { OPERAND_qr1_w }, 'm' },
15880
+
{ { OPERAND_mac_qr1_w }, 'm' },
15977
15881
{ { OPERAND_pr }, 'i' },
15978
15882
{ { OPERAND_pr0 }, 'i' }
15979
15883
};
···
15984
15888
};
15985
15889
15986
15890
static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
15987
-
{ { OPERAND_qr1_w }, 'm' },
15891
+
{ { OPERAND_mac_qr1_w }, 'm' },
15988
15892
{ { OPERAND_pr }, 'i' },
15989
15893
{ { OPERAND_pr0 }, 'i' }
15990
15894
};
···
15995
15899
};
15996
15900
15997
15901
static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
15998
-
{ { OPERAND_qr1_w }, 'm' },
15902
+
{ { OPERAND_mac_qr1_w }, 'm' },
15999
15903
{ { OPERAND_pr }, 'i' },
16000
15904
{ { OPERAND_pr0 }, 'i' }
16001
15905
};
···
16006
15910
};
16007
15911
16008
15912
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
16009
-
{ { OPERAND_qr1_w }, 'o' },
16010
-
{ { OPERAND_qr0_rw }, 'i' },
15913
+
{ { OPERAND_mac_qr1_w }, 'o' },
15914
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16011
15915
{ { OPERAND_pr }, 'i' }
16012
15916
};
16013
15917
···
16016
15920
};
16017
15921
16018
15922
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
16019
-
{ { OPERAND_qr1_w }, 'o' },
16020
-
{ { OPERAND_qr0_rw }, 'i' },
15923
+
{ { OPERAND_mac_qr1_w }, 'o' },
15924
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16021
15925
{ { OPERAND_pr }, 'i' }
16022
15926
};
16023
15927
···
16026
15930
};
16027
15931
16028
15932
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
16029
-
{ { OPERAND_qr1_w }, 'o' },
16030
-
{ { OPERAND_qr0_rw }, 'i' },
15933
+
{ { OPERAND_mac_qr1_w }, 'o' },
15934
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16031
15935
{ { OPERAND_pr }, 'i' }
16032
15936
};
16033
15937
···
16036
15940
};
16037
15941
16038
15942
static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
16039
-
{ { OPERAND_qr1_w }, 'o' },
16040
-
{ { OPERAND_qr0_rw }, 'i' },
15943
+
{ { OPERAND_mac_qr1_w }, 'o' },
15944
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16041
15945
{ { OPERAND_pr }, 'i' }
16042
15946
};
16043
15947
···
16046
15950
};
16047
15951
16048
15952
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
16049
-
{ { OPERAND_qr1_w }, 'o' },
16050
-
{ { OPERAND_qr0_rw }, 'i' },
15953
+
{ { OPERAND_mac_qr1_w }, 'o' },
15954
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16051
15955
{ { OPERAND_pr }, 'i' }
16052
15956
};
16053
15957
···
16056
15960
};
16057
15961
16058
15962
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
16059
-
{ { OPERAND_qr1_w }, 'o' },
16060
-
{ { OPERAND_qr0_rw }, 'i' },
15963
+
{ { OPERAND_mac_qr1_w }, 'o' },
15964
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16061
15965
{ { OPERAND_pr }, 'i' }
16062
15966
};
16063
15967
···
16066
15970
};
16067
15971
16068
15972
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
16069
-
{ { OPERAND_qr1_w }, 'o' },
16070
-
{ { OPERAND_qr0_rw }, 'i' },
15973
+
{ { OPERAND_mac_qr1_w }, 'o' },
15974
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16071
15975
{ { OPERAND_pr }, 'i' }
16072
15976
};
16073
15977
···
16076
15980
};
16077
15981
16078
15982
static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
16079
-
{ { OPERAND_qr1_w }, 'o' },
16080
-
{ { OPERAND_qr0_rw }, 'i' },
15983
+
{ { OPERAND_mac_qr1_w }, 'o' },
15984
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16081
15985
{ { OPERAND_pr }, 'i' }
16082
15986
};
16083
15987
···
16086
15990
};
16087
15991
16088
15992
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
16089
-
{ { OPERAND_qr1_w }, 'm' },
16090
-
{ { OPERAND_qr0_rw }, 'i' },
15993
+
{ { OPERAND_mac_qr1_w }, 'm' },
15994
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16091
15995
{ { OPERAND_pr }, 'i' }
16092
15996
};
16093
15997
···
16096
16000
};
16097
16001
16098
16002
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
16099
-
{ { OPERAND_qr1_w }, 'm' },
16100
-
{ { OPERAND_qr0_rw }, 'i' },
16003
+
{ { OPERAND_mac_qr1_w }, 'm' },
16004
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16101
16005
{ { OPERAND_pr }, 'i' }
16102
16006
};
16103
16007
···
16106
16010
};
16107
16011
16108
16012
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
16109
-
{ { OPERAND_qr1_w }, 'm' },
16110
-
{ { OPERAND_qr0_rw }, 'i' },
16013
+
{ { OPERAND_mac_qr1_w }, 'm' },
16014
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16111
16015
{ { OPERAND_pr }, 'i' }
16112
16016
};
16113
16017
···
16116
16020
};
16117
16021
16118
16022
static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
16119
-
{ { OPERAND_qr1_w }, 'm' },
16120
-
{ { OPERAND_qr0_rw }, 'i' },
16023
+
{ { OPERAND_mac_qr1_w }, 'm' },
16024
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16121
16025
{ { OPERAND_pr }, 'i' }
16122
16026
};
16123
16027
···
16126
16030
};
16127
16031
16128
16032
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
16129
-
{ { OPERAND_qr1_w }, 'm' },
16130
-
{ { OPERAND_qr0_rw }, 'i' },
16033
+
{ { OPERAND_mac_qr1_w }, 'm' },
16034
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16131
16035
{ { OPERAND_pr }, 'i' }
16132
16036
};
16133
16037
···
16136
16040
};
16137
16041
16138
16042
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
16139
-
{ { OPERAND_qr1_w }, 'm' },
16140
-
{ { OPERAND_qr0_rw }, 'i' },
16043
+
{ { OPERAND_mac_qr1_w }, 'm' },
16044
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16141
16045
{ { OPERAND_pr }, 'i' }
16142
16046
};
16143
16047
···
16146
16050
};
16147
16051
16148
16052
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
16149
-
{ { OPERAND_qr1_w }, 'm' },
16150
-
{ { OPERAND_qr0_rw }, 'i' },
16053
+
{ { OPERAND_mac_qr1_w }, 'm' },
16054
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16151
16055
{ { OPERAND_pr }, 'i' }
16152
16056
};
16153
16057
···
16156
16060
};
16157
16061
16158
16062
static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
16159
-
{ { OPERAND_qr1_w }, 'm' },
16160
-
{ { OPERAND_qr0_rw }, 'i' },
16063
+
{ { OPERAND_mac_qr1_w }, 'm' },
16064
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16161
16065
{ { OPERAND_pr }, 'i' }
16162
16066
};
16163
16067
···
16166
16070
};
16167
16071
16168
16072
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
16169
-
{ { OPERAND_qr1_w }, 'm' },
16170
-
{ { OPERAND_qr0_rw }, 'i' },
16073
+
{ { OPERAND_mac_qr1_w }, 'm' },
16074
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16171
16075
{ { OPERAND_pr }, 'i' }
16172
16076
};
16173
16077
···
16176
16080
};
16177
16081
16178
16082
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
16179
-
{ { OPERAND_qr1_w }, 'm' },
16180
-
{ { OPERAND_qr0_rw }, 'i' },
16083
+
{ { OPERAND_mac_qr1_w }, 'm' },
16084
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16181
16085
{ { OPERAND_pr }, 'i' }
16182
16086
};
16183
16087
···
16186
16090
};
16187
16091
16188
16092
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
16189
-
{ { OPERAND_qr1_w }, 'm' },
16190
-
{ { OPERAND_qr0_rw }, 'i' },
16093
+
{ { OPERAND_mac_qr1_w }, 'm' },
16094
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16191
16095
{ { OPERAND_pr }, 'i' }
16192
16096
};
16193
16097
···
16196
16100
};
16197
16101
16198
16102
static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
16199
-
{ { OPERAND_qr1_w }, 'm' },
16200
-
{ { OPERAND_qr0_rw }, 'i' },
16103
+
{ { OPERAND_mac_qr1_w }, 'm' },
16104
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16201
16105
{ { OPERAND_pr }, 'i' }
16202
16106
};
16203
16107
···
16206
16110
};
16207
16111
16208
16112
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
16209
-
{ { OPERAND_qr1_w }, 'm' },
16210
-
{ { OPERAND_qr0_rw }, 'i' },
16113
+
{ { OPERAND_mac_qr1_w }, 'm' },
16114
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16211
16115
{ { OPERAND_pr }, 'i' }
16212
16116
};
16213
16117
···
16216
16120
};
16217
16121
16218
16122
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
16219
-
{ { OPERAND_qr1_w }, 'm' },
16220
-
{ { OPERAND_qr0_rw }, 'i' },
16123
+
{ { OPERAND_mac_qr1_w }, 'm' },
16124
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16221
16125
{ { OPERAND_pr }, 'i' }
16222
16126
};
16223
16127
···
16226
16130
};
16227
16131
16228
16132
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
16229
-
{ { OPERAND_qr1_w }, 'm' },
16230
-
{ { OPERAND_qr0_rw }, 'i' },
16133
+
{ { OPERAND_mac_qr1_w }, 'm' },
16134
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16231
16135
{ { OPERAND_pr }, 'i' }
16232
16136
};
16233
16137
···
16236
16140
};
16237
16141
16238
16142
static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
16239
-
{ { OPERAND_qr1_w }, 'm' },
16240
-
{ { OPERAND_qr0_rw }, 'i' },
16143
+
{ { OPERAND_mac_qr1_w }, 'm' },
16144
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16241
16145
{ { OPERAND_pr }, 'i' }
16242
16146
};
16243
16147
···
16246
16150
};
16247
16151
16248
16152
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
16249
-
{ { OPERAND_qr1_w }, 'o' },
16250
-
{ { OPERAND_qr0_rw }, 'i' },
16153
+
{ { OPERAND_mac_qr1_w }, 'o' },
16154
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16251
16155
{ { OPERAND_pr }, 'i' },
16252
-
{ { OPERAND_qr0 }, 'i' },
16156
+
{ { OPERAND_mac_qr0 }, 'i' },
16253
16157
{ { OPERAND_pr0 }, 'i' }
16254
16158
};
16255
16159
···
16258
16162
};
16259
16163
16260
16164
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
16261
-
{ { OPERAND_qr1_w }, 'o' },
16262
-
{ { OPERAND_qr0_rw }, 'i' },
16165
+
{ { OPERAND_mac_qr1_w }, 'o' },
16166
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16263
16167
{ { OPERAND_pr }, 'i' },
16264
-
{ { OPERAND_qr0 }, 'i' },
16168
+
{ { OPERAND_mac_qr0 }, 'i' },
16265
16169
{ { OPERAND_pr0 }, 'i' }
16266
16170
};
16267
16171
···
16270
16174
};
16271
16175
16272
16176
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
16273
-
{ { OPERAND_qr1_w }, 'o' },
16274
-
{ { OPERAND_qr0_rw }, 'i' },
16177
+
{ { OPERAND_mac_qr1_w }, 'o' },
16178
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16275
16179
{ { OPERAND_pr }, 'i' },
16276
-
{ { OPERAND_qr0 }, 'i' },
16180
+
{ { OPERAND_mac_qr0 }, 'i' },
16277
16181
{ { OPERAND_pr0 }, 'i' }
16278
16182
};
16279
16183
···
16282
16186
};
16283
16187
16284
16188
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
16285
-
{ { OPERAND_qr1_w }, 'o' },
16286
-
{ { OPERAND_qr0_rw }, 'i' },
16189
+
{ { OPERAND_mac_qr1_w }, 'o' },
16190
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16287
16191
{ { OPERAND_pr }, 'i' },
16288
-
{ { OPERAND_qr0 }, 'i' },
16192
+
{ { OPERAND_mac_qr0 }, 'i' },
16289
16193
{ { OPERAND_pr0 }, 'i' }
16290
16194
};
16291
16195
···
16294
16198
};
16295
16199
16296
16200
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
16297
-
{ { OPERAND_qr1_w }, 'o' },
16298
-
{ { OPERAND_qr0_rw }, 'i' },
16201
+
{ { OPERAND_mac_qr1_w }, 'o' },
16202
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16299
16203
{ { OPERAND_pr }, 'i' },
16300
-
{ { OPERAND_qr0 }, 'i' },
16204
+
{ { OPERAND_mac_qr0 }, 'i' },
16301
16205
{ { OPERAND_pr0 }, 'i' }
16302
16206
};
16303
16207
···
16306
16210
};
16307
16211
16308
16212
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
16309
-
{ { OPERAND_qr1_w }, 'o' },
16310
-
{ { OPERAND_qr0_rw }, 'i' },
16213
+
{ { OPERAND_mac_qr1_w }, 'o' },
16214
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16311
16215
{ { OPERAND_pr }, 'i' },
16312
-
{ { OPERAND_qr0 }, 'i' },
16216
+
{ { OPERAND_mac_qr0 }, 'i' },
16313
16217
{ { OPERAND_pr0 }, 'i' }
16314
16218
};
16315
16219
···
16318
16222
};
16319
16223
16320
16224
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
16321
-
{ { OPERAND_qr1_w }, 'o' },
16322
-
{ { OPERAND_qr0_rw }, 'i' },
16225
+
{ { OPERAND_mac_qr1_w }, 'o' },
16226
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16323
16227
{ { OPERAND_pr }, 'i' },
16324
-
{ { OPERAND_qr0 }, 'i' },
16228
+
{ { OPERAND_mac_qr0 }, 'i' },
16325
16229
{ { OPERAND_pr0 }, 'i' }
16326
16230
};
16327
16231
···
16330
16234
};
16331
16235
16332
16236
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
16333
-
{ { OPERAND_qr1_w }, 'o' },
16334
-
{ { OPERAND_qr0_rw }, 'i' },
16237
+
{ { OPERAND_mac_qr1_w }, 'o' },
16238
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16335
16239
{ { OPERAND_pr }, 'i' },
16336
-
{ { OPERAND_qr0 }, 'i' },
16240
+
{ { OPERAND_mac_qr0 }, 'i' },
16337
16241
{ { OPERAND_pr0 }, 'i' }
16338
16242
};
16339
16243
···
16342
16246
};
16343
16247
16344
16248
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
16345
-
{ { OPERAND_qr1_w }, 'o' },
16346
-
{ { OPERAND_qr0_rw }, 'i' },
16249
+
{ { OPERAND_mac_qr1_w }, 'o' },
16250
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16347
16251
{ { OPERAND_pr }, 'i' },
16348
-
{ { OPERAND_qr0 }, 'i' },
16252
+
{ { OPERAND_mac_qr0 }, 'i' },
16349
16253
{ { OPERAND_pr0 }, 'i' }
16350
16254
};
16351
16255
···
16354
16258
};
16355
16259
16356
16260
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
16357
-
{ { OPERAND_qr1_w }, 'o' },
16358
-
{ { OPERAND_qr0_rw }, 'i' },
16261
+
{ { OPERAND_mac_qr1_w }, 'o' },
16262
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16359
16263
{ { OPERAND_pr }, 'i' },
16360
-
{ { OPERAND_qr0 }, 'i' },
16264
+
{ { OPERAND_mac_qr0 }, 'i' },
16361
16265
{ { OPERAND_pr0 }, 'i' }
16362
16266
};
16363
16267
···
16366
16270
};
16367
16271
16368
16272
static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
16369
-
{ { OPERAND_qr1_w }, 'o' },
16370
-
{ { OPERAND_qr0_rw }, 'i' },
16273
+
{ { OPERAND_mac_qr1_w }, 'o' },
16274
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16371
16275
{ { OPERAND_pr }, 'i' },
16372
-
{ { OPERAND_qr0 }, 'i' },
16276
+
{ { OPERAND_mac_qr0 }, 'i' },
16373
16277
{ { OPERAND_pr0 }, 'i' }
16374
16278
};
16375
16279
···
16378
16282
};
16379
16283
16380
16284
static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
16381
-
{ { OPERAND_qr1_w }, 'o' },
16382
-
{ { OPERAND_qr0_rw }, 'i' },
16285
+
{ { OPERAND_mac_qr1_w }, 'o' },
16286
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16383
16287
{ { OPERAND_pr }, 'i' },
16384
-
{ { OPERAND_qr0 }, 'i' },
16288
+
{ { OPERAND_mac_qr0 }, 'i' },
16385
16289
{ { OPERAND_pr0 }, 'i' }
16386
16290
};
16387
16291
···
16390
16294
};
16391
16295
16392
16296
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
16393
-
{ { OPERAND_qr1_w }, 'o' },
16394
-
{ { OPERAND_qr0_rw }, 'i' },
16297
+
{ { OPERAND_mac_qr1_w }, 'o' },
16298
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16395
16299
{ { OPERAND_pr }, 'i' },
16396
-
{ { OPERAND_qr0 }, 'i' },
16300
+
{ { OPERAND_mac_qr0 }, 'i' },
16397
16301
{ { OPERAND_pr0 }, 'i' }
16398
16302
};
16399
16303
···
16402
16306
};
16403
16307
16404
16308
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
16405
-
{ { OPERAND_qr1_w }, 'o' },
16406
-
{ { OPERAND_qr0_rw }, 'i' },
16309
+
{ { OPERAND_mac_qr1_w }, 'o' },
16310
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16407
16311
{ { OPERAND_pr }, 'i' },
16408
-
{ { OPERAND_qr0 }, 'i' },
16312
+
{ { OPERAND_mac_qr0 }, 'i' },
16409
16313
{ { OPERAND_pr0 }, 'i' }
16410
16314
};
16411
16315
···
16414
16318
};
16415
16319
16416
16320
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
16417
-
{ { OPERAND_qr1_w }, 'o' },
16418
-
{ { OPERAND_qr0_rw }, 'i' },
16321
+
{ { OPERAND_mac_qr1_w }, 'o' },
16322
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16419
16323
{ { OPERAND_pr }, 'i' },
16420
-
{ { OPERAND_qr0 }, 'i' },
16324
+
{ { OPERAND_mac_qr0 }, 'i' },
16421
16325
{ { OPERAND_pr0 }, 'i' }
16422
16326
};
16423
16327
···
16426
16330
};
16427
16331
16428
16332
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
16429
-
{ { OPERAND_qr1_w }, 'o' },
16430
-
{ { OPERAND_qr0_rw }, 'i' },
16333
+
{ { OPERAND_mac_qr1_w }, 'o' },
16334
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16431
16335
{ { OPERAND_pr }, 'i' },
16432
-
{ { OPERAND_qr0 }, 'i' },
16336
+
{ { OPERAND_mac_qr0 }, 'i' },
16433
16337
{ { OPERAND_pr0 }, 'i' }
16434
16338
};
16435
16339
···
16438
16342
};
16439
16343
16440
16344
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
16441
-
{ { OPERAND_qr1_w }, 'o' },
16442
-
{ { OPERAND_qr0_rw }, 'i' },
16345
+
{ { OPERAND_mac_qr1_w }, 'o' },
16346
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16443
16347
{ { OPERAND_pr }, 'i' },
16444
-
{ { OPERAND_qr0 }, 'i' },
16348
+
{ { OPERAND_mac_qr0 }, 'i' },
16445
16349
{ { OPERAND_pr0 }, 'i' }
16446
16350
};
16447
16351
···
16450
16354
};
16451
16355
16452
16356
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
16453
-
{ { OPERAND_qr1_w }, 'o' },
16454
-
{ { OPERAND_qr0_rw }, 'i' },
16357
+
{ { OPERAND_mac_qr1_w }, 'o' },
16358
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16455
16359
{ { OPERAND_pr }, 'i' },
16456
-
{ { OPERAND_qr0 }, 'i' },
16360
+
{ { OPERAND_mac_qr0 }, 'i' },
16457
16361
{ { OPERAND_pr0 }, 'i' }
16458
16362
};
16459
16363
···
16462
16366
};
16463
16367
16464
16368
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
16465
-
{ { OPERAND_qr1_w }, 'o' },
16466
-
{ { OPERAND_qr0_rw }, 'i' },
16369
+
{ { OPERAND_mac_qr1_w }, 'o' },
16370
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16467
16371
{ { OPERAND_pr }, 'i' },
16468
-
{ { OPERAND_qr0 }, 'i' },
16372
+
{ { OPERAND_mac_qr0 }, 'i' },
16469
16373
{ { OPERAND_pr0 }, 'i' }
16470
16374
};
16471
16375
···
16474
16378
};
16475
16379
16476
16380
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
16477
-
{ { OPERAND_qr1_w }, 'o' },
16478
-
{ { OPERAND_qr0_rw }, 'i' },
16381
+
{ { OPERAND_mac_qr1_w }, 'o' },
16382
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16479
16383
{ { OPERAND_pr }, 'i' },
16480
-
{ { OPERAND_qr0 }, 'i' },
16384
+
{ { OPERAND_mac_qr0 }, 'i' },
16481
16385
{ { OPERAND_pr0 }, 'i' }
16482
16386
};
16483
16387
···
16486
16390
};
16487
16391
16488
16392
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
16489
-
{ { OPERAND_qr1_w }, 'o' },
16490
-
{ { OPERAND_qr0_rw }, 'i' },
16393
+
{ { OPERAND_mac_qr1_w }, 'o' },
16394
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16491
16395
{ { OPERAND_pr }, 'i' },
16492
-
{ { OPERAND_qr0 }, 'i' },
16396
+
{ { OPERAND_mac_qr0 }, 'i' },
16493
16397
{ { OPERAND_pr0 }, 'i' }
16494
16398
};
16495
16399
···
16498
16402
};
16499
16403
16500
16404
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
16501
-
{ { OPERAND_qr1_w }, 'o' },
16502
-
{ { OPERAND_qr0_rw }, 'i' },
16405
+
{ { OPERAND_mac_qr1_w }, 'o' },
16406
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16503
16407
{ { OPERAND_pr }, 'i' },
16504
-
{ { OPERAND_qr0 }, 'i' },
16408
+
{ { OPERAND_mac_qr0 }, 'i' },
16505
16409
{ { OPERAND_pr0 }, 'i' }
16506
16410
};
16507
16411
···
16510
16414
};
16511
16415
16512
16416
static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
16513
-
{ { OPERAND_qr1_w }, 'o' },
16514
-
{ { OPERAND_qr0_rw }, 'i' },
16417
+
{ { OPERAND_mac_qr1_w }, 'o' },
16418
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16515
16419
{ { OPERAND_pr }, 'i' },
16516
-
{ { OPERAND_qr0 }, 'i' },
16420
+
{ { OPERAND_mac_qr0 }, 'i' },
16517
16421
{ { OPERAND_pr0 }, 'i' }
16518
16422
};
16519
16423
···
16522
16426
};
16523
16427
16524
16428
static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
16525
-
{ { OPERAND_qr1_w }, 'o' },
16526
-
{ { OPERAND_qr0_rw }, 'i' },
16429
+
{ { OPERAND_mac_qr1_w }, 'o' },
16430
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16527
16431
{ { OPERAND_pr }, 'i' },
16528
-
{ { OPERAND_qr0 }, 'i' },
16432
+
{ { OPERAND_mac_qr0 }, 'i' },
16529
16433
{ { OPERAND_pr0 }, 'i' }
16530
16434
};
16531
16435
···
16534
16438
};
16535
16439
16536
16440
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
16537
-
{ { OPERAND_qr1_w }, 'o' },
16538
-
{ { OPERAND_qr0_rw }, 'i' },
16441
+
{ { OPERAND_mac_qr1_w }, 'o' },
16442
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16539
16443
{ { OPERAND_pr }, 'i' },
16540
-
{ { OPERAND_qr0 }, 'i' },
16444
+
{ { OPERAND_mac_qr0 }, 'i' },
16541
16445
{ { OPERAND_pr0 }, 'i' }
16542
16446
};
16543
16447
···
16546
16450
};
16547
16451
16548
16452
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
16549
-
{ { OPERAND_qr1_w }, 'o' },
16550
-
{ { OPERAND_qr0_rw }, 'i' },
16453
+
{ { OPERAND_mac_qr1_w }, 'o' },
16454
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16551
16455
{ { OPERAND_pr }, 'i' },
16552
-
{ { OPERAND_qr0 }, 'i' },
16456
+
{ { OPERAND_mac_qr0 }, 'i' },
16553
16457
{ { OPERAND_pr0 }, 'i' }
16554
16458
};
16555
16459
···
16558
16462
};
16559
16463
16560
16464
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
16561
-
{ { OPERAND_qr1_w }, 'o' },
16562
-
{ { OPERAND_qr0_rw }, 'i' },
16465
+
{ { OPERAND_mac_qr1_w }, 'o' },
16466
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16563
16467
{ { OPERAND_pr }, 'i' },
16564
-
{ { OPERAND_qr0 }, 'i' },
16468
+
{ { OPERAND_mac_qr0 }, 'i' },
16565
16469
{ { OPERAND_pr0 }, 'i' }
16566
16470
};
16567
16471
···
16570
16474
};
16571
16475
16572
16476
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
16573
-
{ { OPERAND_qr1_w }, 'o' },
16574
-
{ { OPERAND_qr0_rw }, 'i' },
16477
+
{ { OPERAND_mac_qr1_w }, 'o' },
16478
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16575
16479
{ { OPERAND_pr }, 'i' },
16576
-
{ { OPERAND_qr0 }, 'i' },
16480
+
{ { OPERAND_mac_qr0 }, 'i' },
16577
16481
{ { OPERAND_pr0 }, 'i' }
16578
16482
};
16579
16483
···
16582
16486
};
16583
16487
16584
16488
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
16585
-
{ { OPERAND_qr1_w }, 'o' },
16586
-
{ { OPERAND_qr0_rw }, 'i' },
16489
+
{ { OPERAND_mac_qr1_w }, 'o' },
16490
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16587
16491
{ { OPERAND_pr }, 'i' },
16588
-
{ { OPERAND_qr0 }, 'i' },
16492
+
{ { OPERAND_mac_qr0 }, 'i' },
16589
16493
{ { OPERAND_pr0 }, 'i' }
16590
16494
};
16591
16495
···
16594
16498
};
16595
16499
16596
16500
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
16597
-
{ { OPERAND_qr1_w }, 'o' },
16598
-
{ { OPERAND_qr0_rw }, 'i' },
16501
+
{ { OPERAND_mac_qr1_w }, 'o' },
16502
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16599
16503
{ { OPERAND_pr }, 'i' },
16600
-
{ { OPERAND_qr0 }, 'i' },
16504
+
{ { OPERAND_mac_qr0 }, 'i' },
16601
16505
{ { OPERAND_pr0 }, 'i' }
16602
16506
};
16603
16507
···
16606
16510
};
16607
16511
16608
16512
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
16609
-
{ { OPERAND_qr1_w }, 'o' },
16610
-
{ { OPERAND_qr0_rw }, 'i' },
16513
+
{ { OPERAND_mac_qr1_w }, 'o' },
16514
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16611
16515
{ { OPERAND_pr }, 'i' },
16612
-
{ { OPERAND_qr0 }, 'i' },
16516
+
{ { OPERAND_mac_qr0 }, 'i' },
16613
16517
{ { OPERAND_pr0 }, 'i' }
16614
16518
};
16615
16519
···
16618
16522
};
16619
16523
16620
16524
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
16621
-
{ { OPERAND_qr1_w }, 'o' },
16622
-
{ { OPERAND_qr0_rw }, 'i' },
16525
+
{ { OPERAND_mac_qr1_w }, 'o' },
16526
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16623
16527
{ { OPERAND_pr }, 'i' },
16624
-
{ { OPERAND_qr0 }, 'i' },
16528
+
{ { OPERAND_mac_qr0 }, 'i' },
16625
16529
{ { OPERAND_pr0 }, 'i' }
16626
16530
};
16627
16531
···
16630
16534
};
16631
16535
16632
16536
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
16633
-
{ { OPERAND_qr1_w }, 'o' },
16634
-
{ { OPERAND_qr0_rw }, 'i' },
16537
+
{ { OPERAND_mac_qr1_w }, 'o' },
16538
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16635
16539
{ { OPERAND_pr }, 'i' },
16636
-
{ { OPERAND_qr0 }, 'i' },
16540
+
{ { OPERAND_mac_qr0 }, 'i' },
16637
16541
{ { OPERAND_pr0 }, 'i' }
16638
16542
};
16639
16543
···
16642
16546
};
16643
16547
16644
16548
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
16645
-
{ { OPERAND_qr1_w }, 'o' },
16646
-
{ { OPERAND_qr0_rw }, 'i' },
16549
+
{ { OPERAND_mac_qr1_w }, 'o' },
16550
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16647
16551
{ { OPERAND_pr }, 'i' },
16648
-
{ { OPERAND_qr0 }, 'i' },
16552
+
{ { OPERAND_mac_qr0 }, 'i' },
16649
16553
{ { OPERAND_pr0 }, 'i' }
16650
16554
};
16651
16555
···
16654
16558
};
16655
16559
16656
16560
static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
16657
-
{ { OPERAND_qr1_w }, 'o' },
16658
-
{ { OPERAND_qr0_rw }, 'i' },
16561
+
{ { OPERAND_mac_qr1_w }, 'o' },
16562
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16659
16563
{ { OPERAND_pr }, 'i' },
16660
-
{ { OPERAND_qr0 }, 'i' },
16564
+
{ { OPERAND_mac_qr0 }, 'i' },
16661
16565
{ { OPERAND_pr0 }, 'i' }
16662
16566
};
16663
16567
···
16666
16570
};
16667
16571
16668
16572
static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
16669
-
{ { OPERAND_qr1_w }, 'o' },
16670
-
{ { OPERAND_qr0_rw }, 'i' },
16573
+
{ { OPERAND_mac_qr1_w }, 'o' },
16574
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16671
16575
{ { OPERAND_pr }, 'i' },
16672
-
{ { OPERAND_qr0 }, 'i' },
16576
+
{ { OPERAND_mac_qr0 }, 'i' },
16673
16577
{ { OPERAND_pr0 }, 'i' }
16674
16578
};
16675
16579
···
16678
16582
};
16679
16583
16680
16584
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
16681
-
{ { OPERAND_qr1_w }, 'o' },
16682
-
{ { OPERAND_qr0_rw }, 'i' },
16585
+
{ { OPERAND_mac_qr1_w }, 'o' },
16586
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16683
16587
{ { OPERAND_pr }, 'i' },
16684
-
{ { OPERAND_qr0 }, 'i' },
16588
+
{ { OPERAND_mac_qr0 }, 'i' },
16685
16589
{ { OPERAND_pr0 }, 'i' }
16686
16590
};
16687
16591
···
16690
16594
};
16691
16595
16692
16596
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
16693
-
{ { OPERAND_qr1_w }, 'o' },
16694
-
{ { OPERAND_qr0_rw }, 'i' },
16597
+
{ { OPERAND_mac_qr1_w }, 'o' },
16598
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16695
16599
{ { OPERAND_pr }, 'i' },
16696
-
{ { OPERAND_qr0 }, 'i' },
16600
+
{ { OPERAND_mac_qr0 }, 'i' },
16697
16601
{ { OPERAND_pr0 }, 'i' }
16698
16602
};
16699
16603
···
16702
16606
};
16703
16607
16704
16608
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
16705
-
{ { OPERAND_qr1_w }, 'o' },
16706
-
{ { OPERAND_qr0_rw }, 'i' },
16609
+
{ { OPERAND_mac_qr1_w }, 'o' },
16610
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16707
16611
{ { OPERAND_pr }, 'i' },
16708
-
{ { OPERAND_qr0 }, 'i' },
16612
+
{ { OPERAND_mac_qr0 }, 'i' },
16709
16613
{ { OPERAND_pr0 }, 'i' }
16710
16614
};
16711
16615
···
16714
16618
};
16715
16619
16716
16620
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
16717
-
{ { OPERAND_qr1_w }, 'o' },
16718
-
{ { OPERAND_qr0_rw }, 'i' },
16621
+
{ { OPERAND_mac_qr1_w }, 'o' },
16622
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16719
16623
{ { OPERAND_pr }, 'i' },
16720
-
{ { OPERAND_qr0 }, 'i' },
16624
+
{ { OPERAND_mac_qr0 }, 'i' },
16721
16625
{ { OPERAND_pr0 }, 'i' }
16722
16626
};
16723
16627
···
16726
16630
};
16727
16631
16728
16632
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
16729
-
{ { OPERAND_qr1_w }, 'o' },
16730
-
{ { OPERAND_qr0_rw }, 'i' },
16633
+
{ { OPERAND_mac_qr1_w }, 'o' },
16634
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16731
16635
{ { OPERAND_pr }, 'i' },
16732
-
{ { OPERAND_qr0 }, 'i' },
16636
+
{ { OPERAND_mac_qr0 }, 'i' },
16733
16637
{ { OPERAND_pr0 }, 'i' }
16734
16638
};
16735
16639
···
16738
16642
};
16739
16643
16740
16644
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
16741
-
{ { OPERAND_qr1_w }, 'o' },
16742
-
{ { OPERAND_qr0_rw }, 'i' },
16645
+
{ { OPERAND_mac_qr1_w }, 'o' },
16646
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16743
16647
{ { OPERAND_pr }, 'i' },
16744
-
{ { OPERAND_qr0 }, 'i' },
16648
+
{ { OPERAND_mac_qr0 }, 'i' },
16745
16649
{ { OPERAND_pr0 }, 'i' }
16746
16650
};
16747
16651
···
16750
16654
};
16751
16655
16752
16656
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
16753
-
{ { OPERAND_qr1_w }, 'o' },
16754
-
{ { OPERAND_qr0_rw }, 'i' },
16657
+
{ { OPERAND_mac_qr1_w }, 'o' },
16658
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16755
16659
{ { OPERAND_pr }, 'i' },
16756
-
{ { OPERAND_qr0 }, 'i' },
16660
+
{ { OPERAND_mac_qr0 }, 'i' },
16757
16661
{ { OPERAND_pr0 }, 'i' }
16758
16662
};
16759
16663
···
16762
16666
};
16763
16667
16764
16668
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
16765
-
{ { OPERAND_qr1_w }, 'o' },
16766
-
{ { OPERAND_qr0_rw }, 'i' },
16669
+
{ { OPERAND_mac_qr1_w }, 'o' },
16670
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16767
16671
{ { OPERAND_pr }, 'i' },
16768
-
{ { OPERAND_qr0 }, 'i' },
16672
+
{ { OPERAND_mac_qr0 }, 'i' },
16769
16673
{ { OPERAND_pr0 }, 'i' }
16770
16674
};
16771
16675
···
16774
16678
};
16775
16679
16776
16680
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
16777
-
{ { OPERAND_qr1_w }, 'o' },
16778
-
{ { OPERAND_qr0_rw }, 'i' },
16681
+
{ { OPERAND_mac_qr1_w }, 'o' },
16682
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16779
16683
{ { OPERAND_pr }, 'i' },
16780
-
{ { OPERAND_qr0 }, 'i' },
16684
+
{ { OPERAND_mac_qr0 }, 'i' },
16781
16685
{ { OPERAND_pr0 }, 'i' }
16782
16686
};
16783
16687
···
16786
16690
};
16787
16691
16788
16692
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
16789
-
{ { OPERAND_qr1_w }, 'o' },
16790
-
{ { OPERAND_qr0_rw }, 'i' },
16693
+
{ { OPERAND_mac_qr1_w }, 'o' },
16694
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16791
16695
{ { OPERAND_pr }, 'i' },
16792
-
{ { OPERAND_qr0 }, 'i' },
16696
+
{ { OPERAND_mac_qr0 }, 'i' },
16793
16697
{ { OPERAND_pr0 }, 'i' }
16794
16698
};
16795
16699
···
16798
16702
};
16799
16703
16800
16704
static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
16801
-
{ { OPERAND_qr1_w }, 'o' },
16802
-
{ { OPERAND_qr0_rw }, 'i' },
16705
+
{ { OPERAND_mac_qr1_w }, 'o' },
16706
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16803
16707
{ { OPERAND_pr }, 'i' },
16804
-
{ { OPERAND_qr0 }, 'i' },
16708
+
{ { OPERAND_mac_qr0 }, 'i' },
16805
16709
{ { OPERAND_pr0 }, 'i' }
16806
16710
};
16807
16711
···
16810
16714
};
16811
16715
16812
16716
static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
16813
-
{ { OPERAND_qr1_w }, 'o' },
16814
-
{ { OPERAND_qr0_rw }, 'i' },
16717
+
{ { OPERAND_mac_qr1_w }, 'o' },
16718
+
{ { OPERAND_mac_qr0_rw }, 'i' },
16815
16719
{ { OPERAND_pr }, 'i' },
16816
-
{ { OPERAND_qr0 }, 'i' },
16720
+
{ { OPERAND_mac_qr0 }, 'i' },
16817
16721
{ { OPERAND_pr0 }, 'i' }
16818
16722
};
16819
16723
···
16822
16726
};
16823
16727
16824
16728
static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
16825
-
{ { OPERAND_qr1_w }, 'o' },
16729
+
{ { OPERAND_mac_qr1_w }, 'o' },
16826
16730
{ { OPERAND_pr }, 'i' },
16827
16731
{ { OPERAND_pr0 }, 'i' }
16828
16732
};
···
16832
16736
};
16833
16737
16834
16738
static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
16835
-
{ { OPERAND_qr1_w }, 'o' },
16739
+
{ { OPERAND_mac_qr1_w }, 'o' },
16836
16740
{ { OPERAND_pr }, 'i' },
16837
16741
{ { OPERAND_pr0 }, 'i' }
16838
16742
};
···
16842
16746
};
16843
16747
16844
16748
static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
16845
-
{ { OPERAND_qr1_w }, 'o' },
16749
+
{ { OPERAND_mac_qr1_w }, 'o' },
16846
16750
{ { OPERAND_pr }, 'i' },
16847
16751
{ { OPERAND_pr0 }, 'i' }
16848
16752
};
···
16852
16756
};
16853
16757
16854
16758
static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
16855
-
{ { OPERAND_qr1_w }, 'o' },
16759
+
{ { OPERAND_mac_qr1_w }, 'o' },
16856
16760
{ { OPERAND_pr }, 'i' },
16857
16761
{ { OPERAND_pr0 }, 'i' }
16858
16762
};
···
16862
16766
};
16863
16767
16864
16768
static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
16865
-
{ { OPERAND_qr1_w }, 'o' },
16769
+
{ { OPERAND_mac_qr1_w }, 'o' },
16866
16770
{ { OPERAND_pr }, 'i' },
16867
16771
{ { OPERAND_pr0 }, 'i' }
16868
16772
};
···
16872
16776
};
16873
16777
16874
16778
static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
16875
-
{ { OPERAND_qr1_w }, 'o' },
16779
+
{ { OPERAND_mac_qr1_w }, 'o' },
16876
16780
{ { OPERAND_pr }, 'i' },
16877
16781
{ { OPERAND_pr0 }, 'i' }
16878
16782
};
···
16882
16786
};
16883
16787
16884
16788
static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
16885
-
{ { OPERAND_qr1_w }, 'o' },
16789
+
{ { OPERAND_mac_qr1_w }, 'o' },
16886
16790
{ { OPERAND_pr }, 'i' },
16887
16791
{ { OPERAND_pr0 }, 'i' }
16888
16792
};
···
16892
16796
};
16893
16797
16894
16798
static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
16895
-
{ { OPERAND_qr1_w }, 'o' },
16799
+
{ { OPERAND_mac_qr1_w }, 'o' },
16896
16800
{ { OPERAND_pr }, 'i' },
16897
16801
{ { OPERAND_pr0 }, 'i' }
16898
16802
};
···
16902
16806
};
16903
16807
16904
16808
static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
16905
-
{ { OPERAND_qr1_w }, 'o' },
16809
+
{ { OPERAND_mac_qr1_w }, 'o' },
16906
16810
{ { OPERAND_pr }, 'i' },
16907
16811
{ { OPERAND_pr0 }, 'i' }
16908
16812
};
···
16912
16816
};
16913
16817
16914
16818
static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
16915
-
{ { OPERAND_qr1_w }, 'o' },
16819
+
{ { OPERAND_mac_qr1_w }, 'o' },
16916
16820
{ { OPERAND_pr }, 'i' },
16917
16821
{ { OPERAND_pr0 }, 'i' }
16918
16822
};
···
16922
16826
};
16923
16827
16924
16828
static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
16925
-
{ { OPERAND_qr1_w }, 'o' },
16829
+
{ { OPERAND_mac_qr1_w }, 'o' },
16926
16830
{ { OPERAND_pr }, 'i' },
16927
16831
{ { OPERAND_pr0 }, 'i' }
16928
16832
};
···
16932
16836
};
16933
16837
16934
16838
static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
16935
-
{ { OPERAND_qr1_w }, 'o' },
16839
+
{ { OPERAND_mac_qr1_w }, 'o' },
16936
16840
{ { OPERAND_pr }, 'i' },
16937
16841
{ { OPERAND_pr0 }, 'i' }
16938
16842
};
···
16942
16846
};
16943
16847
16944
16848
static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
16945
-
{ { OPERAND_qr1_w }, 'o' },
16849
+
{ { OPERAND_mac_qr1_w }, 'o' },
16946
16850
{ { OPERAND_pr }, 'i' },
16947
16851
{ { OPERAND_pr0 }, 'i' }
16948
16852
};
···
16952
16856
};
16953
16857
16954
16858
static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
16955
-
{ { OPERAND_qr1_w }, 'o' },
16859
+
{ { OPERAND_mac_qr1_w }, 'o' },
16956
16860
{ { OPERAND_pr }, 'i' },
16957
16861
{ { OPERAND_pr0 }, 'i' }
16958
16862
};
···
16962
16866
};
16963
16867
16964
16868
static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
16965
-
{ { OPERAND_qr1_w }, 'o' },
16869
+
{ { OPERAND_mac_qr1_w }, 'o' },
16966
16870
{ { OPERAND_pr }, 'i' },
16967
16871
{ { OPERAND_pr0 }, 'i' }
16968
16872
};
···
16972
16876
};
16973
16877
16974
16878
static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
16975
-
{ { OPERAND_qr1_w }, 'o' },
16879
+
{ { OPERAND_mac_qr1_w }, 'o' },
16976
16880
{ { OPERAND_pr }, 'i' },
16977
16881
{ { OPERAND_pr0 }, 'i' }
16978
16882
};
···
16982
16886
};
16983
16887
16984
16888
static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
16985
-
{ { OPERAND_qr1_w }, 'm' },
16889
+
{ { OPERAND_mac_qr1_w }, 'm' },
16986
16890
{ { OPERAND_pr }, 'i' },
16987
16891
{ { OPERAND_pr0 }, 'i' }
16988
16892
};
···
16992
16896
};
16993
16897
16994
16898
static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
16995
-
{ { OPERAND_qr1_w }, 'm' },
16899
+
{ { OPERAND_mac_qr1_w }, 'm' },
16996
16900
{ { OPERAND_pr }, 'i' },
16997
16901
{ { OPERAND_pr0 }, 'i' }
16998
16902
};
···
17002
16906
};
17003
16907
17004
16908
static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
17005
-
{ { OPERAND_qr1_w }, 'm' },
16909
+
{ { OPERAND_mac_qr1_w }, 'm' },
17006
16910
{ { OPERAND_pr }, 'i' },
17007
16911
{ { OPERAND_pr0 }, 'i' }
17008
16912
};
···
17012
16916
};
17013
16917
17014
16918
static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
17015
-
{ { OPERAND_qr1_w }, 'm' },
16919
+
{ { OPERAND_mac_qr1_w }, 'm' },
17016
16920
{ { OPERAND_pr }, 'i' },
17017
16921
{ { OPERAND_pr0 }, 'i' }
17018
16922
};
···
17022
16926
};
17023
16927
17024
16928
static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
17025
-
{ { OPERAND_qr1_w }, 'm' },
16929
+
{ { OPERAND_mac_qr1_w }, 'm' },
17026
16930
{ { OPERAND_pr }, 'i' },
17027
16931
{ { OPERAND_pr0 }, 'i' }
17028
16932
};
···
17032
16936
};
17033
16937
17034
16938
static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
17035
-
{ { OPERAND_qr1_w }, 'm' },
16939
+
{ { OPERAND_mac_qr1_w }, 'm' },
17036
16940
{ { OPERAND_pr }, 'i' },
17037
16941
{ { OPERAND_pr0 }, 'i' }
17038
16942
};
···
17042
16946
};
17043
16947
17044
16948
static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
17045
-
{ { OPERAND_qr1_w }, 'm' },
16949
+
{ { OPERAND_mac_qr1_w }, 'm' },
17046
16950
{ { OPERAND_pr }, 'i' },
17047
16951
{ { OPERAND_pr0 }, 'i' }
17048
16952
};
···
17052
16956
};
17053
16957
17054
16958
static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
17055
-
{ { OPERAND_qr1_w }, 'm' },
16959
+
{ { OPERAND_mac_qr1_w }, 'm' },
17056
16960
{ { OPERAND_pr }, 'i' },
17057
16961
{ { OPERAND_pr0 }, 'i' }
17058
16962
};
···
17062
16966
};
17063
16967
17064
16968
static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
17065
-
{ { OPERAND_qr1_w }, 'm' },
16969
+
{ { OPERAND_mac_qr1_w }, 'm' },
17066
16970
{ { OPERAND_pr }, 'i' },
17067
16971
{ { OPERAND_pr0 }, 'i' }
17068
16972
};
···
17072
16976
};
17073
16977
17074
16978
static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
17075
-
{ { OPERAND_qr1_w }, 'm' },
16979
+
{ { OPERAND_mac_qr1_w }, 'm' },
17076
16980
{ { OPERAND_pr }, 'i' },
17077
16981
{ { OPERAND_pr0 }, 'i' }
17078
16982
};
···
17082
16986
};
17083
16987
17084
16988
static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
17085
-
{ { OPERAND_qr1_w }, 'm' },
16989
+
{ { OPERAND_mac_qr1_w }, 'm' },
17086
16990
{ { OPERAND_pr }, 'i' },
17087
16991
{ { OPERAND_pr0 }, 'i' }
17088
16992
};
···
17092
16996
};
17093
16997
17094
16998
static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
17095
-
{ { OPERAND_qr1_w }, 'm' },
16999
+
{ { OPERAND_mac_qr1_w }, 'm' },
17096
17000
{ { OPERAND_pr }, 'i' },
17097
17001
{ { OPERAND_pr0 }, 'i' }
17098
17002
};
···
17102
17006
};
17103
17007
17104
17008
static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
17105
-
{ { OPERAND_qr1_w }, 'm' },
17009
+
{ { OPERAND_mac_qr1_w }, 'm' },
17106
17010
{ { OPERAND_pr }, 'i' },
17107
17011
{ { OPERAND_pr0 }, 'i' }
17108
17012
};
···
17112
17016
};
17113
17017
17114
17018
static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
17115
-
{ { OPERAND_qr1_w }, 'm' },
17019
+
{ { OPERAND_mac_qr1_w }, 'm' },
17116
17020
{ { OPERAND_pr }, 'i' },
17117
17021
{ { OPERAND_pr0 }, 'i' }
17118
17022
};
···
17122
17026
};
17123
17027
17124
17028
static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
17125
-
{ { OPERAND_qr1_w }, 'm' },
17029
+
{ { OPERAND_mac_qr1_w }, 'm' },
17126
17030
{ { OPERAND_pr }, 'i' },
17127
17031
{ { OPERAND_pr0 }, 'i' }
17128
17032
};
···
17132
17036
};
17133
17037
17134
17038
static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
17135
-
{ { OPERAND_qr1_w }, 'm' },
17039
+
{ { OPERAND_mac_qr1_w }, 'm' },
17136
17040
{ { OPERAND_pr }, 'i' },
17137
17041
{ { OPERAND_pr0 }, 'i' }
17138
17042
};
···
17215
17119
17216
17120
static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
17217
17121
{ { OPERAND_arr }, 'o' },
17218
-
{ { OPERAND_ae_ohba }, 'i' }
17122
+
{ { OPERAND_ae_ohba2 }, 'i' }
17219
17123
};
17220
17124
17221
17125
static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
···
17239
17143
static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
17240
17144
{ { OPERAND_arr }, 'o' },
17241
17145
{ { OPERAND_ars }, 'i' },
17242
-
{ { OPERAND_ae_ohba }, 'i' }
17146
+
{ { OPERAND_ae_ohba2 }, 'i' }
17243
17147
};
17244
17148
17245
17149
static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
···
17349
17253
3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
17350
17254
{ 0, 0 /* xt_iclass_syscall */,
17351
17255
0, 0, 0, 0 },
17352
-
{ 0, 0 /* xt_iclass_simcall */,
17353
-
0, 0, 0, 0 },
17354
17256
{ 2, Iclass_xt_iclass_call12_args,
17355
17257
1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
17356
17258
{ 2, Iclass_xt_iclass_call8_args,
···
17467
17369
0, 0, 0, 0 },
17468
17370
{ 1, Iclass_xt_iclass_return_args,
17469
17371
0, 0, 0, 0 },
17372
+
{ 0, 0 /* xt_iclass_simcall */,
17373
+
0, 0, 0, 0 },
17470
17374
{ 3, Iclass_xt_iclass_s16i_args,
17471
17375
0, 0, 0, 0 },
17472
17376
{ 3, Iclass_xt_iclass_s32i_args,
···
17529
17433
2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
17530
17434
{ 1, Iclass_xt_iclass_xsr_litbase_args,
17531
17435
2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
17532
-
{ 1, Iclass_xt_iclass_rsr_176_args,
17533
-
2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
17534
-
{ 1, Iclass_xt_iclass_wsr_176_args,
17535
-
2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
17536
-
{ 1, Iclass_xt_iclass_rsr_208_args,
17537
-
2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
17436
+
{ 1, Iclass_xt_iclass_rsr_configid0_args,
17437
+
2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
17438
+
{ 1, Iclass_xt_iclass_wsr_configid0_args,
17439
+
2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
17440
+
{ 1, Iclass_xt_iclass_rsr_configid1_args,
17441
+
2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
17538
17442
{ 1, Iclass_xt_iclass_rsr_ps_args,
17539
17443
7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
17540
17444
{ 1, Iclass_xt_iclass_wsr_ps_args,
···
18524
18428
ICLASS_xt_iclass_rfe,
18525
18429
ICLASS_xt_iclass_rfde,
18526
18430
ICLASS_xt_iclass_syscall,
18527
-
ICLASS_xt_iclass_simcall,
18528
18431
ICLASS_xt_iclass_call12,
18529
18432
ICLASS_xt_iclass_call8,
18530
18433
ICLASS_xt_iclass_call4,
···
18583
18486
ICLASS_xt_iclass_neg,
18584
18487
ICLASS_xt_iclass_nop,
18585
18488
ICLASS_xt_iclass_return,
18489
+
ICLASS_xt_iclass_simcall,
18586
18490
ICLASS_xt_iclass_s16i,
18587
18491
ICLASS_xt_iclass_s32i,
18588
18492
ICLASS_xt_iclass_s8i,
···
18614
18518
ICLASS_xt_iclass_rsr_litbase,
18615
18519
ICLASS_xt_iclass_wsr_litbase,
18616
18520
ICLASS_xt_iclass_xsr_litbase,
18617
-
ICLASS_xt_iclass_rsr_176,
18618
-
ICLASS_xt_iclass_wsr_176,
18619
-
ICLASS_xt_iclass_rsr_208,
18521
+
ICLASS_xt_iclass_rsr_configid0,
18522
+
ICLASS_xt_iclass_wsr_configid0,
18523
+
ICLASS_xt_iclass_rsr_configid1,
18620
18524
ICLASS_xt_iclass_rsr_ps,
18621
18525
ICLASS_xt_iclass_wsr_ps,
18622
18526
ICLASS_xt_iclass_xsr_ps,
···
19138
19042
}
19139
19043
19140
19044
static void
19141
-
Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19142
-
{
19143
-
slotbuf[0] = 0x5100;
19144
-
}
19145
-
19146
-
static void
19147
19045
Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
19148
19046
{
19149
19047
slotbuf[0] = 0x35;
···
20032
19930
}
20033
19931
20034
19932
static void
19933
+
Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
19934
+
{
19935
+
slotbuf[0] = 0x5100;
19936
+
}
19937
+
19938
+
static void
20035
19939
Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
20036
19940
{
20037
19941
slotbuf[0] = 0x5002;
···
20344
20248
}
20345
20249
20346
20250
static void
20347
-
Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
20251
+
Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20348
20252
{
20349
20253
slotbuf[0] = 0x3b000;
20350
20254
}
20351
20255
20352
20256
static void
20353
-
Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
20257
+
Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
20354
20258
{
20355
20259
slotbuf[0] = 0x13b000;
20356
20260
}
20357
20261
20358
20262
static void
20359
-
Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
20263
+
Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
20360
20264
{
20361
20265
slotbuf[0] = 0x3d000;
20362
20266
}
···
24175
24079
Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
24176
24080
};
24177
24081
24178
-
static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
24179
-
Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
24180
-
};
24181
-
24182
24082
static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
24183
24083
Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
24184
24084
};
···
24555
24455
Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
24556
24456
};
24557
24457
24458
+
static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
24459
+
Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
24460
+
};
24461
+
24558
24462
static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
24559
24463
Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
24560
24464
};
···
24703
24607
Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
24704
24608
};
24705
24609
24706
-
static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
24707
-
Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0
24610
+
static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
24611
+
Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
24708
24612
};
24709
24613
24710
-
static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
24711
-
Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0
24614
+
static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
24615
+
Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
24712
24616
};
24713
24617
24714
-
static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
24715
-
Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0
24618
+
static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
24619
+
Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
24716
24620
};
24717
24621
24718
24622
static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
···
26873
26777
{ "syscall", ICLASS_xt_iclass_syscall,
26874
26778
0,
26875
26779
Opcode_syscall_encode_fns, 0, 0 },
26876
-
{ "simcall", ICLASS_xt_iclass_simcall,
26877
-
0,
26878
-
Opcode_simcall_encode_fns, 0, 0 },
26879
26780
{ "call12", ICLASS_xt_iclass_call12,
26880
26781
XTENSA_OPCODE_IS_CALL,
26881
26782
Opcode_call12_encode_fns, 0, 0 },
···
27158
27059
{ "ret", ICLASS_xt_iclass_return,
27159
27060
XTENSA_OPCODE_IS_JUMP,
27160
27061
Opcode_ret_encode_fns, 0, 0 },
27062
+
{ "simcall", ICLASS_xt_iclass_simcall,
27063
+
0,
27064
+
Opcode_simcall_encode_fns, 0, 0 },
27161
27065
{ "s16i", ICLASS_xt_iclass_s16i,
27162
27066
0,
27163
27067
Opcode_s16i_encode_fns, 0, 0 },
···
27269
27173
{ "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
27270
27174
0,
27271
27175
Opcode_xsr_litbase_encode_fns, 0, 0 },
27272
-
{ "rsr.176", ICLASS_xt_iclass_rsr_176,
27176
+
{ "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
27273
27177
0,
27274
-
Opcode_rsr_176_encode_fns, 0, 0 },
27275
-
{ "wsr.176", ICLASS_xt_iclass_wsr_176,
27178
+
Opcode_rsr_configid0_encode_fns, 0, 0 },
27179
+
{ "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
27276
27180
0,
27277
-
Opcode_wsr_176_encode_fns, 0, 0 },
27278
-
{ "rsr.208", ICLASS_xt_iclass_rsr_208,
27181
+
Opcode_wsr_configid0_encode_fns, 0, 0 },
27182
+
{ "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
27279
27183
0,
27280
-
Opcode_rsr_208_encode_fns, 0, 0 },
27184
+
Opcode_rsr_configid1_encode_fns, 0, 0 },
27281
27185
{ "rsr.ps", ICLASS_xt_iclass_rsr_ps,
27282
27186
0,
27283
27187
Opcode_rsr_ps_encode_fns, 0, 0 },
···
28836
28740
OPCODE_RFE,
28837
28741
OPCODE_RFDE,
28838
28742
OPCODE_SYSCALL,
28839
-
OPCODE_SIMCALL,
28840
28743
OPCODE_CALL12,
28841
28744
OPCODE_CALL8,
28842
28745
OPCODE_CALL4,
···
28931
28834
OPCODE_ABS,
28932
28835
OPCODE_NOP,
28933
28836
OPCODE_RET,
28837
+
OPCODE_SIMCALL,
28934
28838
OPCODE_S16I,
28935
28839
OPCODE_S32I,
28936
28840
OPCODE_S8I,
···
28968
28872
OPCODE_RSR_LITBASE,
28969
28873
OPCODE_WSR_LITBASE,
28970
28874
OPCODE_XSR_LITBASE,
28971
-
OPCODE_RSR_176,
28972
-
OPCODE_WSR_176,
28973
-
OPCODE_RSR_208,
28875
+
OPCODE_RSR_CONFIGID0,
28876
+
OPCODE_WSR_CONFIGID0,
28877
+
OPCODE_RSR_CONFIGID1,
28974
28878
OPCODE_RSR_PS,
28975
28879
OPCODE_WSR_PS,
28976
28880
OPCODE_XSR_PS,
···
29496
29400
static int
29497
29401
Slot_inst_decode (const xtensa_insnbuf insn)
29498
29402
{
29499
-
switch (Field_op0_Slot_inst_get (insn))
29403
+
if (Field_op0_Slot_inst_get (insn) == 0)
29500
29404
{
29501
-
case 0:
29502
-
switch (Field_op1_Slot_inst_get (insn))
29405
+
if (Field_op1_Slot_inst_get (insn) == 0)
29503
29406
{
29504
-
case 0:
29505
-
switch (Field_op2_Slot_inst_get (insn))
29407
+
if (Field_op2_Slot_inst_get (insn) == 0)
29506
29408
{
29507
-
case 0:
29508
-
switch (Field_r_Slot_inst_get (insn))
29409
+
if (Field_r_Slot_inst_get (insn) == 0)
29509
29410
{
29510
-
case 0:
29511
-
switch (Field_m_Slot_inst_get (insn))
29411
+
if (Field_m_Slot_inst_get (insn) == 0 &&
29412
+
Field_s_Slot_inst_get (insn) == 0 &&
29413
+
Field_n_Slot_inst_get (insn) == 0)
29414
+
return OPCODE_ILL;
29415
+
if (Field_m_Slot_inst_get (insn) == 2)
29512
29416
{
29513
-
case 0:
29514
-
if (Field_s_Slot_inst_get (insn) == 0 &&
29515
-
Field_n_Slot_inst_get (insn) == 0)
29516
-
return OPCODE_ILL;
29517
-
break;
29518
-
case 2:
29519
-
switch (Field_n_Slot_inst_get (insn))
29520
-
{
29521
-
case 0:
29522
-
return OPCODE_RET;
29523
-
case 1:
29524
-
return OPCODE_RETW;
29525
-
case 2:
29526
-
return OPCODE_JX;
29527
-
}
29528
-
break;
29529
-
case 3:
29530
-
switch (Field_n_Slot_inst_get (insn))
29531
-
{
29532
-
case 0:
29533
-
return OPCODE_CALLX0;
29534
-
case 1:
29535
-
return OPCODE_CALLX4;
29536
-
case 2:
29537
-
return OPCODE_CALLX8;
29538
-
case 3:
29539
-
return OPCODE_CALLX12;
29540
-
}
29541
-
break;
29417
+
if (Field_n_Slot_inst_get (insn) == 0)
29418
+
return OPCODE_RET;
29419
+
if (Field_n_Slot_inst_get (insn) == 1)
29420
+
return OPCODE_RETW;
29421
+
if (Field_n_Slot_inst_get (insn) == 2)
29422
+
return OPCODE_JX;
29542
29423
}
29543
-
break;
29544
-
case 1:
29545
-
return OPCODE_MOVSP;
29546
-
case 2:
29547
-
if (Field_s_Slot_inst_get (insn) == 0)
29424
+
if (Field_m_Slot_inst_get (insn) == 3)
29548
29425
{
29549
-
switch (Field_t_Slot_inst_get (insn))
29550
-
{
29551
-
case 0:
29552
-
return OPCODE_ISYNC;
29553
-
case 1:
29554
-
return OPCODE_RSYNC;
29555
-
case 2:
29556
-
return OPCODE_ESYNC;
29557
-
case 3:
29558
-
return OPCODE_DSYNC;
29559
-
case 8:
29560
-
return OPCODE_EXCW;
29561
-
case 12:
29562
-
return OPCODE_MEMW;
29563
-
case 13:
29564
-
return OPCODE_EXTW;
29565
-
case 15:
29566
-
return OPCODE_NOP;
29567
-
}
29426
+
if (Field_n_Slot_inst_get (insn) == 0)
29427
+
return OPCODE_CALLX0;
29428
+
if (Field_n_Slot_inst_get (insn) == 1)
29429
+
return OPCODE_CALLX4;
29430
+
if (Field_n_Slot_inst_get (insn) == 2)
29431
+
return OPCODE_CALLX8;
29432
+
if (Field_n_Slot_inst_get (insn) == 3)
29433
+
return OPCODE_CALLX12;
29568
29434
}
29569
-
break;
29570
-
case 3:
29571
-
switch (Field_t_Slot_inst_get (insn))
29435
+
}
29436
+
if (Field_r_Slot_inst_get (insn) == 1)
29437
+
return OPCODE_MOVSP;
29438
+
if (Field_r_Slot_inst_get (insn) == 2)
29439
+
{
29440
+
if (Field_s_Slot_inst_get (insn) == 0)
29572
29441
{
29573
-
case 0:
29574
-
switch (Field_s_Slot_inst_get (insn))
29575
-
{
29576
-
case 0:
29577
-
return OPCODE_RFE;
29578
-
case 2:
29579
-
return OPCODE_RFDE;
29580
-
case 4:
29581
-
return OPCODE_RFWO;
29582
-
case 5:
29583
-
return OPCODE_RFWU;
29584
-
}
29585
-
break;
29586
-
case 1:
29587
-
return OPCODE_RFI;
29588
-
}
29589
-
break;
29590
-
case 4:
29591
-
return OPCODE_BREAK;
29592
-
case 5:
29593
-
switch (Field_s_Slot_inst_get (insn))
29594
-
{
29595
-
case 0:
29596
29442
if (Field_t_Slot_inst_get (insn) == 0)
29597
-
return OPCODE_SYSCALL;
29598
-
break;
29599
-
case 1:
29600
-
if (Field_t_Slot_inst_get (insn) == 0)
29601
-
return OPCODE_SIMCALL;
29602
-
break;
29443
+
return OPCODE_ISYNC;
29444
+
if (Field_t_Slot_inst_get (insn) == 1)
29445
+
return OPCODE_RSYNC;
29446
+
if (Field_t_Slot_inst_get (insn) == 2)
29447
+
return OPCODE_ESYNC;
29448
+
if (Field_t_Slot_inst_get (insn) == 3)
29449
+
return OPCODE_DSYNC;
29450
+
if (Field_t_Slot_inst_get (insn) == 8)
29451
+
return OPCODE_EXCW;
29452
+
if (Field_t_Slot_inst_get (insn) == 12)
29453
+
return OPCODE_MEMW;
29454
+
if (Field_t_Slot_inst_get (insn) == 13)
29455
+
return OPCODE_EXTW;
29456
+
if (Field_t_Slot_inst_get (insn) == 15)
29457
+
return OPCODE_NOP;
29603
29458
}
29604
-
break;
29605
-
case 6:
29606
-
return OPCODE_RSIL;
29607
-
case 7:
29608
-
if (Field_t_Slot_inst_get (insn) == 0)
29609
-
return OPCODE_WAITI;
29610
-
break;
29611
-
case 8:
29612
-
return OPCODE_ANY4;
29613
-
case 9:
29614
-
return OPCODE_ALL4;
29615
-
case 10:
29616
-
return OPCODE_ANY8;
29617
-
case 11:
29618
-
return OPCODE_ALL8;
29619
29459
}
29620
-
break;
29621
-
case 1:
29622
-
return OPCODE_AND;
29623
-
case 2:
29624
-
return OPCODE_OR;
29625
-
case 3:
29626
-
return OPCODE_XOR;
29627
-
case 4:
29628
-
switch (Field_r_Slot_inst_get (insn))
29460
+
if (Field_r_Slot_inst_get (insn) == 3)
29629
29461
{
29630
-
case 0:
29631
29462
if (Field_t_Slot_inst_get (insn) == 0)
29632
-
return OPCODE_SSR;
29633
-
break;
29634
-
case 1:
29635
-
if (Field_t_Slot_inst_get (insn) == 0)
29636
-
return OPCODE_SSL;
29637
-
break;
29638
-
case 2:
29639
-
if (Field_t_Slot_inst_get (insn) == 0)
29640
-
return OPCODE_SSA8L;
29641
-
break;
29642
-
case 3:
29643
-
if (Field_t_Slot_inst_get (insn) == 0)
29644
-
return OPCODE_SSA8B;
29645
-
break;
29646
-
case 4:
29647
-
if (Field_thi3_Slot_inst_get (insn) == 0)
29648
-
return OPCODE_SSAI;
29649
-
break;
29650
-
case 6:
29651
-
return OPCODE_RER;
29652
-
case 7:
29653
-
return OPCODE_WER;
29654
-
case 8:
29655
-
if (Field_s_Slot_inst_get (insn) == 0)
29656
-
return OPCODE_ROTW;
29657
-
break;
29658
-
case 14:
29659
-
return OPCODE_NSA;
29660
-
case 15:
29661
-
return OPCODE_NSAU;
29463
+
{
29464
+
if (Field_s_Slot_inst_get (insn) == 0)
29465
+
return OPCODE_RFE;
29466
+
if (Field_s_Slot_inst_get (insn) == 2)
29467
+
return OPCODE_RFDE;
29468
+
if (Field_s_Slot_inst_get (insn) == 4)
29469
+
return OPCODE_RFWO;
29470
+
if (Field_s_Slot_inst_get (insn) == 5)
29471
+
return OPCODE_RFWU;
29472
+
}
29473
+
if (Field_t_Slot_inst_get (insn) == 1)
29474
+
return OPCODE_RFI;
29662
29475
}
29663
-
break;
29664
-
case 5:
29665
-
switch (Field_r_Slot_inst_get (insn))
29666
-
{
29667
-
case 1:
29668
-
return OPCODE_HWWITLBA;
29669
-
case 3:
29670
-
return OPCODE_RITLB0;
29671
-
case 4:
29672
-
if (Field_t_Slot_inst_get (insn) == 0)
29673
-
return OPCODE_IITLB;
29674
-
break;
29675
-
case 5:
29676
-
return OPCODE_PITLB;
29677
-
case 6:
29678
-
return OPCODE_WITLB;
29679
-
case 7:
29680
-
return OPCODE_RITLB1;
29681
-
case 9:
29682
-
return OPCODE_HWWDTLBA;
29683
-
case 11:
29684
-
return OPCODE_RDTLB0;
29685
-
case 12:
29686
-
if (Field_t_Slot_inst_get (insn) == 0)
29687
-
return OPCODE_IDTLB;
29688
-
break;
29689
-
case 13:
29690
-
return OPCODE_PDTLB;
29691
-
case 14:
29692
-
return OPCODE_WDTLB;
29693
-
case 15:
29694
-
return OPCODE_RDTLB1;
29695
-
}
29696
-
break;
29697
-
case 6:
29698
-
switch (Field_s_Slot_inst_get (insn))
29699
-
{
29700
-
case 0:
29701
-
return OPCODE_NEG;
29702
-
case 1:
29703
-
return OPCODE_ABS;
29704
-
}
29705
-
break;
29706
-
case 8:
29707
-
return OPCODE_ADD;
29708
-
case 9:
29709
-
return OPCODE_ADDX2;
29710
-
case 10:
29711
-
return OPCODE_ADDX4;
29712
-
case 11:
29713
-
return OPCODE_ADDX8;
29714
-
case 12:
29715
-
return OPCODE_SUB;
29716
-
case 13:
29717
-
return OPCODE_SUBX2;
29718
-
case 14:
29719
-
return OPCODE_SUBX4;
29720
-
case 15:
29721
-
return OPCODE_SUBX8;
29722
-
}
29723
-
break;
29724
-
case 1:
29725
-
switch (Field_op2_Slot_inst_get (insn))
29726
-
{
29727
-
case 0:
29728
-
case 1:
29729
-
return OPCODE_SLLI;
29730
-
case 2:
29731
-
case 3:
29732
-
return OPCODE_SRAI;
29733
-
case 4:
29734
-
return OPCODE_SRLI;
29735
-
case 6:
29736
-
switch (Field_sr_Slot_inst_get (insn))
29737
-
{
29738
-
case 0:
29739
-
return OPCODE_XSR_LBEG;
29740
-
case 1:
29741
-
return OPCODE_XSR_LEND;
29742
-
case 2:
29743
-
return OPCODE_XSR_LCOUNT;
29744
-
case 3:
29745
-
return OPCODE_XSR_SAR;
29746
-
case 4:
29747
-
return OPCODE_XSR_BR;
29748
-
case 5:
29749
-
return OPCODE_XSR_LITBASE;
29750
-
case 12:
29751
-
return OPCODE_XSR_SCOMPARE1;
29752
-
case 72:
29753
-
return OPCODE_XSR_WINDOWBASE;
29754
-
case 73:
29755
-
return OPCODE_XSR_WINDOWSTART;
29756
-
case 83:
29757
-
return OPCODE_XSR_PTEVADDR;
29758
-
case 90:
29759
-
return OPCODE_XSR_RASID;
29760
-
case 91:
29761
-
return OPCODE_XSR_ITLBCFG;
29762
-
case 92:
29763
-
return OPCODE_XSR_DTLBCFG;
29764
-
case 99:
29765
-
return OPCODE_XSR_ATOMCTL;
29766
-
case 104:
29767
-
return OPCODE_XSR_DDR;
29768
-
case 177:
29769
-
return OPCODE_XSR_EPC1;
29770
-
case 178:
29771
-
return OPCODE_XSR_EPC2;
29772
-
case 192:
29773
-
return OPCODE_XSR_DEPC;
29774
-
case 194:
29775
-
return OPCODE_XSR_EPS2;
29776
-
case 209:
29777
-
return OPCODE_XSR_EXCSAVE1;
29778
-
case 210:
29779
-
return OPCODE_XSR_EXCSAVE2;
29780
-
case 224:
29781
-
return OPCODE_XSR_CPENABLE;
29782
-
case 228:
29783
-
return OPCODE_XSR_INTENABLE;
29784
-
case 230:
29785
-
return OPCODE_XSR_PS;
29786
-
case 231:
29787
-
return OPCODE_XSR_VECBASE;
29788
-
case 232:
29789
-
return OPCODE_XSR_EXCCAUSE;
29790
-
case 233:
29791
-
return OPCODE_XSR_DEBUGCAUSE;
29792
-
case 234:
29793
-
return OPCODE_XSR_CCOUNT;
29794
-
case 236:
29795
-
return OPCODE_XSR_ICOUNT;
29796
-
case 237:
29797
-
return OPCODE_XSR_ICOUNTLEVEL;
29798
-
case 238:
29799
-
return OPCODE_XSR_EXCVADDR;
29800
-
case 240:
29801
-
return OPCODE_XSR_CCOMPARE0;
29802
-
case 241:
29803
-
return OPCODE_XSR_CCOMPARE1;
29804
-
case 244:
29805
-
return OPCODE_XSR_MISC0;
29806
-
case 245:
29807
-
return OPCODE_XSR_MISC1;
29808
-
}
29809
-
break;
29810
-
case 8:
29811
-
return OPCODE_SRC;
29812
-
case 9:
29813
-
if (Field_s_Slot_inst_get (insn) == 0)
29814
-
return OPCODE_SRL;
29815
-
break;
29816
-
case 10:
29817
-
if (Field_t_Slot_inst_get (insn) == 0)
29818
-
return OPCODE_SLL;
29819
-
break;
29820
-
case 11:
29821
-
if (Field_s_Slot_inst_get (insn) == 0)
29822
-
return OPCODE_SRA;
29823
-
break;
29824
-
case 12:
29825
-
return OPCODE_MUL16U;
29826
-
case 13:
29827
-
return OPCODE_MUL16S;
29828
-
case 15:
29829
-
switch (Field_r_Slot_inst_get (insn))
29476
+
if (Field_r_Slot_inst_get (insn) == 4)
29477
+
return OPCODE_BREAK;
29478
+
if (Field_r_Slot_inst_get (insn) == 5)
29830
29479
{
29831
-
case 0:
29832
-
return OPCODE_LICT;
29833
-
case 1:
29834
-
return OPCODE_SICT;
29835
-
case 2:
29836
-
return OPCODE_LICW;
29837
-
case 3:
29838
-
return OPCODE_SICW;
29839
-
case 8:
29840
-
return OPCODE_LDCT;
29841
-
case 9:
29842
-
return OPCODE_SDCT;
29843
-
case 14:
29844
-
if (Field_t_Slot_inst_get (insn) == 0)
29845
-
return OPCODE_RFDO;
29846
-
if (Field_t_Slot_inst_get (insn) == 1)
29847
-
return OPCODE_RFDD;
29848
-
break;
29849
-
case 15:
29850
-
return OPCODE_LDPTE;
29480
+
if (Field_s_Slot_inst_get (insn) == 0 &&
29481
+
Field_t_Slot_inst_get (insn) == 0)
29482
+
return OPCODE_SYSCALL;
29483
+
if (Field_s_Slot_inst_get (insn) == 1 &&
29484
+
Field_t_Slot_inst_get (insn) == 0)
29485
+
return OPCODE_SIMCALL;
29851
29486
}
29852
-
break;
29487
+
if (Field_r_Slot_inst_get (insn) == 6)
29488
+
return OPCODE_RSIL;
29489
+
if (Field_r_Slot_inst_get (insn) == 7 &&
29490
+
Field_t_Slot_inst_get (insn) == 0)
29491
+
return OPCODE_WAITI;
29492
+
if (Field_r_Slot_inst_get (insn) == 8)
29493
+
return OPCODE_ANY4;
29494
+
if (Field_r_Slot_inst_get (insn) == 9)
29495
+
return OPCODE_ALL4;
29496
+
if (Field_r_Slot_inst_get (insn) == 10)
29497
+
return OPCODE_ANY8;
29498
+
if (Field_r_Slot_inst_get (insn) == 11)
29499
+
return OPCODE_ALL8;
29853
29500
}
29854
-
break;
29855
-
case 2:
29856
-
switch (Field_op2_Slot_inst_get (insn))
29501
+
if (Field_op2_Slot_inst_get (insn) == 1)
29502
+
return OPCODE_AND;
29503
+
if (Field_op2_Slot_inst_get (insn) == 2)
29504
+
return OPCODE_OR;
29505
+
if (Field_op2_Slot_inst_get (insn) == 3)
29506
+
return OPCODE_XOR;
29507
+
if (Field_op2_Slot_inst_get (insn) == 4)
29857
29508
{
29858
-
case 0:
29859
-
return OPCODE_ANDB;
29860
-
case 1:
29861
-
return OPCODE_ANDBC;
29862
-
case 2:
29863
-
return OPCODE_ORB;
29864
-
case 3:
29865
-
return OPCODE_ORBC;
29866
-
case 4:
29867
-
return OPCODE_XORB;
29868
-
case 8:
29869
-
return OPCODE_MULL;
29509
+
if (Field_r_Slot_inst_get (insn) == 0 &&
29510
+
Field_t_Slot_inst_get (insn) == 0)
29511
+
return OPCODE_SSR;
29512
+
if (Field_r_Slot_inst_get (insn) == 1 &&
29513
+
Field_t_Slot_inst_get (insn) == 0)
29514
+
return OPCODE_SSL;
29515
+
if (Field_r_Slot_inst_get (insn) == 2 &&
29516
+
Field_t_Slot_inst_get (insn) == 0)
29517
+
return OPCODE_SSA8L;
29518
+
if (Field_r_Slot_inst_get (insn) == 3 &&
29519
+
Field_t_Slot_inst_get (insn) == 0)
29520
+
return OPCODE_SSA8B;
29521
+
if (Field_r_Slot_inst_get (insn) == 4 &&
29522
+
Field_thi3_Slot_inst_get (insn) == 0)
29523
+
return OPCODE_SSAI;
29524
+
if (Field_r_Slot_inst_get (insn) == 6)
29525
+
return OPCODE_RER;
29526
+
if (Field_r_Slot_inst_get (insn) == 7)
29527
+
return OPCODE_WER;
29528
+
if (Field_r_Slot_inst_get (insn) == 8 &&
29529
+
Field_s_Slot_inst_get (insn) == 0)
29530
+
return OPCODE_ROTW;
29531
+
if (Field_r_Slot_inst_get (insn) == 14)
29532
+
return OPCODE_NSA;
29533
+
if (Field_r_Slot_inst_get (insn) == 15)
29534
+
return OPCODE_NSAU;
29870
29535
}
29871
-
break;
29872
-
case 3:
29873
-
switch (Field_op2_Slot_inst_get (insn))
29536
+
if (Field_op2_Slot_inst_get (insn) == 5)
29874
29537
{
29875
-
case 0:
29876
-
switch (Field_sr_Slot_inst_get (insn))
29877
-
{
29878
-
case 0:
29879
-
return OPCODE_RSR_LBEG;
29880
-
case 1:
29881
-
return OPCODE_RSR_LEND;
29882
-
case 2:
29883
-
return OPCODE_RSR_LCOUNT;
29884
-
case 3:
29885
-
return OPCODE_RSR_SAR;
29886
-
case 4:
29887
-
return OPCODE_RSR_BR;
29888
-
case 5:
29889
-
return OPCODE_RSR_LITBASE;
29890
-
case 12:
29891
-
return OPCODE_RSR_SCOMPARE1;
29892
-
case 72:
29893
-
return OPCODE_RSR_WINDOWBASE;
29894
-
case 73:
29895
-
return OPCODE_RSR_WINDOWSTART;
29896
-
case 83:
29897
-
return OPCODE_RSR_PTEVADDR;
29898
-
case 90:
29899
-
return OPCODE_RSR_RASID;
29900
-
case 91:
29901
-
return OPCODE_RSR_ITLBCFG;
29902
-
case 92:
29903
-
return OPCODE_RSR_DTLBCFG;
29904
-
case 99:
29905
-
return OPCODE_RSR_ATOMCTL;
29906
-
case 104:
29907
-
return OPCODE_RSR_DDR;
29908
-
case 176:
29909
-
return OPCODE_RSR_176;
29910
-
case 177:
29911
-
return OPCODE_RSR_EPC1;
29912
-
case 178:
29913
-
return OPCODE_RSR_EPC2;
29914
-
case 192:
29915
-
return OPCODE_RSR_DEPC;
29916
-
case 194:
29917
-
return OPCODE_RSR_EPS2;
29918
-
case 208:
29919
-
return OPCODE_RSR_208;
29920
-
case 209:
29921
-
return OPCODE_RSR_EXCSAVE1;
29922
-
case 210:
29923
-
return OPCODE_RSR_EXCSAVE2;
29924
-
case 224:
29925
-
return OPCODE_RSR_CPENABLE;
29926
-
case 226:
29927
-
return OPCODE_RSR_INTERRUPT;
29928
-
case 228:
29929
-
return OPCODE_RSR_INTENABLE;
29930
-
case 230:
29931
-
return OPCODE_RSR_PS;
29932
-
case 231:
29933
-
return OPCODE_RSR_VECBASE;
29934
-
case 232:
29935
-
return OPCODE_RSR_EXCCAUSE;
29936
-
case 233:
29937
-
return OPCODE_RSR_DEBUGCAUSE;
29938
-
case 234:
29939
-
return OPCODE_RSR_CCOUNT;
29940
-
case 235:
29941
-
return OPCODE_RSR_PRID;
29942
-
case 236:
29943
-
return OPCODE_RSR_ICOUNT;
29944
-
case 237:
29945
-
return OPCODE_RSR_ICOUNTLEVEL;
29946
-
case 238:
29947
-
return OPCODE_RSR_EXCVADDR;
29948
-
case 240:
29949
-
return OPCODE_RSR_CCOMPARE0;
29950
-
case 241:
29951
-
return OPCODE_RSR_CCOMPARE1;
29952
-
case 244:
29953
-
return OPCODE_RSR_MISC0;
29954
-
case 245:
29955
-
return OPCODE_RSR_MISC1;
29956
-
}
29957
-
break;
29958
-
case 1:
29959
-
switch (Field_sr_Slot_inst_get (insn))
29960
-
{
29961
-
case 0:
29962
-
return OPCODE_WSR_LBEG;
29963
-
case 1:
29964
-
return OPCODE_WSR_LEND;
29965
-
case 2:
29966
-
return OPCODE_WSR_LCOUNT;
29967
-
case 3:
29968
-
return OPCODE_WSR_SAR;
29969
-
case 4:
29970
-
return OPCODE_WSR_BR;
29971
-
case 5:
29972
-
return OPCODE_WSR_LITBASE;
29973
-
case 12:
29974
-
return OPCODE_WSR_SCOMPARE1;
29975
-
case 72:
29976
-
return OPCODE_WSR_WINDOWBASE;
29977
-
case 73:
29978
-
return OPCODE_WSR_WINDOWSTART;
29979
-
case 83:
29980
-
return OPCODE_WSR_PTEVADDR;
29981
-
case 90:
29982
-
return OPCODE_WSR_RASID;
29983
-
case 91:
29984
-
return OPCODE_WSR_ITLBCFG;
29985
-
case 92:
29986
-
return OPCODE_WSR_DTLBCFG;
29987
-
case 99:
29988
-
return OPCODE_WSR_ATOMCTL;
29989
-
case 104:
29990
-
return OPCODE_WSR_DDR;
29991
-
case 176:
29992
-
return OPCODE_WSR_176;
29993
-
case 177:
29994
-
return OPCODE_WSR_EPC1;
29995
-
case 178:
29996
-
return OPCODE_WSR_EPC2;
29997
-
case 192:
29998
-
return OPCODE_WSR_DEPC;
29999
-
case 194:
30000
-
return OPCODE_WSR_EPS2;
30001
-
case 209:
30002
-
return OPCODE_WSR_EXCSAVE1;
30003
-
case 210:
30004
-
return OPCODE_WSR_EXCSAVE2;
30005
-
case 224:
30006
-
return OPCODE_WSR_CPENABLE;
30007
-
case 226:
30008
-
return OPCODE_WSR_INTSET;
30009
-
case 227:
30010
-
return OPCODE_WSR_INTCLEAR;
30011
-
case 228:
30012
-
return OPCODE_WSR_INTENABLE;
30013
-
case 230:
30014
-
return OPCODE_WSR_PS;
30015
-
case 231:
30016
-
return OPCODE_WSR_VECBASE;
30017
-
case 232:
30018
-
return OPCODE_WSR_EXCCAUSE;
30019
-
case 233:
30020
-
return OPCODE_WSR_DEBUGCAUSE;
30021
-
case 234:
30022
-
return OPCODE_WSR_CCOUNT;
30023
-
case 236:
30024
-
return OPCODE_WSR_ICOUNT;
30025
-
case 237:
30026
-
return OPCODE_WSR_ICOUNTLEVEL;
30027
-
case 238:
30028
-
return OPCODE_WSR_EXCVADDR;
30029
-
case 240:
30030
-
return OPCODE_WSR_CCOMPARE0;
30031
-
case 241:
30032
-
return OPCODE_WSR_CCOMPARE1;
30033
-
case 244:
30034
-
return OPCODE_WSR_MISC0;
30035
-
case 245:
30036
-
return OPCODE_WSR_MISC1;
30037
-
}
30038
-
break;
30039
-
case 2:
30040
-
return OPCODE_SEXT;
30041
-
case 3:
30042
-
return OPCODE_CLAMPS;
30043
-
case 4:
30044
-
return OPCODE_MIN;
30045
-
case 5:
30046
-
return OPCODE_MAX;
30047
-
case 6:
30048
-
return OPCODE_MINU;
30049
-
case 7:
30050
-
return OPCODE_MAXU;
30051
-
case 8:
30052
-
return OPCODE_MOVEQZ;
30053
-
case 9:
30054
-
return OPCODE_MOVNEZ;
30055
-
case 10:
30056
-
return OPCODE_MOVLTZ;
30057
-
case 11:
30058
-
return OPCODE_MOVGEZ;
30059
-
case 12:
30060
-
return OPCODE_MOVF;
30061
-
case 13:
30062
-
return OPCODE_MOVT;
30063
-
case 14:
30064
-
switch (Field_st_Slot_inst_get (insn))
30065
-
{
30066
-
case 231:
30067
-
return OPCODE_RUR_THREADPTR;
30068
-
case 240:
30069
-
return OPCODE_RUR_AE_OVF_SAR;
30070
-
case 241:
30071
-
return OPCODE_RUR_AE_BITHEAD;
30072
-
case 242:
30073
-
return OPCODE_RUR_AE_TS_FTS_BU_BP;
30074
-
case 243:
30075
-
return OPCODE_RUR_AE_SD_NO;
30076
-
}
30077
-
break;
30078
-
case 15:
30079
-
switch (Field_sr_Slot_inst_get (insn))
30080
-
{
30081
-
case 231:
30082
-
return OPCODE_WUR_THREADPTR;
30083
-
case 240:
30084
-
return OPCODE_WUR_AE_OVF_SAR;
30085
-
case 241:
30086
-
return OPCODE_WUR_AE_BITHEAD;
30087
-
case 242:
30088
-
return OPCODE_WUR_AE_TS_FTS_BU_BP;
30089
-
case 243:
30090
-
return OPCODE_WUR_AE_SD_NO;
30091
-
}
30092
-
break;
29538
+
if (Field_r_Slot_inst_get (insn) == 1)
29539
+
return OPCODE_HWWITLBA;
29540
+
if (Field_r_Slot_inst_get (insn) == 3)
29541
+
return OPCODE_RITLB0;
29542
+
if (Field_r_Slot_inst_get (insn) == 4 &&
29543
+
Field_t_Slot_inst_get (insn) == 0)
29544
+
return OPCODE_IITLB;
29545
+
if (Field_r_Slot_inst_get (insn) == 5)
29546
+
return OPCODE_PITLB;
29547
+
if (Field_r_Slot_inst_get (insn) == 6)
29548
+
return OPCODE_WITLB;
29549
+
if (Field_r_Slot_inst_get (insn) == 7)
29550
+
return OPCODE_RITLB1;
29551
+
if (Field_r_Slot_inst_get (insn) == 9)
29552
+
return OPCODE_HWWDTLBA;
29553
+
if (Field_r_Slot_inst_get (insn) == 11)
29554
+
return OPCODE_RDTLB0;
29555
+
if (Field_r_Slot_inst_get (insn) == 12 &&
29556
+
Field_t_Slot_inst_get (insn) == 0)
29557
+
return OPCODE_IDTLB;
29558
+
if (Field_r_Slot_inst_get (insn) == 13)
29559
+
return OPCODE_PDTLB;
29560
+
if (Field_r_Slot_inst_get (insn) == 14)
29561
+
return OPCODE_WDTLB;
29562
+
if (Field_r_Slot_inst_get (insn) == 15)
29563
+
return OPCODE_RDTLB1;
30093
29564
}
30094
-
break;
30095
-
case 4:
30096
-
case 5:
30097
-
return OPCODE_EXTUI;
30098
-
case 9:
30099
-
switch (Field_op2_Slot_inst_get (insn))
29565
+
if (Field_op2_Slot_inst_get (insn) == 6)
30100
29566
{
30101
-
case 0:
30102
-
return OPCODE_L32E;
30103
-
case 4:
30104
-
return OPCODE_S32E;
29567
+
if (Field_s_Slot_inst_get (insn) == 0)
29568
+
return OPCODE_NEG;
29569
+
if (Field_s_Slot_inst_get (insn) == 1)
29570
+
return OPCODE_ABS;
30105
29571
}
30106
-
break;
29572
+
if (Field_op2_Slot_inst_get (insn) == 8)
29573
+
return OPCODE_ADD;
29574
+
if (Field_op2_Slot_inst_get (insn) == 9)
29575
+
return OPCODE_ADDX2;
29576
+
if (Field_op2_Slot_inst_get (insn) == 10)
29577
+
return OPCODE_ADDX4;
29578
+
if (Field_op2_Slot_inst_get (insn) == 11)
29579
+
return OPCODE_ADDX8;
29580
+
if (Field_op2_Slot_inst_get (insn) == 12)
29581
+
return OPCODE_SUB;
29582
+
if (Field_op2_Slot_inst_get (insn) == 13)
29583
+
return OPCODE_SUBX2;
29584
+
if (Field_op2_Slot_inst_get (insn) == 14)
29585
+
return OPCODE_SUBX4;
29586
+
if (Field_op2_Slot_inst_get (insn) == 15)
29587
+
return OPCODE_SUBX8;
30107
29588
}
30108
-
break;
30109
-
case 1:
30110
-
return OPCODE_L32R;
30111
-
case 2:
30112
-
switch (Field_r_Slot_inst_get (insn))
29589
+
if (Field_op1_Slot_inst_get (insn) == 1)
30113
29590
{
30114
-
case 0:
30115
-
return OPCODE_L8UI;
30116
-
case 1:
30117
-
return OPCODE_L16UI;
30118
-
case 2:
30119
-
return OPCODE_L32I;
30120
-
case 4:
30121
-
return OPCODE_S8I;
30122
-
case 5:
30123
-
return OPCODE_S16I;
30124
-
case 6:
30125
-
return OPCODE_S32I;
30126
-
case 7:
30127
-
switch (Field_t_Slot_inst_get (insn))
29591
+
if ((Field_op2_Slot_inst_get (insn) == 0 ||
29592
+
Field_op2_Slot_inst_get (insn) == 1))
29593
+
return OPCODE_SLLI;
29594
+
if ((Field_op2_Slot_inst_get (insn) == 2 ||
29595
+
Field_op2_Slot_inst_get (insn) == 3))
29596
+
return OPCODE_SRAI;
29597
+
if (Field_op2_Slot_inst_get (insn) == 4)
29598
+
return OPCODE_SRLI;
29599
+
if (Field_op2_Slot_inst_get (insn) == 6)
30128
29600
{
30129
-
case 0:
30130
-
return OPCODE_DPFR;
30131
-
case 1:
30132
-
return OPCODE_DPFW;
30133
-
case 2:
30134
-
return OPCODE_DPFRO;
30135
-
case 3:
30136
-
return OPCODE_DPFWO;
30137
-
case 4:
30138
-
return OPCODE_DHWB;
30139
-
case 5:
30140
-
return OPCODE_DHWBI;
30141
-
case 6:
30142
-
return OPCODE_DHI;
30143
-
case 7:
30144
-
return OPCODE_DII;
30145
-
case 8:
30146
-
switch (Field_op1_Slot_inst_get (insn))
30147
-
{
30148
-
case 4:
30149
-
return OPCODE_DIWB;
30150
-
case 5:
30151
-
return OPCODE_DIWBI;
30152
-
}
30153
-
break;
30154
-
case 12:
30155
-
return OPCODE_IPF;
30156
-
case 14:
30157
-
return OPCODE_IHI;
30158
-
case 15:
30159
-
return OPCODE_III;
29601
+
if (Field_sr_Slot_inst_get (insn) == 0)
29602
+
return OPCODE_XSR_LBEG;
29603
+
if (Field_sr_Slot_inst_get (insn) == 1)
29604
+
return OPCODE_XSR_LEND;
29605
+
if (Field_sr_Slot_inst_get (insn) == 2)
29606
+
return OPCODE_XSR_LCOUNT;
29607
+
if (Field_sr_Slot_inst_get (insn) == 3)
29608
+
return OPCODE_XSR_SAR;
29609
+
if (Field_sr_Slot_inst_get (insn) == 4)
29610
+
return OPCODE_XSR_BR;
29611
+
if (Field_sr_Slot_inst_get (insn) == 5)
29612
+
return OPCODE_XSR_LITBASE;
29613
+
if (Field_sr_Slot_inst_get (insn) == 12)
29614
+
return OPCODE_XSR_SCOMPARE1;
29615
+
if (Field_sr_Slot_inst_get (insn) == 72)
29616
+
return OPCODE_XSR_WINDOWBASE;
29617
+
if (Field_sr_Slot_inst_get (insn) == 73)
29618
+
return OPCODE_XSR_WINDOWSTART;
29619
+
if (Field_sr_Slot_inst_get (insn) == 83)
29620
+
return OPCODE_XSR_PTEVADDR;
29621
+
if (Field_sr_Slot_inst_get (insn) == 90)
29622
+
return OPCODE_XSR_RASID;
29623
+
if (Field_sr_Slot_inst_get (insn) == 91)
29624
+
return OPCODE_XSR_ITLBCFG;
29625
+
if (Field_sr_Slot_inst_get (insn) == 92)
29626
+
return OPCODE_XSR_DTLBCFG;
29627
+
if (Field_sr_Slot_inst_get (insn) == 99)
29628
+
return OPCODE_XSR_ATOMCTL;
29629
+
if (Field_sr_Slot_inst_get (insn) == 104)
29630
+
return OPCODE_XSR_DDR;
29631
+
if (Field_sr_Slot_inst_get (insn) == 177)
29632
+
return OPCODE_XSR_EPC1;
29633
+
if (Field_sr_Slot_inst_get (insn) == 178)
29634
+
return OPCODE_XSR_EPC2;
29635
+
if (Field_sr_Slot_inst_get (insn) == 192)
29636
+
return OPCODE_XSR_DEPC;
29637
+
if (Field_sr_Slot_inst_get (insn) == 194)
29638
+
return OPCODE_XSR_EPS2;
29639
+
if (Field_sr_Slot_inst_get (insn) == 209)
29640
+
return OPCODE_XSR_EXCSAVE1;
29641
+
if (Field_sr_Slot_inst_get (insn) == 210)
29642
+
return OPCODE_XSR_EXCSAVE2;
29643
+
if (Field_sr_Slot_inst_get (insn) == 224)
29644
+
return OPCODE_XSR_CPENABLE;
29645
+
if (Field_sr_Slot_inst_get (insn) == 228)
29646
+
return OPCODE_XSR_INTENABLE;
29647
+
if (Field_sr_Slot_inst_get (insn) == 230)
29648
+
return OPCODE_XSR_PS;
29649
+
if (Field_sr_Slot_inst_get (insn) == 231)
29650
+
return OPCODE_XSR_VECBASE;
29651
+
if (Field_sr_Slot_inst_get (insn) == 232)
29652
+
return OPCODE_XSR_EXCCAUSE;
29653
+
if (Field_sr_Slot_inst_get (insn) == 233)
29654
+
return OPCODE_XSR_DEBUGCAUSE;
29655
+
if (Field_sr_Slot_inst_get (insn) == 234)
29656
+
return OPCODE_XSR_CCOUNT;
29657
+
if (Field_sr_Slot_inst_get (insn) == 236)
29658
+
return OPCODE_XSR_ICOUNT;
29659
+
if (Field_sr_Slot_inst_get (insn) == 237)
29660
+
return OPCODE_XSR_ICOUNTLEVEL;
29661
+
if (Field_sr_Slot_inst_get (insn) == 238)
29662
+
return OPCODE_XSR_EXCVADDR;
29663
+
if (Field_sr_Slot_inst_get (insn) == 240)
29664
+
return OPCODE_XSR_CCOMPARE0;
29665
+
if (Field_sr_Slot_inst_get (insn) == 241)
29666
+
return OPCODE_XSR_CCOMPARE1;
29667
+
if (Field_sr_Slot_inst_get (insn) == 244)
29668
+
return OPCODE_XSR_MISC0;
29669
+
if (Field_sr_Slot_inst_get (insn) == 245)
29670
+
return OPCODE_XSR_MISC1;
30160
29671
}
30161
-
break;
30162
-
case 9:
30163
-
return OPCODE_L16SI;
30164
-
case 10:
30165
-
return OPCODE_MOVI;
30166
-
case 11:
30167
-
return OPCODE_L32AI;
30168
-
case 12:
30169
-
return OPCODE_ADDI;
30170
-
case 13:
30171
-
return OPCODE_ADDMI;
30172
-
case 14:
30173
-
return OPCODE_S32C1I;
30174
-
case 15:
30175
-
return OPCODE_S32RI;
29672
+
if (Field_op2_Slot_inst_get (insn) == 8)
29673
+
return OPCODE_SRC;
29674
+
if (Field_op2_Slot_inst_get (insn) == 9 &&
29675
+
Field_s_Slot_inst_get (insn) == 0)
29676
+
return OPCODE_SRL;
29677
+
if (Field_op2_Slot_inst_get (insn) == 10 &&
29678
+
Field_t_Slot_inst_get (insn) == 0)
29679
+
return OPCODE_SLL;
29680
+
if (Field_op2_Slot_inst_get (insn) == 11 &&
29681
+
Field_s_Slot_inst_get (insn) == 0)
29682
+
return OPCODE_SRA;
29683
+
if (Field_op2_Slot_inst_get (insn) == 12)
29684
+
return OPCODE_MUL16U;
29685
+
if (Field_op2_Slot_inst_get (insn) == 13)
29686
+
return OPCODE_MUL16S;
29687
+
if (Field_op2_Slot_inst_get (insn) == 15)
29688
+
{
29689
+
if (Field_r_Slot_inst_get (insn) == 0)
29690
+
return OPCODE_LICT;
29691
+
if (Field_r_Slot_inst_get (insn) == 1)
29692
+
return OPCODE_SICT;
29693
+
if (Field_r_Slot_inst_get (insn) == 2)
29694
+
return OPCODE_LICW;
29695
+
if (Field_r_Slot_inst_get (insn) == 3)
29696
+
return OPCODE_SICW;
29697
+
if (Field_r_Slot_inst_get (insn) == 8)
29698
+
return OPCODE_LDCT;
29699
+
if (Field_r_Slot_inst_get (insn) == 9)
29700
+
return OPCODE_SDCT;
29701
+
if (Field_r_Slot_inst_get (insn) == 14 &&
29702
+
Field_t_Slot_inst_get (insn) == 0)
29703
+
return OPCODE_RFDO;
29704
+
if (Field_r_Slot_inst_get (insn) == 14 &&
29705
+
Field_t_Slot_inst_get (insn) == 1)
29706
+
return OPCODE_RFDD;
29707
+
if (Field_r_Slot_inst_get (insn) == 15)
29708
+
return OPCODE_LDPTE;
29709
+
}
30176
29710
}
30177
-
break;
30178
-
case 4:
30179
-
switch (Field_ae_r10_Slot_inst_get (insn))
29711
+
if (Field_op1_Slot_inst_get (insn) == 2)
30180
29712
{
30181
-
case 0:
30182
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30183
-
Field_op2_Slot_inst_get (insn) == 12)
30184
-
return OPCODE_AE_LQ56_I;
30185
-
if (Field_op1_Slot_inst_get (insn) == 2 &&
30186
-
Field_op2_Slot_inst_get (insn) == 12)
30187
-
return OPCODE_AE_LQ56_X;
30188
-
break;
30189
-
case 1:
30190
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30191
-
Field_op2_Slot_inst_get (insn) == 12)
30192
-
return OPCODE_AE_LQ32F_I;
30193
-
if (Field_op1_Slot_inst_get (insn) == 2 &&
30194
-
Field_op2_Slot_inst_get (insn) == 12)
30195
-
return OPCODE_AE_LQ32F_X;
30196
-
break;
30197
-
case 2:
30198
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30199
-
Field_op2_Slot_inst_get (insn) == 12)
30200
-
return OPCODE_AE_LQ56_IU;
30201
-
if (Field_op1_Slot_inst_get (insn) == 2 &&
30202
-
Field_op2_Slot_inst_get (insn) == 12)
30203
-
return OPCODE_AE_LQ56_XU;
30204
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30205
-
Field_t_Slot_inst_get (insn) == 3 &&
30206
-
Field_op2_Slot_inst_get (insn) == 14)
30207
-
return OPCODE_AE_CVTQ48A32S;
30208
-
break;
30209
-
case 3:
30210
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30211
-
Field_op2_Slot_inst_get (insn) == 12)
30212
-
return OPCODE_AE_LQ32F_IU;
30213
-
if (Field_op1_Slot_inst_get (insn) == 2 &&
30214
-
Field_op2_Slot_inst_get (insn) == 12)
30215
-
return OPCODE_AE_LQ32F_XU;
30216
-
break;
29713
+
if (Field_op2_Slot_inst_get (insn) == 0)
29714
+
return OPCODE_ANDB;
29715
+
if (Field_op2_Slot_inst_get (insn) == 1)
29716
+
return OPCODE_ANDBC;
29717
+
if (Field_op2_Slot_inst_get (insn) == 2)
29718
+
return OPCODE_ORB;
29719
+
if (Field_op2_Slot_inst_get (insn) == 3)
29720
+
return OPCODE_ORBC;
29721
+
if (Field_op2_Slot_inst_get (insn) == 4)
29722
+
return OPCODE_XORB;
29723
+
if (Field_op2_Slot_inst_get (insn) == 8)
29724
+
return OPCODE_MULL;
30217
29725
}
30218
-
switch (Field_ae_r3_Slot_inst_get (insn))
29726
+
if (Field_op1_Slot_inst_get (insn) == 3)
30219
29727
{
30220
-
case 0:
30221
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30222
-
Field_op2_Slot_inst_get (insn) == 10)
30223
-
return OPCODE_AE_LP16F_I;
30224
-
if (Field_op1_Slot_inst_get (insn) == 9 &&
30225
-
Field_op2_Slot_inst_get (insn) == 10)
30226
-
return OPCODE_AE_LP16F_IU;
30227
-
if (Field_op1_Slot_inst_get (insn) == 12 &&
30228
-
Field_op2_Slot_inst_get (insn) == 10)
30229
-
return OPCODE_AE_LP16F_X;
30230
-
if (Field_op1_Slot_inst_get (insn) == 15 &&
30231
-
Field_op2_Slot_inst_get (insn) == 10)
30232
-
return OPCODE_AE_LP16F_XU;
30233
-
if (Field_op1_Slot_inst_get (insn) == 6 &&
30234
-
Field_op2_Slot_inst_get (insn) == 10)
30235
-
return OPCODE_AE_LP24F_I;
30236
-
if (Field_op1_Slot_inst_get (insn) == 10 &&
30237
-
Field_op2_Slot_inst_get (insn) == 10)
30238
-
return OPCODE_AE_LP24F_IU;
30239
-
if (Field_op1_Slot_inst_get (insn) == 13 &&
30240
-
Field_op2_Slot_inst_get (insn) == 10)
30241
-
return OPCODE_AE_LP24F_X;
30242
-
if (Field_op1_Slot_inst_get (insn) == 0 &&
30243
-
Field_op2_Slot_inst_get (insn) == 11)
30244
-
return OPCODE_AE_LP24F_XU;
30245
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30246
-
Field_op2_Slot_inst_get (insn) == 10)
30247
-
return OPCODE_AE_LP24X2F_I;
30248
-
if (Field_op1_Slot_inst_get (insn) == 11 &&
30249
-
Field_op2_Slot_inst_get (insn) == 10)
30250
-
return OPCODE_AE_LP24X2F_IU;
30251
-
if (Field_op1_Slot_inst_get (insn) == 14 &&
30252
-
Field_op2_Slot_inst_get (insn) == 10)
30253
-
return OPCODE_AE_LP24X2F_X;
30254
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30255
-
Field_op2_Slot_inst_get (insn) == 11)
30256
-
return OPCODE_AE_LP24X2F_XU;
30257
-
if (Field_op1_Slot_inst_get (insn) == 2 &&
30258
-
Field_op2_Slot_inst_get (insn) == 11)
30259
-
return OPCODE_AE_SP16X2F_I;
30260
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30261
-
Field_op2_Slot_inst_get (insn) == 11)
30262
-
return OPCODE_AE_SP16X2F_IU;
30263
-
if (Field_op1_Slot_inst_get (insn) == 8 &&
30264
-
Field_op2_Slot_inst_get (insn) == 11)
30265
-
return OPCODE_AE_SP16X2F_X;
30266
-
if (Field_op1_Slot_inst_get (insn) == 11 &&
30267
-
Field_op2_Slot_inst_get (insn) == 11)
30268
-
return OPCODE_AE_SP16X2F_XU;
30269
-
if (Field_op1_Slot_inst_get (insn) == 3 &&
30270
-
Field_op2_Slot_inst_get (insn) == 11)
30271
-
return OPCODE_AE_SP24X2F_I;
30272
-
if (Field_op1_Slot_inst_get (insn) == 6 &&
30273
-
Field_op2_Slot_inst_get (insn) == 11)
30274
-
return OPCODE_AE_SP24X2F_IU;
30275
-
if (Field_op1_Slot_inst_get (insn) == 9 &&
30276
-
Field_op2_Slot_inst_get (insn) == 11)
30277
-
return OPCODE_AE_SP24X2F_X;
30278
-
if (Field_op1_Slot_inst_get (insn) == 12 &&
30279
-
Field_op2_Slot_inst_get (insn) == 11)
30280
-
return OPCODE_AE_SP24X2F_XU;
30281
-
if (Field_op1_Slot_inst_get (insn) == 4 &&
30282
-
Field_op2_Slot_inst_get (insn) == 11)
30283
-
return OPCODE_AE_SP24S_L_I;
30284
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30285
-
Field_op2_Slot_inst_get (insn) == 11)
30286
-
return OPCODE_AE_SP24S_L_IU;
30287
-
if (Field_op1_Slot_inst_get (insn) == 10 &&
30288
-
Field_op2_Slot_inst_get (insn) == 11)
30289
-
return OPCODE_AE_SP24S_L_X;
30290
-
if (Field_op1_Slot_inst_get (insn) == 13 &&
30291
-
Field_op2_Slot_inst_get (insn) == 11)
30292
-
return OPCODE_AE_SP24S_L_XU;
30293
-
if (Field_ae_s3_Slot_inst_get (insn) == 0 &&
30294
-
Field_t_Slot_inst_get (insn) == 0 &&
30295
-
Field_op1_Slot_inst_get (insn) == 9 &&
30296
-
Field_op2_Slot_inst_get (insn) == 12)
30297
-
return OPCODE_AE_MOVP48;
30298
-
if (Field_op1_Slot_inst_get (insn) == 0 &&
30299
-
Field_op2_Slot_inst_get (insn) == 12)
30300
-
return OPCODE_AE_MOVPA24X2;
30301
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30302
-
Field_op1_Slot_inst_get (insn) == 11 &&
30303
-
Field_op2_Slot_inst_get (insn) == 12)
30304
-
return OPCODE_AE_CVTA32P24_L;
30305
-
if (Field_op1_Slot_inst_get (insn) == 14 &&
30306
-
Field_op2_Slot_inst_get (insn) == 11)
30307
-
return OPCODE_AE_CVTP24A16X2_LL;
30308
-
if (Field_op1_Slot_inst_get (insn) == 15 &&
30309
-
Field_op2_Slot_inst_get (insn) == 11)
30310
-
return OPCODE_AE_CVTP24A16X2_HL;
30311
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30312
-
Field_op1_Slot_inst_get (insn) == 7 &&
30313
-
Field_op2_Slot_inst_get (insn) == 12)
30314
-
return OPCODE_AE_MOVAP24S_L;
30315
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30316
-
Field_op1_Slot_inst_get (insn) == 8 &&
30317
-
Field_op2_Slot_inst_get (insn) == 12)
30318
-
return OPCODE_AE_TRUNCA16P24S_L;
30319
-
break;
30320
-
case 1:
30321
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30322
-
Field_op2_Slot_inst_get (insn) == 10)
30323
-
return OPCODE_AE_LP24_I;
30324
-
if (Field_op1_Slot_inst_get (insn) == 9 &&
30325
-
Field_op2_Slot_inst_get (insn) == 10)
30326
-
return OPCODE_AE_LP24_IU;
30327
-
if (Field_op1_Slot_inst_get (insn) == 12 &&
30328
-
Field_op2_Slot_inst_get (insn) == 10)
30329
-
return OPCODE_AE_LP24_X;
30330
-
if (Field_op1_Slot_inst_get (insn) == 15 &&
30331
-
Field_op2_Slot_inst_get (insn) == 10)
30332
-
return OPCODE_AE_LP24_XU;
30333
-
if (Field_op1_Slot_inst_get (insn) == 6 &&
30334
-
Field_op2_Slot_inst_get (insn) == 10)
30335
-
return OPCODE_AE_LP16X2F_I;
30336
-
if (Field_op1_Slot_inst_get (insn) == 10 &&
30337
-
Field_op2_Slot_inst_get (insn) == 10)
30338
-
return OPCODE_AE_LP16X2F_IU;
30339
-
if (Field_op1_Slot_inst_get (insn) == 13 &&
30340
-
Field_op2_Slot_inst_get (insn) == 10)
30341
-
return OPCODE_AE_LP16X2F_X;
30342
-
if (Field_op1_Slot_inst_get (insn) == 0 &&
30343
-
Field_op2_Slot_inst_get (insn) == 11)
30344
-
return OPCODE_AE_LP16X2F_XU;
30345
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30346
-
Field_op2_Slot_inst_get (insn) == 10)
30347
-
return OPCODE_AE_LP24X2_I;
30348
-
if (Field_op1_Slot_inst_get (insn) == 11 &&
30349
-
Field_op2_Slot_inst_get (insn) == 10)
30350
-
return OPCODE_AE_LP24X2_IU;
30351
-
if (Field_op1_Slot_inst_get (insn) == 14 &&
30352
-
Field_op2_Slot_inst_get (insn) == 10)
30353
-
return OPCODE_AE_LP24X2_X;
30354
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30355
-
Field_op2_Slot_inst_get (insn) == 11)
30356
-
return OPCODE_AE_LP24X2_XU;
30357
-
if (Field_op1_Slot_inst_get (insn) == 2 &&
30358
-
Field_op2_Slot_inst_get (insn) == 11)
30359
-
return OPCODE_AE_SP24X2S_I;
30360
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30361
-
Field_op2_Slot_inst_get (insn) == 11)
30362
-
return OPCODE_AE_SP24X2S_IU;
30363
-
if (Field_op1_Slot_inst_get (insn) == 8 &&
30364
-
Field_op2_Slot_inst_get (insn) == 11)
30365
-
return OPCODE_AE_SP24X2S_X;
30366
-
if (Field_op1_Slot_inst_get (insn) == 11 &&
30367
-
Field_op2_Slot_inst_get (insn) == 11)
30368
-
return OPCODE_AE_SP24X2S_XU;
30369
-
if (Field_op1_Slot_inst_get (insn) == 3 &&
30370
-
Field_op2_Slot_inst_get (insn) == 11)
30371
-
return OPCODE_AE_SP16F_L_I;
30372
-
if (Field_op1_Slot_inst_get (insn) == 6 &&
30373
-
Field_op2_Slot_inst_get (insn) == 11)
30374
-
return OPCODE_AE_SP16F_L_IU;
30375
-
if (Field_op1_Slot_inst_get (insn) == 9 &&
30376
-
Field_op2_Slot_inst_get (insn) == 11)
30377
-
return OPCODE_AE_SP16F_L_X;
30378
-
if (Field_op1_Slot_inst_get (insn) == 12 &&
30379
-
Field_op2_Slot_inst_get (insn) == 11)
30380
-
return OPCODE_AE_SP16F_L_XU;
30381
-
if (Field_op1_Slot_inst_get (insn) == 4 &&
30382
-
Field_op2_Slot_inst_get (insn) == 11)
30383
-
return OPCODE_AE_SP24F_L_I;
30384
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30385
-
Field_op2_Slot_inst_get (insn) == 11)
30386
-
return OPCODE_AE_SP24F_L_IU;
30387
-
if (Field_op1_Slot_inst_get (insn) == 10 &&
30388
-
Field_op2_Slot_inst_get (insn) == 11)
30389
-
return OPCODE_AE_SP24F_L_X;
30390
-
if (Field_op1_Slot_inst_get (insn) == 13 &&
30391
-
Field_op2_Slot_inst_get (insn) == 11)
30392
-
return OPCODE_AE_SP24F_L_XU;
30393
-
if (Field_op1_Slot_inst_get (insn) == 0 &&
30394
-
Field_op2_Slot_inst_get (insn) == 12)
30395
-
return OPCODE_AE_TRUNCP24A32X2;
30396
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30397
-
Field_op1_Slot_inst_get (insn) == 11 &&
30398
-
Field_op2_Slot_inst_get (insn) == 12)
30399
-
return OPCODE_AE_CVTA32P24_H;
30400
-
if (Field_op1_Slot_inst_get (insn) == 14 &&
30401
-
Field_op2_Slot_inst_get (insn) == 11)
30402
-
return OPCODE_AE_CVTP24A16X2_LH;
30403
-
if (Field_op1_Slot_inst_get (insn) == 15 &&
30404
-
Field_op2_Slot_inst_get (insn) == 11)
30405
-
return OPCODE_AE_CVTP24A16X2_HH;
30406
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30407
-
Field_op1_Slot_inst_get (insn) == 7 &&
30408
-
Field_op2_Slot_inst_get (insn) == 12)
30409
-
return OPCODE_AE_MOVAP24S_H;
30410
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30411
-
Field_op1_Slot_inst_get (insn) == 8 &&
30412
-
Field_op2_Slot_inst_get (insn) == 12)
30413
-
return OPCODE_AE_TRUNCA16P24S_H;
30414
-
break;
30415
-
}
30416
-
switch (Field_ae_r32_Slot_inst_get (insn))
30417
-
{
30418
-
case 0:
30419
-
if (Field_op1_Slot_inst_get (insn) == 3 &&
30420
-
Field_op2_Slot_inst_get (insn) == 12)
30421
-
return OPCODE_AE_SQ56S_I;
30422
-
if (Field_op1_Slot_inst_get (insn) == 4 &&
30423
-
Field_op2_Slot_inst_get (insn) == 12)
30424
-
return OPCODE_AE_SQ56S_X;
30425
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30426
-
Field_t_Slot_inst_get (insn) == 1 &&
30427
-
Field_op2_Slot_inst_get (insn) == 14)
30428
-
return OPCODE_AE_TRUNCA32Q48;
30429
-
break;
30430
-
case 1:
30431
-
if (Field_op1_Slot_inst_get (insn) == 3 &&
30432
-
Field_op2_Slot_inst_get (insn) == 12)
30433
-
return OPCODE_AE_SQ32F_I;
30434
-
if (Field_op1_Slot_inst_get (insn) == 4 &&
30435
-
Field_op2_Slot_inst_get (insn) == 12)
30436
-
return OPCODE_AE_SQ32F_X;
30437
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30438
-
Field_t_Slot_inst_get (insn) == 1 &&
30439
-
Field_op2_Slot_inst_get (insn) == 14)
30440
-
return OPCODE_AE_NSAQ56S;
30441
-
break;
30442
-
case 2:
30443
-
if (Field_op1_Slot_inst_get (insn) == 3 &&
30444
-
Field_op2_Slot_inst_get (insn) == 12)
30445
-
return OPCODE_AE_SQ56S_IU;
30446
-
if (Field_op1_Slot_inst_get (insn) == 4 &&
30447
-
Field_op2_Slot_inst_get (insn) == 12)
30448
-
return OPCODE_AE_SQ56S_XU;
30449
-
break;
30450
-
case 3:
30451
-
if (Field_op1_Slot_inst_get (insn) == 3 &&
30452
-
Field_op2_Slot_inst_get (insn) == 12)
30453
-
return OPCODE_AE_SQ32F_IU;
30454
-
if (Field_op1_Slot_inst_get (insn) == 4 &&
30455
-
Field_op2_Slot_inst_get (insn) == 12)
30456
-
return OPCODE_AE_SQ32F_XU;
30457
-
break;
30458
-
}
30459
-
switch (Field_ae_s_non_samt_Slot_inst_get (insn))
30460
-
{
30461
-
case 0:
30462
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30463
-
Field_op2_Slot_inst_get (insn) == 12)
30464
-
return OPCODE_AE_SLLIQ56;
30465
-
break;
30466
-
case 1:
30467
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30468
-
Field_op2_Slot_inst_get (insn) == 12)
30469
-
return OPCODE_AE_SRLIQ56;
30470
-
break;
30471
-
case 2:
30472
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30473
-
Field_op2_Slot_inst_get (insn) == 12)
30474
-
return OPCODE_AE_SRAIQ56;
30475
-
break;
30476
-
case 3:
30477
-
if (Field_op1_Slot_inst_get (insn) == 5 &&
30478
-
Field_op2_Slot_inst_get (insn) == 12)
30479
-
return OPCODE_AE_SLLISQ56S;
30480
-
break;
30481
-
}
30482
-
switch (Field_op1_Slot_inst_get (insn))
30483
-
{
30484
-
case 0:
30485
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30486
-
Field_op2_Slot_inst_get (insn) == 14)
30487
-
return OPCODE_AE_SHA32;
29728
+
if (Field_op2_Slot_inst_get (insn) == 0)
29729
+
{
29730
+
if (Field_sr_Slot_inst_get (insn) == 0)
29731
+
return OPCODE_RSR_LBEG;
29732
+
if (Field_sr_Slot_inst_get (insn) == 1)
29733
+
return OPCODE_RSR_LEND;
29734
+
if (Field_sr_Slot_inst_get (insn) == 2)
29735
+
return OPCODE_RSR_LCOUNT;
29736
+
if (Field_sr_Slot_inst_get (insn) == 3)
29737
+
return OPCODE_RSR_SAR;
29738
+
if (Field_sr_Slot_inst_get (insn) == 4)
29739
+
return OPCODE_RSR_BR;
29740
+
if (Field_sr_Slot_inst_get (insn) == 5)
29741
+
return OPCODE_RSR_LITBASE;
29742
+
if (Field_sr_Slot_inst_get (insn) == 12)
29743
+
return OPCODE_RSR_SCOMPARE1;
29744
+
if (Field_sr_Slot_inst_get (insn) == 72)
29745
+
return OPCODE_RSR_WINDOWBASE;
29746
+
if (Field_sr_Slot_inst_get (insn) == 73)
29747
+
return OPCODE_RSR_WINDOWSTART;
29748
+
if (Field_sr_Slot_inst_get (insn) == 83)
29749
+
return OPCODE_RSR_PTEVADDR;
29750
+
if (Field_sr_Slot_inst_get (insn) == 90)
29751
+
return OPCODE_RSR_RASID;
29752
+
if (Field_sr_Slot_inst_get (insn) == 91)
29753
+
return OPCODE_RSR_ITLBCFG;
29754
+
if (Field_sr_Slot_inst_get (insn) == 92)
29755
+
return OPCODE_RSR_DTLBCFG;
29756
+
if (Field_sr_Slot_inst_get (insn) == 99)
29757
+
return OPCODE_RSR_ATOMCTL;
29758
+
if (Field_sr_Slot_inst_get (insn) == 104)
29759
+
return OPCODE_RSR_DDR;
29760
+
if (Field_sr_Slot_inst_get (insn) == 176)
29761
+
return OPCODE_RSR_CONFIGID0;
29762
+
if (Field_sr_Slot_inst_get (insn) == 177)
29763
+
return OPCODE_RSR_EPC1;
29764
+
if (Field_sr_Slot_inst_get (insn) == 178)
29765
+
return OPCODE_RSR_EPC2;
29766
+
if (Field_sr_Slot_inst_get (insn) == 192)
29767
+
return OPCODE_RSR_DEPC;
29768
+
if (Field_sr_Slot_inst_get (insn) == 194)
29769
+
return OPCODE_RSR_EPS2;
29770
+
if (Field_sr_Slot_inst_get (insn) == 208)
29771
+
return OPCODE_RSR_CONFIGID1;
29772
+
if (Field_sr_Slot_inst_get (insn) == 209)
29773
+
return OPCODE_RSR_EXCSAVE1;
29774
+
if (Field_sr_Slot_inst_get (insn) == 210)
29775
+
return OPCODE_RSR_EXCSAVE2;
29776
+
if (Field_sr_Slot_inst_get (insn) == 224)
29777
+
return OPCODE_RSR_CPENABLE;
29778
+
if (Field_sr_Slot_inst_get (insn) == 226)
29779
+
return OPCODE_RSR_INTERRUPT;
29780
+
if (Field_sr_Slot_inst_get (insn) == 228)
29781
+
return OPCODE_RSR_INTENABLE;
29782
+
if (Field_sr_Slot_inst_get (insn) == 230)
29783
+
return OPCODE_RSR_PS;
29784
+
if (Field_sr_Slot_inst_get (insn) == 231)
29785
+
return OPCODE_RSR_VECBASE;
29786
+
if (Field_sr_Slot_inst_get (insn) == 232)
29787
+
return OPCODE_RSR_EXCCAUSE;
29788
+
if (Field_sr_Slot_inst_get (insn) == 233)
29789
+
return OPCODE_RSR_DEBUGCAUSE;
29790
+
if (Field_sr_Slot_inst_get (insn) == 234)
29791
+
return OPCODE_RSR_CCOUNT;
29792
+
if (Field_sr_Slot_inst_get (insn) == 235)
29793
+
return OPCODE_RSR_PRID;
29794
+
if (Field_sr_Slot_inst_get (insn) == 236)
29795
+
return OPCODE_RSR_ICOUNT;
29796
+
if (Field_sr_Slot_inst_get (insn) == 237)
29797
+
return OPCODE_RSR_ICOUNTLEVEL;
29798
+
if (Field_sr_Slot_inst_get (insn) == 238)
29799
+
return OPCODE_RSR_EXCVADDR;
29800
+
if (Field_sr_Slot_inst_get (insn) == 240)
29801
+
return OPCODE_RSR_CCOMPARE0;
29802
+
if (Field_sr_Slot_inst_get (insn) == 241)
29803
+
return OPCODE_RSR_CCOMPARE1;
29804
+
if (Field_sr_Slot_inst_get (insn) == 244)
29805
+
return OPCODE_RSR_MISC0;
29806
+
if (Field_sr_Slot_inst_get (insn) == 245)
29807
+
return OPCODE_RSR_MISC1;
29808
+
}
29809
+
if (Field_op2_Slot_inst_get (insn) == 1)
29810
+
{
29811
+
if (Field_sr_Slot_inst_get (insn) == 0)
29812
+
return OPCODE_WSR_LBEG;
29813
+
if (Field_sr_Slot_inst_get (insn) == 1)
29814
+
return OPCODE_WSR_LEND;
29815
+
if (Field_sr_Slot_inst_get (insn) == 2)
29816
+
return OPCODE_WSR_LCOUNT;
29817
+
if (Field_sr_Slot_inst_get (insn) == 3)
29818
+
return OPCODE_WSR_SAR;
29819
+
if (Field_sr_Slot_inst_get (insn) == 4)
29820
+
return OPCODE_WSR_BR;
29821
+
if (Field_sr_Slot_inst_get (insn) == 5)
29822
+
return OPCODE_WSR_LITBASE;
29823
+
if (Field_sr_Slot_inst_get (insn) == 12)
29824
+
return OPCODE_WSR_SCOMPARE1;
29825
+
if (Field_sr_Slot_inst_get (insn) == 72)
29826
+
return OPCODE_WSR_WINDOWBASE;
29827
+
if (Field_sr_Slot_inst_get (insn) == 73)
29828
+
return OPCODE_WSR_WINDOWSTART;
29829
+
if (Field_sr_Slot_inst_get (insn) == 83)
29830
+
return OPCODE_WSR_PTEVADDR;
29831
+
if (Field_sr_Slot_inst_get (insn) == 90)
29832
+
return OPCODE_WSR_RASID;
29833
+
if (Field_sr_Slot_inst_get (insn) == 91)
29834
+
return OPCODE_WSR_ITLBCFG;
29835
+
if (Field_sr_Slot_inst_get (insn) == 92)
29836
+
return OPCODE_WSR_DTLBCFG;
29837
+
if (Field_sr_Slot_inst_get (insn) == 99)
29838
+
return OPCODE_WSR_ATOMCTL;
29839
+
if (Field_sr_Slot_inst_get (insn) == 104)
29840
+
return OPCODE_WSR_DDR;
29841
+
if (Field_sr_Slot_inst_get (insn) == 176)
29842
+
return OPCODE_WSR_CONFIGID0;
29843
+
if (Field_sr_Slot_inst_get (insn) == 177)
29844
+
return OPCODE_WSR_EPC1;
29845
+
if (Field_sr_Slot_inst_get (insn) == 178)
29846
+
return OPCODE_WSR_EPC2;
29847
+
if (Field_sr_Slot_inst_get (insn) == 192)
29848
+
return OPCODE_WSR_DEPC;
29849
+
if (Field_sr_Slot_inst_get (insn) == 194)
29850
+
return OPCODE_WSR_EPS2;
29851
+
if (Field_sr_Slot_inst_get (insn) == 209)
29852
+
return OPCODE_WSR_EXCSAVE1;
29853
+
if (Field_sr_Slot_inst_get (insn) == 210)
29854
+
return OPCODE_WSR_EXCSAVE2;
29855
+
if (Field_sr_Slot_inst_get (insn) == 224)
29856
+
return OPCODE_WSR_CPENABLE;
29857
+
if (Field_sr_Slot_inst_get (insn) == 226)
29858
+
return OPCODE_WSR_INTSET;
29859
+
if (Field_sr_Slot_inst_get (insn) == 227)
29860
+
return OPCODE_WSR_INTCLEAR;
29861
+
if (Field_sr_Slot_inst_get (insn) == 228)
29862
+
return OPCODE_WSR_INTENABLE;
29863
+
if (Field_sr_Slot_inst_get (insn) == 230)
29864
+
return OPCODE_WSR_PS;
29865
+
if (Field_sr_Slot_inst_get (insn) == 231)
29866
+
return OPCODE_WSR_VECBASE;
29867
+
if (Field_sr_Slot_inst_get (insn) == 232)
29868
+
return OPCODE_WSR_EXCCAUSE;
29869
+
if (Field_sr_Slot_inst_get (insn) == 233)
29870
+
return OPCODE_WSR_DEBUGCAUSE;
29871
+
if (Field_sr_Slot_inst_get (insn) == 234)
29872
+
return OPCODE_WSR_CCOUNT;
29873
+
if (Field_sr_Slot_inst_get (insn) == 236)
29874
+
return OPCODE_WSR_ICOUNT;
29875
+
if (Field_sr_Slot_inst_get (insn) == 237)
29876
+
return OPCODE_WSR_ICOUNTLEVEL;
29877
+
if (Field_sr_Slot_inst_get (insn) == 238)
29878
+
return OPCODE_WSR_EXCVADDR;
29879
+
if (Field_sr_Slot_inst_get (insn) == 240)
29880
+
return OPCODE_WSR_CCOMPARE0;
29881
+
if (Field_sr_Slot_inst_get (insn) == 241)
29882
+
return OPCODE_WSR_CCOMPARE1;
29883
+
if (Field_sr_Slot_inst_get (insn) == 244)
29884
+
return OPCODE_WSR_MISC0;
29885
+
if (Field_sr_Slot_inst_get (insn) == 245)
29886
+
return OPCODE_WSR_MISC1;
29887
+
}
29888
+
if (Field_op2_Slot_inst_get (insn) == 2)
29889
+
return OPCODE_SEXT;
29890
+
if (Field_op2_Slot_inst_get (insn) == 3)
29891
+
return OPCODE_CLAMPS;
29892
+
if (Field_op2_Slot_inst_get (insn) == 4)
29893
+
return OPCODE_MIN;
29894
+
if (Field_op2_Slot_inst_get (insn) == 5)
29895
+
return OPCODE_MAX;
29896
+
if (Field_op2_Slot_inst_get (insn) == 6)
29897
+
return OPCODE_MINU;
29898
+
if (Field_op2_Slot_inst_get (insn) == 7)
29899
+
return OPCODE_MAXU;
29900
+
if (Field_op2_Slot_inst_get (insn) == 8)
29901
+
return OPCODE_MOVEQZ;
29902
+
if (Field_op2_Slot_inst_get (insn) == 9)
29903
+
return OPCODE_MOVNEZ;
30488
29904
if (Field_op2_Slot_inst_get (insn) == 10)
30489
-
return OPCODE_AE_VLDL32T;
30490
-
break;
30491
-
case 1:
30492
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30493
-
Field_op2_Slot_inst_get (insn) == 14)
30494
-
return OPCODE_AE_SLLAQ56;
30495
-
if (Field_op2_Slot_inst_get (insn) == 10)
30496
-
return OPCODE_AE_VLDL16T;
30497
-
break;
30498
-
case 2:
30499
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30500
-
Field_op2_Slot_inst_get (insn) == 14)
30501
-
return OPCODE_AE_SRLAQ56;
30502
-
if (Field_op2_Slot_inst_get (insn) == 10)
30503
-
return OPCODE_AE_LBK;
30504
-
break;
30505
-
case 3:
30506
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30507
-
Field_op2_Slot_inst_get (insn) == 14)
30508
-
return OPCODE_AE_SRAAQ56;
30509
-
if (Field_op2_Slot_inst_get (insn) == 10)
30510
-
return OPCODE_AE_VLEL32T;
30511
-
break;
30512
-
case 4:
30513
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30514
-
Field_op2_Slot_inst_get (insn) == 14)
30515
-
return OPCODE_AE_SLLASQ56S;
30516
-
if (Field_op2_Slot_inst_get (insn) == 10)
30517
-
return OPCODE_AE_VLEL16T;
30518
-
break;
30519
-
case 5:
30520
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30521
-
Field_op2_Slot_inst_get (insn) == 14)
30522
-
return OPCODE_AE_MOVTQ56;
30523
-
break;
30524
-
case 6:
30525
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30526
-
Field_op2_Slot_inst_get (insn) == 14)
30527
-
return OPCODE_AE_MOVFQ56;
30528
-
break;
29905
+
return OPCODE_MOVLTZ;
29906
+
if (Field_op2_Slot_inst_get (insn) == 11)
29907
+
return OPCODE_MOVGEZ;
29908
+
if (Field_op2_Slot_inst_get (insn) == 12)
29909
+
return OPCODE_MOVF;
29910
+
if (Field_op2_Slot_inst_get (insn) == 13)
29911
+
return OPCODE_MOVT;
29912
+
if (Field_op2_Slot_inst_get (insn) == 14)
29913
+
{
29914
+
if (Field_st_Slot_inst_get (insn) == 231)
29915
+
return OPCODE_RUR_THREADPTR;
29916
+
if (Field_st_Slot_inst_get (insn) == 240)
29917
+
return OPCODE_RUR_AE_OVF_SAR;
29918
+
if (Field_st_Slot_inst_get (insn) == 241)
29919
+
return OPCODE_RUR_AE_BITHEAD;
29920
+
if (Field_st_Slot_inst_get (insn) == 242)
29921
+
return OPCODE_RUR_AE_TS_FTS_BU_BP;
29922
+
if (Field_st_Slot_inst_get (insn) == 243)
29923
+
return OPCODE_RUR_AE_SD_NO;
29924
+
}
29925
+
if (Field_op2_Slot_inst_get (insn) == 15)
29926
+
{
29927
+
if (Field_sr_Slot_inst_get (insn) == 231)
29928
+
return OPCODE_WUR_THREADPTR;
29929
+
if (Field_sr_Slot_inst_get (insn) == 240)
29930
+
return OPCODE_WUR_AE_OVF_SAR;
29931
+
if (Field_sr_Slot_inst_get (insn) == 241)
29932
+
return OPCODE_WUR_AE_BITHEAD;
29933
+
if (Field_sr_Slot_inst_get (insn) == 242)
29934
+
return OPCODE_WUR_AE_TS_FTS_BU_BP;
29935
+
if (Field_sr_Slot_inst_get (insn) == 243)
29936
+
return OPCODE_WUR_AE_SD_NO;
29937
+
}
30529
29938
}
30530
-
switch (Field_r_Slot_inst_get (insn))
29939
+
if ((Field_op1_Slot_inst_get (insn) == 4 ||
29940
+
Field_op1_Slot_inst_get (insn) == 5))
29941
+
return OPCODE_EXTUI;
29942
+
if (Field_op1_Slot_inst_get (insn) == 9)
30531
29943
{
30532
-
case 0:
30533
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30534
-
Field_op1_Slot_inst_get (insn) == 10 &&
30535
-
Field_op2_Slot_inst_get (insn) == 12)
30536
-
return OPCODE_WUR_AE_OVERFLOW;
30537
-
if (Field_op2_Slot_inst_get (insn) == 15)
30538
-
return OPCODE_AE_SBI;
30539
-
break;
30540
-
case 1:
30541
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30542
-
Field_op1_Slot_inst_get (insn) == 10 &&
30543
-
Field_op2_Slot_inst_get (insn) == 12)
30544
-
return OPCODE_WUR_AE_SAR;
30545
-
if (Field_op1_Slot_inst_get (insn) == 0 &&
30546
-
Field_op2_Slot_inst_get (insn) == 15)
30547
-
return OPCODE_AE_DB;
30548
-
if (Field_op1_Slot_inst_get (insn) == 1 &&
30549
-
Field_op2_Slot_inst_get (insn) == 15)
30550
-
return OPCODE_AE_SB;
30551
-
break;
30552
-
case 2:
30553
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30554
-
Field_op1_Slot_inst_get (insn) == 10 &&
30555
-
Field_op2_Slot_inst_get (insn) == 12)
30556
-
return OPCODE_WUR_AE_BITPTR;
30557
-
break;
30558
-
case 3:
30559
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30560
-
Field_op1_Slot_inst_get (insn) == 10 &&
30561
-
Field_op2_Slot_inst_get (insn) == 12)
30562
-
return OPCODE_WUR_AE_BITSUSED;
30563
-
break;
30564
-
case 4:
30565
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30566
-
Field_op1_Slot_inst_get (insn) == 10 &&
30567
-
Field_op2_Slot_inst_get (insn) == 12)
30568
-
return OPCODE_WUR_AE_TABLESIZE;
30569
-
break;
30570
-
case 5:
30571
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30572
-
Field_op1_Slot_inst_get (insn) == 10 &&
30573
-
Field_op2_Slot_inst_get (insn) == 12)
30574
-
return OPCODE_WUR_AE_FIRST_TS;
30575
-
break;
30576
-
case 6:
30577
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30578
-
Field_op1_Slot_inst_get (insn) == 10 &&
30579
-
Field_op2_Slot_inst_get (insn) == 12)
30580
-
return OPCODE_WUR_AE_NEXTOFFSET;
30581
-
break;
30582
-
case 7:
30583
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30584
-
Field_op1_Slot_inst_get (insn) == 10 &&
30585
-
Field_op2_Slot_inst_get (insn) == 12)
30586
-
return OPCODE_WUR_AE_SEARCHDONE;
30587
-
break;
30588
-
case 8:
30589
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30590
-
Field_op1_Slot_inst_get (insn) == 10 &&
30591
-
Field_op2_Slot_inst_get (insn) == 12)
30592
-
return OPCODE_AE_VLDSHT;
30593
-
break;
30594
-
case 12:
30595
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30596
-
Field_t_Slot_inst_get (insn) == 1 &&
30597
-
Field_op2_Slot_inst_get (insn) == 14)
30598
-
return OPCODE_AE_VLES16C;
30599
-
break;
30600
-
case 13:
30601
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30602
-
Field_t_Slot_inst_get (insn) == 1 &&
30603
-
Field_op2_Slot_inst_get (insn) == 14)
30604
-
return OPCODE_AE_SBF;
30605
-
break;
30606
-
case 14:
30607
-
if (Field_op1_Slot_inst_get (insn) == 7 &&
30608
-
Field_t_Slot_inst_get (insn) == 1 &&
30609
-
Field_op2_Slot_inst_get (insn) == 14)
30610
-
return OPCODE_AE_VLDL16C;
30611
-
break;
29944
+
if (Field_op2_Slot_inst_get (insn) == 0)
29945
+
return OPCODE_L32E;
29946
+
if (Field_op2_Slot_inst_get (insn) == 4)
29947
+
return OPCODE_S32E;
30612
29948
}
30613
-
switch (Field_s_Slot_inst_get (insn))
29949
+
}
29950
+
if (Field_op0_Slot_inst_get (insn) == 1)
29951
+
return OPCODE_L32R;
29952
+
if (Field_op0_Slot_inst_get (insn) == 2)
29953
+
{
29954
+
if (Field_r_Slot_inst_get (insn) == 0)
29955
+
return OPCODE_L8UI;
29956
+
if (Field_r_Slot_inst_get (insn) == 1)
29957
+
return OPCODE_L16UI;
29958
+
if (Field_r_Slot_inst_get (insn) == 2)
29959
+
return OPCODE_L32I;
29960
+
if (Field_r_Slot_inst_get (insn) == 4)
29961
+
return OPCODE_S8I;
29962
+
if (Field_r_Slot_inst_get (insn) == 5)
29963
+
return OPCODE_S16I;
29964
+
if (Field_r_Slot_inst_get (insn) == 6)
29965
+
return OPCODE_S32I;
29966
+
if (Field_r_Slot_inst_get (insn) == 7)
30614
29967
{
30615
-
case 0:
30616
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30617
-
Field_op1_Slot_inst_get (insn) == 9 &&
30618
-
Field_op2_Slot_inst_get (insn) == 12)
30619
-
return OPCODE_AE_SLLSQ56;
30620
-
if (Field_op1_Slot_inst_get (insn) == 6 &&
30621
-
Field_op2_Slot_inst_get (insn) == 12)
30622
-
return OPCODE_AE_LB;
30623
-
break;
30624
-
case 1:
30625
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30626
-
Field_op1_Slot_inst_get (insn) == 9 &&
30627
-
Field_op2_Slot_inst_get (insn) == 12)
30628
-
return OPCODE_AE_SRLSQ56;
30629
-
break;
30630
-
case 2:
30631
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30632
-
Field_op1_Slot_inst_get (insn) == 9 &&
30633
-
Field_op2_Slot_inst_get (insn) == 12)
30634
-
return OPCODE_AE_SRASQ56;
30635
-
break;
30636
-
case 3:
30637
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30638
-
Field_op1_Slot_inst_get (insn) == 9 &&
30639
-
Field_op2_Slot_inst_get (insn) == 12)
30640
-
return OPCODE_AE_SLLSSQ56S;
30641
-
break;
30642
-
case 4:
30643
-
if (Field_t_Slot_inst_get (insn) == 1 &&
30644
-
Field_op1_Slot_inst_get (insn) == 9 &&
30645
-
Field_op2_Slot_inst_get (insn) == 12)
30646
-
return OPCODE_AE_MOVQ56;
30647
-
break;
30648
-
case 8:
30649
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30650
-
Field_op1_Slot_inst_get (insn) == 9 &&
30651
-
Field_op2_Slot_inst_get (insn) == 12)
30652
-
return OPCODE_RUR_AE_OVERFLOW;
30653
-
break;
30654
-
case 9:
30655
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30656
-
Field_op1_Slot_inst_get (insn) == 9 &&
30657
-
Field_op2_Slot_inst_get (insn) == 12)
30658
-
return OPCODE_RUR_AE_SAR;
30659
-
break;
30660
-
case 10:
30661
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30662
-
Field_op1_Slot_inst_get (insn) == 9 &&
30663
-
Field_op2_Slot_inst_get (insn) == 12)
30664
-
return OPCODE_RUR_AE_BITPTR;
30665
-
break;
30666
-
case 11:
30667
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30668
-
Field_op1_Slot_inst_get (insn) == 9 &&
30669
-
Field_op2_Slot_inst_get (insn) == 12)
30670
-
return OPCODE_RUR_AE_BITSUSED;
30671
-
break;
30672
-
case 12:
30673
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30674
-
Field_op1_Slot_inst_get (insn) == 9 &&
30675
-
Field_op2_Slot_inst_get (insn) == 12)
30676
-
return OPCODE_RUR_AE_TABLESIZE;
30677
-
break;
30678
-
case 13:
30679
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30680
-
Field_op1_Slot_inst_get (insn) == 9 &&
30681
-
Field_op2_Slot_inst_get (insn) == 12)
30682
-
return OPCODE_RUR_AE_FIRST_TS;
30683
-
break;
30684
-
case 14:
30685
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30686
-
Field_op1_Slot_inst_get (insn) == 9 &&
30687
-
Field_op2_Slot_inst_get (insn) == 12)
30688
-
return OPCODE_RUR_AE_NEXTOFFSET;
30689
-
break;
30690
-
case 15:
30691
-
if (Field_t_Slot_inst_get (insn) == 0 &&
30692
-
Field_op1_Slot_inst_get (insn) == 9 &&
30693
-
Field_op2_Slot_inst_get (insn) == 12)
30694
-
return OPCODE_RUR_AE_SEARCHDONE;
30695
-
break;
29968
+
if (Field_t_Slot_inst_get (insn) == 0)
29969
+
return OPCODE_DPFR;
29970
+
if (Field_t_Slot_inst_get (insn) == 1)
29971
+
return OPCODE_DPFW;
29972
+
if (Field_t_Slot_inst_get (insn) == 2)
29973
+
return OPCODE_DPFRO;
29974
+
if (Field_t_Slot_inst_get (insn) == 3)
29975
+
return OPCODE_DPFWO;
29976
+
if (Field_t_Slot_inst_get (insn) == 4)
29977
+
return OPCODE_DHWB;
29978
+
if (Field_t_Slot_inst_get (insn) == 5)
29979
+
return OPCODE_DHWBI;
29980
+
if (Field_t_Slot_inst_get (insn) == 6)
29981
+
return OPCODE_DHI;
29982
+
if (Field_t_Slot_inst_get (insn) == 7)
29983
+
return OPCODE_DII;
29984
+
if (Field_t_Slot_inst_get (insn) == 8)
29985
+
{
29986
+
if (Field_op1_Slot_inst_get (insn) == 4)
29987
+
return OPCODE_DIWB;
29988
+
if (Field_op1_Slot_inst_get (insn) == 5)
29989
+
return OPCODE_DIWBI;
29990
+
}
29991
+
if (Field_t_Slot_inst_get (insn) == 12)
29992
+
return OPCODE_IPF;
29993
+
if (Field_t_Slot_inst_get (insn) == 14)
29994
+
return OPCODE_IHI;
29995
+
if (Field_t_Slot_inst_get (insn) == 15)
29996
+
return OPCODE_III;
30696
29997
}
30697
-
switch (Field_t_Slot_inst_get (insn))
29998
+
if (Field_r_Slot_inst_get (insn) == 9)
29999
+
return OPCODE_L16SI;
30000
+
if (Field_r_Slot_inst_get (insn) == 10)
30001
+
return OPCODE_MOVI;
30002
+
if (Field_r_Slot_inst_get (insn) == 11)
30003
+
return OPCODE_L32AI;
30004
+
if (Field_r_Slot_inst_get (insn) == 12)
30005
+
return OPCODE_ADDI;
30006
+
if (Field_r_Slot_inst_get (insn) == 13)
30007
+
return OPCODE_ADDMI;
30008
+
if (Field_r_Slot_inst_get (insn) == 14)
30009
+
return OPCODE_S32C1I;
30010
+
if (Field_r_Slot_inst_get (insn) == 15)
30011
+
return OPCODE_S32RI;
30012
+
}
30013
+
if (Field_op0_Slot_inst_get (insn) == 4)
30014
+
{
30015
+
if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
30016
+
Field_op1_Slot_inst_get (insn) == 1 &&
30017
+
Field_op2_Slot_inst_get (insn) == 12)
30018
+
return OPCODE_AE_LQ56_I;
30019
+
if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
30020
+
Field_op1_Slot_inst_get (insn) == 2 &&
30021
+
Field_op2_Slot_inst_get (insn) == 12)
30022
+
return OPCODE_AE_LQ56_X;
30023
+
if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
30024
+
Field_op1_Slot_inst_get (insn) == 1 &&
30025
+
Field_op2_Slot_inst_get (insn) == 12)
30026
+
return OPCODE_AE_LQ32F_I;
30027
+
if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
30028
+
Field_op1_Slot_inst_get (insn) == 2 &&
30029
+
Field_op2_Slot_inst_get (insn) == 12)
30030
+
return OPCODE_AE_LQ32F_X;
30031
+
if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30032
+
Field_op1_Slot_inst_get (insn) == 1 &&
30033
+
Field_op2_Slot_inst_get (insn) == 12)
30034
+
return OPCODE_AE_LQ56_IU;
30035
+
if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30036
+
Field_op1_Slot_inst_get (insn) == 2 &&
30037
+
Field_op2_Slot_inst_get (insn) == 12)
30038
+
return OPCODE_AE_LQ56_XU;
30039
+
if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
30040
+
Field_op1_Slot_inst_get (insn) == 7 &&
30041
+
Field_t_Slot_inst_get (insn) == 3 &&
30042
+
Field_op2_Slot_inst_get (insn) == 14)
30043
+
return OPCODE_AE_CVTQ48A32S;
30044
+
if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
30045
+
Field_op1_Slot_inst_get (insn) == 1 &&
30046
+
Field_op2_Slot_inst_get (insn) == 12)
30047
+
return OPCODE_AE_LQ32F_IU;
30048
+
if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
30049
+
Field_op1_Slot_inst_get (insn) == 2 &&
30050
+
Field_op2_Slot_inst_get (insn) == 12)
30051
+
return OPCODE_AE_LQ32F_XU;
30052
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30053
+
Field_op1_Slot_inst_get (insn) == 5 &&
30054
+
Field_op2_Slot_inst_get (insn) == 10)
30055
+
return OPCODE_AE_LP16F_I;
30056
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30057
+
Field_op1_Slot_inst_get (insn) == 9 &&
30058
+
Field_op2_Slot_inst_get (insn) == 10)
30059
+
return OPCODE_AE_LP16F_IU;
30060
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30061
+
Field_op1_Slot_inst_get (insn) == 12 &&
30062
+
Field_op2_Slot_inst_get (insn) == 10)
30063
+
return OPCODE_AE_LP16F_X;
30064
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30065
+
Field_op1_Slot_inst_get (insn) == 15 &&
30066
+
Field_op2_Slot_inst_get (insn) == 10)
30067
+
return OPCODE_AE_LP16F_XU;
30068
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30069
+
Field_op1_Slot_inst_get (insn) == 6 &&
30070
+
Field_op2_Slot_inst_get (insn) == 10)
30071
+
return OPCODE_AE_LP24F_I;
30072
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30073
+
Field_op1_Slot_inst_get (insn) == 10 &&
30074
+
Field_op2_Slot_inst_get (insn) == 10)
30075
+
return OPCODE_AE_LP24F_IU;
30076
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30077
+
Field_op1_Slot_inst_get (insn) == 13 &&
30078
+
Field_op2_Slot_inst_get (insn) == 10)
30079
+
return OPCODE_AE_LP24F_X;
30080
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30081
+
Field_op1_Slot_inst_get (insn) == 0 &&
30082
+
Field_op2_Slot_inst_get (insn) == 11)
30083
+
return OPCODE_AE_LP24F_XU;
30084
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30085
+
Field_op1_Slot_inst_get (insn) == 7 &&
30086
+
Field_op2_Slot_inst_get (insn) == 10)
30087
+
return OPCODE_AE_LP24X2F_I;
30088
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30089
+
Field_op1_Slot_inst_get (insn) == 11 &&
30090
+
Field_op2_Slot_inst_get (insn) == 10)
30091
+
return OPCODE_AE_LP24X2F_IU;
30092
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30093
+
Field_op1_Slot_inst_get (insn) == 14 &&
30094
+
Field_op2_Slot_inst_get (insn) == 10)
30095
+
return OPCODE_AE_LP24X2F_X;
30096
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30097
+
Field_op1_Slot_inst_get (insn) == 1 &&
30098
+
Field_op2_Slot_inst_get (insn) == 11)
30099
+
return OPCODE_AE_LP24X2F_XU;
30100
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30101
+
Field_op1_Slot_inst_get (insn) == 2 &&
30102
+
Field_op2_Slot_inst_get (insn) == 11)
30103
+
return OPCODE_AE_SP16X2F_I;
30104
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30105
+
Field_op1_Slot_inst_get (insn) == 5 &&
30106
+
Field_op2_Slot_inst_get (insn) == 11)
30107
+
return OPCODE_AE_SP16X2F_IU;
30108
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30109
+
Field_op1_Slot_inst_get (insn) == 8 &&
30110
+
Field_op2_Slot_inst_get (insn) == 11)
30111
+
return OPCODE_AE_SP16X2F_X;
30112
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30113
+
Field_op1_Slot_inst_get (insn) == 11 &&
30114
+
Field_op2_Slot_inst_get (insn) == 11)
30115
+
return OPCODE_AE_SP16X2F_XU;
30116
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30117
+
Field_op1_Slot_inst_get (insn) == 3 &&
30118
+
Field_op2_Slot_inst_get (insn) == 11)
30119
+
return OPCODE_AE_SP24X2F_I;
30120
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30121
+
Field_op1_Slot_inst_get (insn) == 6 &&
30122
+
Field_op2_Slot_inst_get (insn) == 11)
30123
+
return OPCODE_AE_SP24X2F_IU;
30124
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30125
+
Field_op1_Slot_inst_get (insn) == 9 &&
30126
+
Field_op2_Slot_inst_get (insn) == 11)
30127
+
return OPCODE_AE_SP24X2F_X;
30128
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30129
+
Field_op1_Slot_inst_get (insn) == 12 &&
30130
+
Field_op2_Slot_inst_get (insn) == 11)
30131
+
return OPCODE_AE_SP24X2F_XU;
30132
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30133
+
Field_op1_Slot_inst_get (insn) == 4 &&
30134
+
Field_op2_Slot_inst_get (insn) == 11)
30135
+
return OPCODE_AE_SP24S_L_I;
30136
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30137
+
Field_op1_Slot_inst_get (insn) == 7 &&
30138
+
Field_op2_Slot_inst_get (insn) == 11)
30139
+
return OPCODE_AE_SP24S_L_IU;
30140
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30141
+
Field_op1_Slot_inst_get (insn) == 10 &&
30142
+
Field_op2_Slot_inst_get (insn) == 11)
30143
+
return OPCODE_AE_SP24S_L_X;
30144
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30145
+
Field_op1_Slot_inst_get (insn) == 13 &&
30146
+
Field_op2_Slot_inst_get (insn) == 11)
30147
+
return OPCODE_AE_SP24S_L_XU;
30148
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30149
+
Field_ae_s3_Slot_inst_get (insn) == 0 &&
30150
+
Field_t_Slot_inst_get (insn) == 0 &&
30151
+
Field_op1_Slot_inst_get (insn) == 9 &&
30152
+
Field_op2_Slot_inst_get (insn) == 12)
30153
+
return OPCODE_AE_MOVP48;
30154
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30155
+
Field_op1_Slot_inst_get (insn) == 0 &&
30156
+
Field_op2_Slot_inst_get (insn) == 12)
30157
+
return OPCODE_AE_MOVPA24X2;
30158
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30159
+
Field_t_Slot_inst_get (insn) == 0 &&
30160
+
Field_op1_Slot_inst_get (insn) == 11 &&
30161
+
Field_op2_Slot_inst_get (insn) == 12)
30162
+
return OPCODE_AE_CVTA32P24_L;
30163
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30164
+
Field_op1_Slot_inst_get (insn) == 14 &&
30165
+
Field_op2_Slot_inst_get (insn) == 11)
30166
+
return OPCODE_AE_CVTP24A16X2_LL;
30167
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30168
+
Field_op1_Slot_inst_get (insn) == 15 &&
30169
+
Field_op2_Slot_inst_get (insn) == 11)
30170
+
return OPCODE_AE_CVTP24A16X2_HL;
30171
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30172
+
Field_t_Slot_inst_get (insn) == 0 &&
30173
+
Field_op1_Slot_inst_get (insn) == 7 &&
30174
+
Field_op2_Slot_inst_get (insn) == 12)
30175
+
return OPCODE_AE_MOVAP24S_L;
30176
+
if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
30177
+
Field_t_Slot_inst_get (insn) == 0 &&
30178
+
Field_op1_Slot_inst_get (insn) == 8 &&
30179
+
Field_op2_Slot_inst_get (insn) == 12)
30180
+
return OPCODE_AE_TRUNCA16P24S_L;
30181
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30182
+
Field_op1_Slot_inst_get (insn) == 5 &&
30183
+
Field_op2_Slot_inst_get (insn) == 10)
30184
+
return OPCODE_AE_LP24_I;
30185
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30186
+
Field_op1_Slot_inst_get (insn) == 9 &&
30187
+
Field_op2_Slot_inst_get (insn) == 10)
30188
+
return OPCODE_AE_LP24_IU;
30189
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30190
+
Field_op1_Slot_inst_get (insn) == 12 &&
30191
+
Field_op2_Slot_inst_get (insn) == 10)
30192
+
return OPCODE_AE_LP24_X;
30193
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30194
+
Field_op1_Slot_inst_get (insn) == 15 &&
30195
+
Field_op2_Slot_inst_get (insn) == 10)
30196
+
return OPCODE_AE_LP24_XU;
30197
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30198
+
Field_op1_Slot_inst_get (insn) == 6 &&
30199
+
Field_op2_Slot_inst_get (insn) == 10)
30200
+
return OPCODE_AE_LP16X2F_I;
30201
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30202
+
Field_op1_Slot_inst_get (insn) == 10 &&
30203
+
Field_op2_Slot_inst_get (insn) == 10)
30204
+
return OPCODE_AE_LP16X2F_IU;
30205
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30206
+
Field_op1_Slot_inst_get (insn) == 13 &&
30207
+
Field_op2_Slot_inst_get (insn) == 10)
30208
+
return OPCODE_AE_LP16X2F_X;
30209
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30210
+
Field_op1_Slot_inst_get (insn) == 0 &&
30211
+
Field_op2_Slot_inst_get (insn) == 11)
30212
+
return OPCODE_AE_LP16X2F_XU;
30213
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30214
+
Field_op1_Slot_inst_get (insn) == 7 &&
30215
+
Field_op2_Slot_inst_get (insn) == 10)
30216
+
return OPCODE_AE_LP24X2_I;
30217
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30218
+
Field_op1_Slot_inst_get (insn) == 11 &&
30219
+
Field_op2_Slot_inst_get (insn) == 10)
30220
+
return OPCODE_AE_LP24X2_IU;
30221
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30222
+
Field_op1_Slot_inst_get (insn) == 14 &&
30223
+
Field_op2_Slot_inst_get (insn) == 10)
30224
+
return OPCODE_AE_LP24X2_X;
30225
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30226
+
Field_op1_Slot_inst_get (insn) == 1 &&
30227
+
Field_op2_Slot_inst_get (insn) == 11)
30228
+
return OPCODE_AE_LP24X2_XU;
30229
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30230
+
Field_op1_Slot_inst_get (insn) == 2 &&
30231
+
Field_op2_Slot_inst_get (insn) == 11)
30232
+
return OPCODE_AE_SP24X2S_I;
30233
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30234
+
Field_op1_Slot_inst_get (insn) == 5 &&
30235
+
Field_op2_Slot_inst_get (insn) == 11)
30236
+
return OPCODE_AE_SP24X2S_IU;
30237
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30238
+
Field_op1_Slot_inst_get (insn) == 8 &&
30239
+
Field_op2_Slot_inst_get (insn) == 11)
30240
+
return OPCODE_AE_SP24X2S_X;
30241
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30242
+
Field_op1_Slot_inst_get (insn) == 11 &&
30243
+
Field_op2_Slot_inst_get (insn) == 11)
30244
+
return OPCODE_AE_SP24X2S_XU;
30245
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30246
+
Field_op1_Slot_inst_get (insn) == 3 &&
30247
+
Field_op2_Slot_inst_get (insn) == 11)
30248
+
return OPCODE_AE_SP16F_L_I;
30249
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30250
+
Field_op1_Slot_inst_get (insn) == 6 &&
30251
+
Field_op2_Slot_inst_get (insn) == 11)
30252
+
return OPCODE_AE_SP16F_L_IU;
30253
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30254
+
Field_op1_Slot_inst_get (insn) == 9 &&
30255
+
Field_op2_Slot_inst_get (insn) == 11)
30256
+
return OPCODE_AE_SP16F_L_X;
30257
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30258
+
Field_op1_Slot_inst_get (insn) == 12 &&
30259
+
Field_op2_Slot_inst_get (insn) == 11)
30260
+
return OPCODE_AE_SP16F_L_XU;
30261
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30262
+
Field_op1_Slot_inst_get (insn) == 4 &&
30263
+
Field_op2_Slot_inst_get (insn) == 11)
30264
+
return OPCODE_AE_SP24F_L_I;
30265
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30266
+
Field_op1_Slot_inst_get (insn) == 7 &&
30267
+
Field_op2_Slot_inst_get (insn) == 11)
30268
+
return OPCODE_AE_SP24F_L_IU;
30269
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30270
+
Field_op1_Slot_inst_get (insn) == 10 &&
30271
+
Field_op2_Slot_inst_get (insn) == 11)
30272
+
return OPCODE_AE_SP24F_L_X;
30273
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30274
+
Field_op1_Slot_inst_get (insn) == 13 &&
30275
+
Field_op2_Slot_inst_get (insn) == 11)
30276
+
return OPCODE_AE_SP24F_L_XU;
30277
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30278
+
Field_op1_Slot_inst_get (insn) == 0 &&
30279
+
Field_op2_Slot_inst_get (insn) == 12)
30280
+
return OPCODE_AE_TRUNCP24A32X2;
30281
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30282
+
Field_t_Slot_inst_get (insn) == 0 &&
30283
+
Field_op1_Slot_inst_get (insn) == 11 &&
30284
+
Field_op2_Slot_inst_get (insn) == 12)
30285
+
return OPCODE_AE_CVTA32P24_H;
30286
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30287
+
Field_op1_Slot_inst_get (insn) == 14 &&
30288
+
Field_op2_Slot_inst_get (insn) == 11)
30289
+
return OPCODE_AE_CVTP24A16X2_LH;
30290
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30291
+
Field_op1_Slot_inst_get (insn) == 15 &&
30292
+
Field_op2_Slot_inst_get (insn) == 11)
30293
+
return OPCODE_AE_CVTP24A16X2_HH;
30294
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30295
+
Field_t_Slot_inst_get (insn) == 0 &&
30296
+
Field_op1_Slot_inst_get (insn) == 7 &&
30297
+
Field_op2_Slot_inst_get (insn) == 12)
30298
+
return OPCODE_AE_MOVAP24S_H;
30299
+
if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
30300
+
Field_t_Slot_inst_get (insn) == 0 &&
30301
+
Field_op1_Slot_inst_get (insn) == 8 &&
30302
+
Field_op2_Slot_inst_get (insn) == 12)
30303
+
return OPCODE_AE_TRUNCA16P24S_H;
30304
+
if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30305
+
Field_op1_Slot_inst_get (insn) == 3 &&
30306
+
Field_op2_Slot_inst_get (insn) == 12)
30307
+
return OPCODE_AE_SQ56S_I;
30308
+
if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30309
+
Field_op1_Slot_inst_get (insn) == 4 &&
30310
+
Field_op2_Slot_inst_get (insn) == 12)
30311
+
return OPCODE_AE_SQ56S_X;
30312
+
if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
30313
+
Field_op1_Slot_inst_get (insn) == 7 &&
30314
+
Field_t_Slot_inst_get (insn) == 1 &&
30315
+
Field_op2_Slot_inst_get (insn) == 14)
30316
+
return OPCODE_AE_TRUNCA32Q48;
30317
+
if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30318
+
Field_op1_Slot_inst_get (insn) == 3 &&
30319
+
Field_op2_Slot_inst_get (insn) == 12)
30320
+
return OPCODE_AE_SQ32F_I;
30321
+
if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30322
+
Field_op1_Slot_inst_get (insn) == 4 &&
30323
+
Field_op2_Slot_inst_get (insn) == 12)
30324
+
return OPCODE_AE_SQ32F_X;
30325
+
if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
30326
+
Field_op1_Slot_inst_get (insn) == 7 &&
30327
+
Field_t_Slot_inst_get (insn) == 1 &&
30328
+
Field_op2_Slot_inst_get (insn) == 14)
30329
+
return OPCODE_AE_NSAQ56S;
30330
+
if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
30331
+
Field_op1_Slot_inst_get (insn) == 3 &&
30332
+
Field_op2_Slot_inst_get (insn) == 12)
30333
+
return OPCODE_AE_SQ56S_IU;
30334
+
if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
30335
+
Field_op1_Slot_inst_get (insn) == 4 &&
30336
+
Field_op2_Slot_inst_get (insn) == 12)
30337
+
return OPCODE_AE_SQ56S_XU;
30338
+
if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
30339
+
Field_op1_Slot_inst_get (insn) == 3 &&
30340
+
Field_op2_Slot_inst_get (insn) == 12)
30341
+
return OPCODE_AE_SQ32F_IU;
30342
+
if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
30343
+
Field_op1_Slot_inst_get (insn) == 4 &&
30344
+
Field_op2_Slot_inst_get (insn) == 12)
30345
+
return OPCODE_AE_SQ32F_XU;
30346
+
if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
30347
+
Field_op1_Slot_inst_get (insn) == 5 &&
30348
+
Field_op2_Slot_inst_get (insn) == 12)
30349
+
return OPCODE_AE_SLLIQ56;
30350
+
if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
30351
+
Field_op1_Slot_inst_get (insn) == 5 &&
30352
+
Field_op2_Slot_inst_get (insn) == 12)
30353
+
return OPCODE_AE_SRLIQ56;
30354
+
if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
30355
+
Field_op1_Slot_inst_get (insn) == 5 &&
30356
+
Field_op2_Slot_inst_get (insn) == 12)
30357
+
return OPCODE_AE_SRAIQ56;
30358
+
if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
30359
+
Field_op1_Slot_inst_get (insn) == 5 &&
30360
+
Field_op2_Slot_inst_get (insn) == 12)
30361
+
return OPCODE_AE_SLLISQ56S;
30362
+
if (Field_op1_Slot_inst_get (insn) == 0 &&
30363
+
Field_t_Slot_inst_get (insn) == 1 &&
30364
+
Field_op2_Slot_inst_get (insn) == 14)
30365
+
return OPCODE_AE_SHA32;
30366
+
if (Field_op1_Slot_inst_get (insn) == 0 &&
30367
+
Field_op2_Slot_inst_get (insn) == 10)
30368
+
return OPCODE_AE_VLDL32T;
30369
+
if (Field_op1_Slot_inst_get (insn) == 1 &&
30370
+
Field_t_Slot_inst_get (insn) == 1 &&
30371
+
Field_op2_Slot_inst_get (insn) == 14)
30372
+
return OPCODE_AE_SLLAQ56;
30373
+
if (Field_op1_Slot_inst_get (insn) == 1 &&
30374
+
Field_op2_Slot_inst_get (insn) == 10)
30375
+
return OPCODE_AE_VLDL16T;
30376
+
if (Field_op1_Slot_inst_get (insn) == 2 &&
30377
+
Field_t_Slot_inst_get (insn) == 1 &&
30378
+
Field_op2_Slot_inst_get (insn) == 14)
30379
+
return OPCODE_AE_SRLAQ56;
30380
+
if (Field_op1_Slot_inst_get (insn) == 2 &&
30381
+
Field_op2_Slot_inst_get (insn) == 10)
30382
+
return OPCODE_AE_LBK;
30383
+
if (Field_op1_Slot_inst_get (insn) == 3 &&
30384
+
Field_t_Slot_inst_get (insn) == 1 &&
30385
+
Field_op2_Slot_inst_get (insn) == 14)
30386
+
return OPCODE_AE_SRAAQ56;
30387
+
if (Field_op1_Slot_inst_get (insn) == 3 &&
30388
+
Field_op2_Slot_inst_get (insn) == 10)
30389
+
return OPCODE_AE_VLEL32T;
30390
+
if (Field_op1_Slot_inst_get (insn) == 4 &&
30391
+
Field_t_Slot_inst_get (insn) == 1 &&
30392
+
Field_op2_Slot_inst_get (insn) == 14)
30393
+
return OPCODE_AE_SLLASQ56S;
30394
+
if (Field_op1_Slot_inst_get (insn) == 4 &&
30395
+
Field_op2_Slot_inst_get (insn) == 10)
30396
+
return OPCODE_AE_VLEL16T;
30397
+
if (Field_op1_Slot_inst_get (insn) == 5 &&
30398
+
Field_t_Slot_inst_get (insn) == 1 &&
30399
+
Field_op2_Slot_inst_get (insn) == 14)
30400
+
return OPCODE_AE_MOVTQ56;
30401
+
if (Field_op1_Slot_inst_get (insn) == 6 &&
30402
+
Field_t_Slot_inst_get (insn) == 1 &&
30403
+
Field_op2_Slot_inst_get (insn) == 14)
30404
+
return OPCODE_AE_MOVFQ56;
30405
+
if (Field_r_Slot_inst_get (insn) == 0 &&
30406
+
Field_s_Slot_inst_get (insn) == 0 &&
30407
+
Field_op1_Slot_inst_get (insn) == 10 &&
30408
+
Field_op2_Slot_inst_get (insn) == 12)
30409
+
return OPCODE_WUR_AE_OVERFLOW;
30410
+
if (Field_r_Slot_inst_get (insn) == 0 &&
30411
+
Field_op2_Slot_inst_get (insn) == 15)
30412
+
return OPCODE_AE_SBI;
30413
+
if (Field_r_Slot_inst_get (insn) == 1 &&
30414
+
Field_s_Slot_inst_get (insn) == 0 &&
30415
+
Field_op1_Slot_inst_get (insn) == 10 &&
30416
+
Field_op2_Slot_inst_get (insn) == 12)
30417
+
return OPCODE_WUR_AE_SAR;
30418
+
if (Field_r_Slot_inst_get (insn) == 1 &&
30419
+
Field_op1_Slot_inst_get (insn) == 0 &&
30420
+
Field_op2_Slot_inst_get (insn) == 15)
30421
+
return OPCODE_AE_DB;
30422
+
if (Field_r_Slot_inst_get (insn) == 1 &&
30423
+
Field_op1_Slot_inst_get (insn) == 1 &&
30424
+
Field_op2_Slot_inst_get (insn) == 15)
30425
+
return OPCODE_AE_SB;
30426
+
if (Field_r_Slot_inst_get (insn) == 2 &&
30427
+
Field_s_Slot_inst_get (insn) == 0 &&
30428
+
Field_op1_Slot_inst_get (insn) == 10 &&
30429
+
Field_op2_Slot_inst_get (insn) == 12)
30430
+
return OPCODE_WUR_AE_BITPTR;
30431
+
if (Field_r_Slot_inst_get (insn) == 3 &&
30432
+
Field_s_Slot_inst_get (insn) == 0 &&
30433
+
Field_op1_Slot_inst_get (insn) == 10 &&
30434
+
Field_op2_Slot_inst_get (insn) == 12)
30435
+
return OPCODE_WUR_AE_BITSUSED;
30436
+
if (Field_r_Slot_inst_get (insn) == 4 &&
30437
+
Field_s_Slot_inst_get (insn) == 0 &&
30438
+
Field_op1_Slot_inst_get (insn) == 10 &&
30439
+
Field_op2_Slot_inst_get (insn) == 12)
30440
+
return OPCODE_WUR_AE_TABLESIZE;
30441
+
if (Field_r_Slot_inst_get (insn) == 5 &&
30442
+
Field_s_Slot_inst_get (insn) == 0 &&
30443
+
Field_op1_Slot_inst_get (insn) == 10 &&
30444
+
Field_op2_Slot_inst_get (insn) == 12)
30445
+
return OPCODE_WUR_AE_FIRST_TS;
30446
+
if (Field_r_Slot_inst_get (insn) == 6 &&
30447
+
Field_s_Slot_inst_get (insn) == 0 &&
30448
+
Field_op1_Slot_inst_get (insn) == 10 &&
30449
+
Field_op2_Slot_inst_get (insn) == 12)
30450
+
return OPCODE_WUR_AE_NEXTOFFSET;
30451
+
if (Field_r_Slot_inst_get (insn) == 7 &&
30452
+
Field_s_Slot_inst_get (insn) == 0 &&
30453
+
Field_op1_Slot_inst_get (insn) == 10 &&
30454
+
Field_op2_Slot_inst_get (insn) == 12)
30455
+
return OPCODE_WUR_AE_SEARCHDONE;
30456
+
if (Field_r_Slot_inst_get (insn) == 8 &&
30457
+
Field_s_Slot_inst_get (insn) == 0 &&
30458
+
Field_op1_Slot_inst_get (insn) == 10 &&
30459
+
Field_op2_Slot_inst_get (insn) == 12)
30460
+
return OPCODE_AE_VLDSHT;
30461
+
if (Field_r_Slot_inst_get (insn) == 12 &&
30462
+
Field_op1_Slot_inst_get (insn) == 7 &&
30463
+
Field_t_Slot_inst_get (insn) == 1 &&
30464
+
Field_op2_Slot_inst_get (insn) == 14)
30465
+
return OPCODE_AE_VLES16C;
30466
+
if (Field_r_Slot_inst_get (insn) == 13 &&
30467
+
Field_op1_Slot_inst_get (insn) == 7 &&
30468
+
Field_t_Slot_inst_get (insn) == 1 &&
30469
+
Field_op2_Slot_inst_get (insn) == 14)
30470
+
return OPCODE_AE_SBF;
30471
+
if (Field_r_Slot_inst_get (insn) == 14 &&
30472
+
Field_op1_Slot_inst_get (insn) == 7 &&
30473
+
Field_t_Slot_inst_get (insn) == 1 &&
30474
+
Field_op2_Slot_inst_get (insn) == 14)
30475
+
return OPCODE_AE_VLDL16C;
30476
+
if (Field_s_Slot_inst_get (insn) == 0 &&
30477
+
Field_t_Slot_inst_get (insn) == 1 &&
30478
+
Field_op1_Slot_inst_get (insn) == 9 &&
30479
+
Field_op2_Slot_inst_get (insn) == 12)
30480
+
return OPCODE_AE_SLLSQ56;
30481
+
if (Field_s_Slot_inst_get (insn) == 0 &&
30482
+
Field_op1_Slot_inst_get (insn) == 6 &&
30483
+
Field_op2_Slot_inst_get (insn) == 12)
30484
+
return OPCODE_AE_LB;
30485
+
if (Field_s_Slot_inst_get (insn) == 1 &&
30486
+
Field_t_Slot_inst_get (insn) == 1 &&
30487
+
Field_op1_Slot_inst_get (insn) == 9 &&
30488
+
Field_op2_Slot_inst_get (insn) == 12)
30489
+
return OPCODE_AE_SRLSQ56;
30490
+
if (Field_s_Slot_inst_get (insn) == 2 &&
30491
+
Field_t_Slot_inst_get (insn) == 1 &&
30492
+
Field_op1_Slot_inst_get (insn) == 9 &&
30493
+
Field_op2_Slot_inst_get (insn) == 12)
30494
+
return OPCODE_AE_SRASQ56;
30495
+
if (Field_s_Slot_inst_get (insn) == 3 &&
30496
+
Field_t_Slot_inst_get (insn) == 1 &&
30497
+
Field_op1_Slot_inst_get (insn) == 9 &&
30498
+
Field_op2_Slot_inst_get (insn) == 12)
30499
+
return OPCODE_AE_SLLSSQ56S;
30500
+
if (Field_s_Slot_inst_get (insn) == 4 &&
30501
+
Field_t_Slot_inst_get (insn) == 1 &&
30502
+
Field_op1_Slot_inst_get (insn) == 9 &&
30503
+
Field_op2_Slot_inst_get (insn) == 12)
30504
+
return OPCODE_AE_MOVQ56;
30505
+
if (Field_s_Slot_inst_get (insn) == 8 &&
30506
+
Field_t_Slot_inst_get (insn) == 0 &&
30507
+
Field_op1_Slot_inst_get (insn) == 9 &&
30508
+
Field_op2_Slot_inst_get (insn) == 12)
30509
+
return OPCODE_RUR_AE_OVERFLOW;
30510
+
if (Field_s_Slot_inst_get (insn) == 9 &&
30511
+
Field_t_Slot_inst_get (insn) == 0 &&
30512
+
Field_op1_Slot_inst_get (insn) == 9 &&
30513
+
Field_op2_Slot_inst_get (insn) == 12)
30514
+
return OPCODE_RUR_AE_SAR;
30515
+
if (Field_s_Slot_inst_get (insn) == 10 &&
30516
+
Field_t_Slot_inst_get (insn) == 0 &&
30517
+
Field_op1_Slot_inst_get (insn) == 9 &&
30518
+
Field_op2_Slot_inst_get (insn) == 12)
30519
+
return OPCODE_RUR_AE_BITPTR;
30520
+
if (Field_s_Slot_inst_get (insn) == 11 &&
30521
+
Field_t_Slot_inst_get (insn) == 0 &&
30522
+
Field_op1_Slot_inst_get (insn) == 9 &&
30523
+
Field_op2_Slot_inst_get (insn) == 12)
30524
+
return OPCODE_RUR_AE_BITSUSED;
30525
+
if (Field_s_Slot_inst_get (insn) == 12 &&
30526
+
Field_t_Slot_inst_get (insn) == 0 &&
30527
+
Field_op1_Slot_inst_get (insn) == 9 &&
30528
+
Field_op2_Slot_inst_get (insn) == 12)
30529
+
return OPCODE_RUR_AE_TABLESIZE;
30530
+
if (Field_s_Slot_inst_get (insn) == 13 &&
30531
+
Field_t_Slot_inst_get (insn) == 0 &&
30532
+
Field_op1_Slot_inst_get (insn) == 9 &&
30533
+
Field_op2_Slot_inst_get (insn) == 12)
30534
+
return OPCODE_RUR_AE_FIRST_TS;
30535
+
if (Field_s_Slot_inst_get (insn) == 14 &&
30536
+
Field_t_Slot_inst_get (insn) == 0 &&
30537
+
Field_op1_Slot_inst_get (insn) == 9 &&
30538
+
Field_op2_Slot_inst_get (insn) == 12)
30539
+
return OPCODE_RUR_AE_NEXTOFFSET;
30540
+
if (Field_s_Slot_inst_get (insn) == 15 &&
30541
+
Field_t_Slot_inst_get (insn) == 0 &&
30542
+
Field_op1_Slot_inst_get (insn) == 9 &&
30543
+
Field_op2_Slot_inst_get (insn) == 12)
30544
+
return OPCODE_RUR_AE_SEARCHDONE;
30545
+
if (Field_t_Slot_inst_get (insn) == 0 &&
30546
+
Field_op2_Slot_inst_get (insn) == 14)
30547
+
return OPCODE_AE_LBKI;
30548
+
if (Field_t_Slot_inst_get (insn) == 0 &&
30549
+
Field_r_Slot_inst_get (insn) == 2 &&
30550
+
Field_op2_Slot_inst_get (insn) == 15)
30551
+
return OPCODE_AE_DBI;
30552
+
if (Field_t_Slot_inst_get (insn) == 2 &&
30553
+
Field_s_Slot_inst_get (insn) == 0 &&
30554
+
Field_op2_Slot_inst_get (insn) == 14)
30555
+
return OPCODE_AE_LBI;
30556
+
}
30557
+
if (Field_op0_Slot_inst_get (insn) == 5)
30558
+
{
30559
+
if (Field_n_Slot_inst_get (insn) == 0)
30560
+
return OPCODE_CALL0;
30561
+
if (Field_n_Slot_inst_get (insn) == 1)
30562
+
return OPCODE_CALL4;
30563
+
if (Field_n_Slot_inst_get (insn) == 2)
30564
+
return OPCODE_CALL8;
30565
+
if (Field_n_Slot_inst_get (insn) == 3)
30566
+
return OPCODE_CALL12;
30567
+
}
30568
+
if (Field_op0_Slot_inst_get (insn) == 6)
30569
+
{
30570
+
if (Field_n_Slot_inst_get (insn) == 0)
30571
+
return OPCODE_J;
30572
+
if (Field_n_Slot_inst_get (insn) == 1)
30698
30573
{
30699
-
case 0:
30700
-
if (Field_op2_Slot_inst_get (insn) == 14)
30701
-
return OPCODE_AE_LBKI;
30702
-
if (Field_r_Slot_inst_get (insn) == 2 &&
30703
-
Field_op2_Slot_inst_get (insn) == 15)
30704
-
return OPCODE_AE_DBI;
30705
-
break;
30706
-
case 2:
30707
-
if (Field_s_Slot_inst_get (insn) == 0 &&
30708
-
Field_op2_Slot_inst_get (insn) == 14)
30709
-
return OPCODE_AE_LBI;
30710
-
break;
30574
+
if (Field_m_Slot_inst_get (insn) == 0)
30575
+
return OPCODE_BEQZ;
30576
+
if (Field_m_Slot_inst_get (insn) == 1)
30577
+
return OPCODE_BNEZ;
30578
+
if (Field_m_Slot_inst_get (insn) == 2)
30579
+
return OPCODE_BLTZ;
30580
+
if (Field_m_Slot_inst_get (insn) == 3)
30581
+
return OPCODE_BGEZ;
30711
30582
}
30712
-
break;
30713
-
case 5:
30714
-
switch (Field_n_Slot_inst_get (insn))
30583
+
if (Field_n_Slot_inst_get (insn) == 2)
30715
30584
{
30716
-
case 0:
30717
-
return OPCODE_CALL0;
30718
-
case 1:
30719
-
return OPCODE_CALL4;
30720
-
case 2:
30721
-
return OPCODE_CALL8;
30722
-
case 3:
30723
-
return OPCODE_CALL12;
30585
+
if (Field_m_Slot_inst_get (insn) == 0)
30586
+
return OPCODE_BEQI;
30587
+
if (Field_m_Slot_inst_get (insn) == 1)
30588
+
return OPCODE_BNEI;
30589
+
if (Field_m_Slot_inst_get (insn) == 2)
30590
+
return OPCODE_BLTI;
30591
+
if (Field_m_Slot_inst_get (insn) == 3)
30592
+
return OPCODE_BGEI;
30724
30593
}
30725
-
break;
30726
-
case 6:
30727
-
switch (Field_n_Slot_inst_get (insn))
30594
+
if (Field_n_Slot_inst_get (insn) == 3)
30728
30595
{
30729
-
case 0:
30730
-
return OPCODE_J;
30731
-
case 1:
30732
-
switch (Field_m_Slot_inst_get (insn))
30733
-
{
30734
-
case 0:
30735
-
return OPCODE_BEQZ;
30736
-
case 1:
30737
-
return OPCODE_BNEZ;
30738
-
case 2:
30739
-
return OPCODE_BLTZ;
30740
-
case 3:
30741
-
return OPCODE_BGEZ;
30742
-
}
30743
-
break;
30744
-
case 2:
30745
-
switch (Field_m_Slot_inst_get (insn))
30746
-
{
30747
-
case 0:
30748
-
return OPCODE_BEQI;
30749
-
case 1:
30750
-
return OPCODE_BNEI;
30751
-
case 2:
30752
-
return OPCODE_BLTI;
30753
-
case 3:
30754
-
return OPCODE_BGEI;
30755
-
}
30756
-
break;
30757
-
case 3:
30758
-
switch (Field_m_Slot_inst_get (insn))
30596
+
if (Field_m_Slot_inst_get (insn) == 0)
30597
+
return OPCODE_ENTRY;
30598
+
if (Field_m_Slot_inst_get (insn) == 1)
30759
30599
{
30760
-
case 0:
30761
-
return OPCODE_ENTRY;
30762
-
case 1:
30763
-
switch (Field_r_Slot_inst_get (insn))
30764
-
{
30765
-
case 0:
30766
-
return OPCODE_BF;
30767
-
case 1:
30768
-
return OPCODE_BT;
30769
-
case 8:
30770
-
return OPCODE_LOOP;
30771
-
case 9:
30772
-
return OPCODE_LOOPNEZ;
30773
-
case 10:
30774
-
return OPCODE_LOOPGTZ;
30775
-
}
30776
-
break;
30777
-
case 2:
30778
-
return OPCODE_BLTUI;
30779
-
case 3:
30780
-
return OPCODE_BGEUI;
30600
+
if (Field_r_Slot_inst_get (insn) == 0)
30601
+
return OPCODE_BF;
30602
+
if (Field_r_Slot_inst_get (insn) == 1)
30603
+
return OPCODE_BT;
30604
+
if (Field_r_Slot_inst_get (insn) == 8)
30605
+
return OPCODE_LOOP;
30606
+
if (Field_r_Slot_inst_get (insn) == 9)
30607
+
return OPCODE_LOOPNEZ;
30608
+
if (Field_r_Slot_inst_get (insn) == 10)
30609
+
return OPCODE_LOOPGTZ;
30781
30610
}
30782
-
break;
30611
+
if (Field_m_Slot_inst_get (insn) == 2)
30612
+
return OPCODE_BLTUI;
30613
+
if (Field_m_Slot_inst_get (insn) == 3)
30614
+
return OPCODE_BGEUI;
30783
30615
}
30784
-
break;
30785
-
case 7:
30786
-
switch (Field_r_Slot_inst_get (insn))
30787
-
{
30788
-
case 0:
30789
-
return OPCODE_BNONE;
30790
-
case 1:
30791
-
return OPCODE_BEQ;
30792
-
case 2:
30793
-
return OPCODE_BLT;
30794
-
case 3:
30795
-
return OPCODE_BLTU;
30796
-
case 4:
30797
-
return OPCODE_BALL;
30798
-
case 5:
30799
-
return OPCODE_BBC;
30800
-
case 6:
30801
-
case 7:
30802
-
return OPCODE_BBCI;
30803
-
case 8:
30804
-
return OPCODE_BANY;
30805
-
case 9:
30806
-
return OPCODE_BNE;
30807
-
case 10:
30808
-
return OPCODE_BGE;
30809
-
case 11:
30810
-
return OPCODE_BGEU;
30811
-
case 12:
30812
-
return OPCODE_BNALL;
30813
-
case 13:
30814
-
return OPCODE_BBS;
30815
-
case 14:
30816
-
case 15:
30817
-
return OPCODE_BBSI;
30818
-
}
30819
-
break;
30616
+
}
30617
+
if (Field_op0_Slot_inst_get (insn) == 7)
30618
+
{
30619
+
if (Field_r_Slot_inst_get (insn) == 0)
30620
+
return OPCODE_BNONE;
30621
+
if (Field_r_Slot_inst_get (insn) == 1)
30622
+
return OPCODE_BEQ;
30623
+
if (Field_r_Slot_inst_get (insn) == 2)
30624
+
return OPCODE_BLT;
30625
+
if (Field_r_Slot_inst_get (insn) == 3)
30626
+
return OPCODE_BLTU;
30627
+
if (Field_r_Slot_inst_get (insn) == 4)
30628
+
return OPCODE_BALL;
30629
+
if (Field_r_Slot_inst_get (insn) == 5)
30630
+
return OPCODE_BBC;
30631
+
if ((Field_r_Slot_inst_get (insn) == 6 ||
30632
+
Field_r_Slot_inst_get (insn) == 7))
30633
+
return OPCODE_BBCI;
30634
+
if (Field_r_Slot_inst_get (insn) == 8)
30635
+
return OPCODE_BANY;
30636
+
if (Field_r_Slot_inst_get (insn) == 9)
30637
+
return OPCODE_BNE;
30638
+
if (Field_r_Slot_inst_get (insn) == 10)
30639
+
return OPCODE_BGE;
30640
+
if (Field_r_Slot_inst_get (insn) == 11)
30641
+
return OPCODE_BGEU;
30642
+
if (Field_r_Slot_inst_get (insn) == 12)
30643
+
return OPCODE_BNALL;
30644
+
if (Field_r_Slot_inst_get (insn) == 13)
30645
+
return OPCODE_BBS;
30646
+
if ((Field_r_Slot_inst_get (insn) == 14 ||
30647
+
Field_r_Slot_inst_get (insn) == 15))
30648
+
return OPCODE_BBSI;
30820
30649
}
30821
30650
return XTENSA_UNDEFINED;
30822
30651
}
···
30824
30653
static int
30825
30654
Slot_inst16b_decode (const xtensa_insnbuf insn)
30826
30655
{
30827
-
switch (Field_op0_Slot_inst16b_get (insn))
30656
+
if (Field_op0_Slot_inst16b_get (insn) == 12)
30828
30657
{
30829
-
case 12:
30830
-
switch (Field_i_Slot_inst16b_get (insn))
30658
+
if (Field_i_Slot_inst16b_get (insn) == 0)
30659
+
return OPCODE_MOVI_N;
30660
+
if (Field_i_Slot_inst16b_get (insn) == 1)
30831
30661
{
30832
-
case 0:
30833
-
return OPCODE_MOVI_N;
30834
-
case 1:
30835
-
switch (Field_z_Slot_inst16b_get (insn))
30836
-
{
30837
-
case 0:
30838
-
return OPCODE_BEQZ_N;
30839
-
case 1:
30840
-
return OPCODE_BNEZ_N;
30841
-
}
30842
-
break;
30662
+
if (Field_z_Slot_inst16b_get (insn) == 0)
30663
+
return OPCODE_BEQZ_N;
30664
+
if (Field_z_Slot_inst16b_get (insn) == 1)
30665
+
return OPCODE_BNEZ_N;
30843
30666
}
30844
-
break;
30845
-
case 13:
30846
-
switch (Field_r_Slot_inst16b_get (insn))
30667
+
}
30668
+
if (Field_op0_Slot_inst16b_get (insn) == 13)
30669
+
{
30670
+
if (Field_r_Slot_inst16b_get (insn) == 0)
30671
+
return OPCODE_MOV_N;
30672
+
if (Field_r_Slot_inst16b_get (insn) == 15)
30847
30673
{
30848
-
case 0:
30849
-
return OPCODE_MOV_N;
30850
-
case 15:
30851
-
switch (Field_t_Slot_inst16b_get (insn))
30852
-
{
30853
-
case 0:
30854
-
return OPCODE_RET_N;
30855
-
case 1:
30856
-
return OPCODE_RETW_N;
30857
-
case 2:
30858
-
return OPCODE_BREAK_N;
30859
-
case 3:
30860
-
if (Field_s_Slot_inst16b_get (insn) == 0)
30861
-
return OPCODE_NOP_N;
30862
-
break;
30863
-
case 6:
30864
-
if (Field_s_Slot_inst16b_get (insn) == 0)
30865
-
return OPCODE_ILL_N;
30866
-
break;
30867
-
}
30868
-
break;
30674
+
if (Field_t_Slot_inst16b_get (insn) == 0)
30675
+
return OPCODE_RET_N;
30676
+
if (Field_t_Slot_inst16b_get (insn) == 1)
30677
+
return OPCODE_RETW_N;
30678
+
if (Field_t_Slot_inst16b_get (insn) == 2)
30679
+
return OPCODE_BREAK_N;
30680
+
if (Field_t_Slot_inst16b_get (insn) == 3 &&
30681
+
Field_s_Slot_inst16b_get (insn) == 0)
30682
+
return OPCODE_NOP_N;
30683
+
if (Field_t_Slot_inst16b_get (insn) == 6 &&
30684
+
Field_s_Slot_inst16b_get (insn) == 0)
30685
+
return OPCODE_ILL_N;
30869
30686
}
30870
-
break;
30871
30687
}
30872
30688
return XTENSA_UNDEFINED;
30873
30689
}
···
30875
30691
static int
30876
30692
Slot_inst16a_decode (const xtensa_insnbuf insn)
30877
30693
{
30878
-
switch (Field_op0_Slot_inst16a_get (insn))
30879
-
{
30880
-
case 8:
30881
-
return OPCODE_L32I_N;
30882
-
case 9:
30883
-
return OPCODE_S32I_N;
30884
-
case 10:
30885
-
return OPCODE_ADD_N;
30886
-
case 11:
30887
-
return OPCODE_ADDI_N;
30888
-
}
30694
+
if (Field_op0_Slot_inst16a_get (insn) == 8)
30695
+
return OPCODE_L32I_N;
30696
+
if (Field_op0_Slot_inst16a_get (insn) == 9)
30697
+
return OPCODE_S32I_N;
30698
+
if (Field_op0_Slot_inst16a_get (insn) == 10)
30699
+
return OPCODE_ADD_N;
30700
+
if (Field_op0_Slot_inst16a_get (insn) == 11)
30701
+
return OPCODE_ADDI_N;
30889
30702
return XTENSA_UNDEFINED;
30890
30703
}
30891
30704
···
30898
30711
if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
30899
30712
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30900
30713
return OPCODE_EXTUI;
30901
-
switch (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn))
30902
-
{
30903
-
case 6:
30904
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30905
-
return OPCODE_BGEZ;
30906
-
break;
30907
-
case 7:
30908
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30909
-
return OPCODE_BLTZ;
30910
-
break;
30911
-
case 8:
30912
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30913
-
return OPCODE_BEQZ;
30914
-
break;
30915
-
case 9:
30916
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30917
-
return OPCODE_BNEZ;
30918
-
break;
30919
-
case 10:
30920
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30921
-
return OPCODE_MOVI;
30922
-
break;
30923
-
}
30924
-
switch (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn))
30925
-
{
30926
-
case 88:
30927
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30928
-
return OPCODE_SRAI;
30929
-
break;
30930
-
case 96:
30931
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30932
-
return OPCODE_SLLI;
30933
-
break;
30934
-
case 123:
30935
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30936
-
Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
30937
-
return OPCODE_AE_MOVTQ56;
30938
-
break;
30939
-
}
30714
+
if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
30715
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30716
+
return OPCODE_BGEZ;
30717
+
if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
30718
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30719
+
return OPCODE_BLTZ;
30720
+
if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 &&
30721
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30722
+
return OPCODE_BEQZ;
30723
+
if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 &&
30724
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30725
+
return OPCODE_BNEZ;
30726
+
if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
30727
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30728
+
return OPCODE_MOVI;
30729
+
if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 &&
30730
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30731
+
return OPCODE_SRAI;
30732
+
if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 &&
30733
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30734
+
return OPCODE_SLLI;
30735
+
if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
30736
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
30737
+
Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
30738
+
return OPCODE_AE_MOVTQ56;
30940
30739
if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
30941
30740
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30942
30741
return OPCODE_AE_CVTP24A16X2_HH;
···
31160
30959
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31161
30960
Field_s_Slot_ae_slot0_get (insn) == 0)
31162
30961
return OPCODE_ALL8;
31163
-
switch (Field_ftsf293_Slot_ae_slot0_get (insn))
31164
-
{
31165
-
case 0:
31166
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31167
-
return OPCODE_BBCI;
31168
-
break;
31169
-
case 1:
31170
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31171
-
return OPCODE_BBSI;
31172
-
break;
31173
-
}
30962
+
if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 &&
30963
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
30964
+
return OPCODE_BBCI;
30965
+
if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 &&
30966
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
30967
+
return OPCODE_BBSI;
31174
30968
if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
31175
30969
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31176
30970
Field_s_Slot_ae_slot0_get (insn) == 0)
···
31188
30982
if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
31189
30983
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31190
30984
return OPCODE_AE_SQ56S_IU;
31191
-
switch (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn))
31192
-
{
31193
-
case 964:
31194
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31195
-
return OPCODE_AE_SLLIQ56;
31196
-
break;
31197
-
case 965:
31198
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31199
-
return OPCODE_AE_SRAIQ56;
31200
-
break;
31201
-
case 966:
31202
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31203
-
return OPCODE_AE_SRLIQ56;
31204
-
break;
31205
-
case 968:
31206
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31207
-
return OPCODE_AE_SLLISQ56S;
31208
-
break;
31209
-
}
31210
-
switch (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn))
31211
-
{
31212
-
case 3868:
31213
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31214
-
return OPCODE_ABS;
31215
-
break;
31216
-
case 3869:
31217
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31218
-
return OPCODE_NEG;
31219
-
break;
31220
-
case 3870:
31221
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31222
-
return OPCODE_SRA;
31223
-
break;
31224
-
case 3871:
31225
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31226
-
return OPCODE_SRL;
31227
-
break;
31228
-
}
31229
-
switch (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn))
31230
-
{
31231
-
case 7752:
31232
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31233
-
Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31234
-
return OPCODE_AE_MOVP48;
31235
-
break;
31236
-
case 7753:
31237
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31238
-
Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
31239
-
return OPCODE_ANY4;
31240
-
break;
31241
-
}
30985
+
if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 &&
30986
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30987
+
return OPCODE_AE_SLLIQ56;
30988
+
if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 &&
30989
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30990
+
return OPCODE_AE_SRAIQ56;
30991
+
if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 &&
30992
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30993
+
return OPCODE_AE_SRLIQ56;
30994
+
if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 &&
30995
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30996
+
return OPCODE_AE_SLLISQ56S;
30997
+
if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 &&
30998
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
30999
+
return OPCODE_ABS;
31000
+
if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 &&
31001
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31002
+
return OPCODE_NEG;
31003
+
if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 &&
31004
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31005
+
return OPCODE_SRA;
31006
+
if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 &&
31007
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31008
+
return OPCODE_SRL;
31009
+
if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 &&
31010
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31011
+
Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
31012
+
return OPCODE_AE_MOVP48;
31013
+
if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 &&
31014
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31015
+
Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
31016
+
return OPCODE_ANY4;
31242
31017
if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
31243
31018
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31244
31019
Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
···
31328
31103
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31329
31104
Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
31330
31105
return OPCODE_AE_SQ32F_XU;
31331
-
switch (Field_imm8_Slot_ae_slot0_get (insn))
31332
-
{
31333
-
case 178:
31334
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31335
-
return OPCODE_ADD;
31336
-
break;
31337
-
case 179:
31338
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31339
-
return OPCODE_ADDX8;
31340
-
break;
31341
-
case 180:
31342
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31343
-
return OPCODE_ADDX2;
31344
-
break;
31345
-
case 181:
31346
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31347
-
return OPCODE_AND;
31348
-
break;
31349
-
case 182:
31350
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31351
-
return OPCODE_ANDB;
31352
-
break;
31353
-
case 183:
31354
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31355
-
return OPCODE_ANDBC;
31356
-
break;
31357
-
case 184:
31358
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31359
-
return OPCODE_ADDX4;
31360
-
break;
31361
-
case 185:
31362
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31363
-
return OPCODE_CLAMPS;
31364
-
break;
31365
-
case 186:
31366
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31367
-
return OPCODE_MAX;
31368
-
break;
31369
-
case 187:
31370
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31371
-
return OPCODE_MIN;
31372
-
break;
31373
-
case 188:
31374
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31375
-
return OPCODE_MAXU;
31376
-
break;
31377
-
case 189:
31378
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31379
-
return OPCODE_MINU;
31380
-
break;
31381
-
case 190:
31382
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31383
-
return OPCODE_MOVEQZ;
31384
-
break;
31385
-
case 191:
31386
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31387
-
return OPCODE_MOVF;
31388
-
break;
31389
-
case 194:
31390
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31391
-
return OPCODE_MOVGEZ;
31392
-
break;
31393
-
case 195:
31394
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31395
-
return OPCODE_ORB;
31396
-
break;
31397
-
case 196:
31398
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31399
-
return OPCODE_MOVLTZ;
31400
-
break;
31401
-
case 197:
31402
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31403
-
return OPCODE_ORBC;
31404
-
break;
31405
-
case 198:
31406
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31407
-
return OPCODE_SEXT;
31408
-
break;
31409
-
case 199:
31410
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31411
-
return OPCODE_SRC;
31412
-
break;
31413
-
case 200:
31414
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31415
-
return OPCODE_MOVNEZ;
31416
-
break;
31417
-
case 201:
31418
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31419
-
return OPCODE_SRLI;
31420
-
break;
31421
-
case 202:
31422
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31423
-
return OPCODE_SUB;
31424
-
break;
31425
-
case 203:
31426
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31427
-
return OPCODE_SUBX4;
31428
-
break;
31429
-
case 204:
31430
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31431
-
return OPCODE_SUBX2;
31432
-
break;
31433
-
case 205:
31434
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31435
-
return OPCODE_SUBX8;
31436
-
break;
31437
-
case 206:
31438
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31439
-
return OPCODE_XOR;
31440
-
break;
31441
-
case 207:
31442
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31443
-
return OPCODE_XORB;
31444
-
break;
31445
-
case 208:
31446
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31447
-
return OPCODE_MOVT;
31448
-
break;
31449
-
case 224:
31450
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31451
-
return OPCODE_OR;
31452
-
break;
31453
-
case 244:
31454
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31455
-
Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
31456
-
return OPCODE_AE_SQ32F_X;
31457
-
break;
31458
-
}
31106
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 178 &&
31107
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31108
+
return OPCODE_ADD;
31109
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 179 &&
31110
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31111
+
return OPCODE_ADDX8;
31112
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 180 &&
31113
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31114
+
return OPCODE_ADDX2;
31115
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 181 &&
31116
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31117
+
return OPCODE_AND;
31118
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 182 &&
31119
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31120
+
return OPCODE_ANDB;
31121
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
31122
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31123
+
return OPCODE_ANDBC;
31124
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 184 &&
31125
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31126
+
return OPCODE_ADDX4;
31127
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 185 &&
31128
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31129
+
return OPCODE_CLAMPS;
31130
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 186 &&
31131
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31132
+
return OPCODE_MAX;
31133
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 187 &&
31134
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31135
+
return OPCODE_MIN;
31136
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 188 &&
31137
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31138
+
return OPCODE_MAXU;
31139
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 189 &&
31140
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31141
+
return OPCODE_MINU;
31142
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 190 &&
31143
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31144
+
return OPCODE_MOVEQZ;
31145
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 191 &&
31146
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31147
+
return OPCODE_MOVF;
31148
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 194 &&
31149
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31150
+
return OPCODE_MOVGEZ;
31151
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 195 &&
31152
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31153
+
return OPCODE_ORB;
31154
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 196 &&
31155
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31156
+
return OPCODE_MOVLTZ;
31157
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 197 &&
31158
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31159
+
return OPCODE_ORBC;
31160
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 198 &&
31161
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31162
+
return OPCODE_SEXT;
31163
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
31164
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31165
+
return OPCODE_SRC;
31166
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 200 &&
31167
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31168
+
return OPCODE_MOVNEZ;
31169
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 201 &&
31170
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31171
+
return OPCODE_SRLI;
31172
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 202 &&
31173
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31174
+
return OPCODE_SUB;
31175
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 203 &&
31176
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31177
+
return OPCODE_SUBX4;
31178
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 204 &&
31179
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31180
+
return OPCODE_SUBX2;
31181
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 205 &&
31182
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31183
+
return OPCODE_SUBX8;
31184
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 206 &&
31185
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31186
+
return OPCODE_XOR;
31187
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 207 &&
31188
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31189
+
return OPCODE_XORB;
31190
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 208 &&
31191
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31192
+
return OPCODE_MOVT;
31193
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 224 &&
31194
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
31195
+
return OPCODE_OR;
31196
+
if (Field_imm8_Slot_ae_slot0_get (insn) == 244 &&
31197
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
31198
+
Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
31199
+
return OPCODE_AE_SQ32F_X;
31459
31200
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
31460
31201
return OPCODE_L32R;
31461
-
switch (Field_r_Slot_ae_slot0_get (insn))
31462
-
{
31463
-
case 0:
31464
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31465
-
return OPCODE_BNE;
31466
-
break;
31467
-
case 1:
31468
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31469
-
return OPCODE_BNONE;
31470
-
break;
31471
-
case 2:
31472
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31473
-
return OPCODE_L16SI;
31474
-
break;
31475
-
case 3:
31476
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31477
-
return OPCODE_L8UI;
31478
-
break;
31479
-
case 4:
31480
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31481
-
return OPCODE_ADDI;
31482
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31483
-
return OPCODE_L16UI;
31484
-
break;
31485
-
case 5:
31486
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31487
-
return OPCODE_BALL;
31488
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31489
-
return OPCODE_S16I;
31490
-
break;
31491
-
case 6:
31492
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31493
-
return OPCODE_BANY;
31494
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31495
-
return OPCODE_S32I;
31496
-
break;
31497
-
case 7:
31498
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31499
-
return OPCODE_BBC;
31500
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31501
-
return OPCODE_S8I;
31502
-
break;
31503
-
case 8:
31504
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31505
-
return OPCODE_ADDMI;
31506
-
break;
31507
-
case 9:
31508
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31509
-
return OPCODE_BBS;
31510
-
break;
31511
-
case 10:
31512
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31513
-
return OPCODE_BEQ;
31514
-
break;
31515
-
case 11:
31516
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31517
-
return OPCODE_BGEU;
31518
-
break;
31519
-
case 12:
31520
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31521
-
return OPCODE_BGE;
31522
-
break;
31523
-
case 13:
31524
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31525
-
return OPCODE_BLT;
31526
-
break;
31527
-
case 14:
31528
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31529
-
return OPCODE_BLTU;
31530
-
break;
31531
-
case 15:
31532
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31533
-
return OPCODE_BNALL;
31534
-
break;
31535
-
}
31536
-
switch (Field_t_Slot_ae_slot0_get (insn))
31537
-
{
31538
-
case 0:
31539
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31540
-
return OPCODE_BEQI;
31541
-
break;
31542
-
case 1:
31543
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31544
-
return OPCODE_BGEI;
31545
-
break;
31546
-
case 2:
31547
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31548
-
return OPCODE_BGEUI;
31549
-
break;
31550
-
case 3:
31551
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31552
-
return OPCODE_BNEI;
31553
-
break;
31554
-
case 4:
31555
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31556
-
return OPCODE_BLTI;
31557
-
break;
31558
-
case 5:
31559
-
if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31560
-
Field_r_Slot_ae_slot0_get (insn) == 0)
31561
-
return OPCODE_BF;
31562
-
break;
31563
-
}
31202
+
if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
31203
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31204
+
return OPCODE_BNE;
31205
+
if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
31206
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31207
+
return OPCODE_BNONE;
31208
+
if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
31209
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31210
+
return OPCODE_L16SI;
31211
+
if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
31212
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31213
+
return OPCODE_L8UI;
31214
+
if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
31215
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31216
+
return OPCODE_ADDI;
31217
+
if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
31218
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31219
+
return OPCODE_L16UI;
31220
+
if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
31221
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31222
+
return OPCODE_BALL;
31223
+
if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
31224
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31225
+
return OPCODE_S16I;
31226
+
if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
31227
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31228
+
return OPCODE_BANY;
31229
+
if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
31230
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31231
+
return OPCODE_S32I;
31232
+
if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
31233
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31234
+
return OPCODE_BBC;
31235
+
if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
31236
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
31237
+
return OPCODE_S8I;
31238
+
if (Field_r_Slot_ae_slot0_get (insn) == 8 &&
31239
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31240
+
return OPCODE_ADDMI;
31241
+
if (Field_r_Slot_ae_slot0_get (insn) == 9 &&
31242
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31243
+
return OPCODE_BBS;
31244
+
if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
31245
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31246
+
return OPCODE_BEQ;
31247
+
if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
31248
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31249
+
return OPCODE_BGEU;
31250
+
if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
31251
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31252
+
return OPCODE_BGE;
31253
+
if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
31254
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31255
+
return OPCODE_BLT;
31256
+
if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
31257
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31258
+
return OPCODE_BLTU;
31259
+
if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
31260
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
31261
+
return OPCODE_BNALL;
31262
+
if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
31263
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31264
+
return OPCODE_BEQI;
31265
+
if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
31266
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31267
+
return OPCODE_BGEI;
31268
+
if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
31269
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31270
+
return OPCODE_BGEUI;
31271
+
if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
31272
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31273
+
return OPCODE_BNEI;
31274
+
if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
31275
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
31276
+
return OPCODE_BLTI;
31277
+
if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
31278
+
Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
31279
+
Field_r_Slot_ae_slot0_get (insn) == 0)
31280
+
return OPCODE_BF;
31564
31281
return XTENSA_UNDEFINED;
31565
31282
}
31566
31283
···
31958
31675
if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
31959
31676
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31960
31677
return OPCODE_AE_SUBP24;
31961
-
switch (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn))
31962
-
{
31963
-
case 8:
31964
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31965
-
return OPCODE_AE_SLLIP24;
31966
-
break;
31967
-
case 9:
31968
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31969
-
return OPCODE_AE_SRAIP24;
31970
-
break;
31971
-
case 10:
31972
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31973
-
return OPCODE_AE_SRLIP24;
31974
-
break;
31975
-
}
31678
+
if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
31679
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31680
+
return OPCODE_AE_SLLIP24;
31681
+
if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
31682
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31683
+
return OPCODE_AE_SRAIP24;
31684
+
if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
31685
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31686
+
return OPCODE_AE_SRLIP24;
31976
31687
if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
31977
31688
Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
31978
31689
return OPCODE_AE_MULAFQ32SP16S_L;
···
32148
31859
Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
32149
31860
Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
32150
31861
return OPCODE_AE_ABSP24;
32151
-
switch (Field_t_Slot_ae_slot1_get (insn))
32152
-
{
32153
-
case 0:
32154
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32155
-
return OPCODE_AE_MULZAAFQ32SP16S_HH;
32156
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32157
-
return OPCODE_AE_MULZASFQ32SP16U_LH;
32158
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32159
-
return OPCODE_AE_MULZSAQ32SP16S_LL;
32160
-
break;
32161
-
case 1:
32162
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32163
-
return OPCODE_AE_MULZAAFQ32SP16S_LH;
32164
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32165
-
return OPCODE_AE_MULZASFQ32SP16U_LL;
32166
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32167
-
return OPCODE_AE_MULZSAQ32SP16U_HH;
32168
-
break;
32169
-
case 2:
32170
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32171
-
return OPCODE_AE_MULZAAFQ32SP16S_LL;
32172
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32173
-
return OPCODE_AE_MULZASQ32SP16S_HH;
32174
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32175
-
return OPCODE_AE_MULZSAQ32SP16U_LH;
32176
-
break;
32177
-
case 3:
32178
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32179
-
return OPCODE_AE_MULZAAFQ32SP16U_LL;
32180
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32181
-
return OPCODE_AE_MULZASQ32SP16U_HH;
32182
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32183
-
return OPCODE_AE_MULZSSFQ32SP16S_LH;
32184
-
break;
32185
-
case 4:
32186
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32187
-
return OPCODE_AE_MULZAAFQ32SP16U_HH;
32188
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32189
-
return OPCODE_AE_MULZASQ32SP16S_LH;
32190
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32191
-
return OPCODE_AE_MULZSAQ32SP16U_LL;
32192
-
break;
32193
-
case 5:
32194
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32195
-
return OPCODE_AE_MULZAAQ32SP16S_HH;
32196
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32197
-
return OPCODE_AE_MULZASQ32SP16U_LH;
32198
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32199
-
return OPCODE_AE_MULZSSFQ32SP16S_LL;
32200
-
break;
32201
-
case 6:
32202
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32203
-
return OPCODE_AE_MULZAAQ32SP16S_LH;
32204
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32205
-
return OPCODE_AE_MULZASQ32SP16U_LL;
32206
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32207
-
return OPCODE_AE_MULZSSFQ32SP16U_HH;
32208
-
break;
32209
-
case 7:
32210
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32211
-
return OPCODE_AE_MULZAAQ32SP16S_LL;
32212
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32213
-
return OPCODE_AE_MULZSAFQ32SP16S_HH;
32214
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32215
-
return OPCODE_AE_MULZSSFQ32SP16U_LH;
32216
-
break;
32217
-
case 8:
32218
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32219
-
return OPCODE_AE_MULZAAFQ32SP16U_LH;
32220
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32221
-
return OPCODE_AE_MULZASQ32SP16S_LL;
32222
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32223
-
return OPCODE_AE_MULZSSFQ32SP16S_HH;
32224
-
break;
32225
-
case 9:
32226
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32227
-
return OPCODE_AE_MULZAAQ32SP16U_HH;
32228
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32229
-
return OPCODE_AE_MULZSAFQ32SP16S_LH;
32230
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32231
-
return OPCODE_AE_MULZSSFQ32SP16U_LL;
32232
-
break;
32233
-
case 10:
32234
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32235
-
return OPCODE_AE_MULZAAQ32SP16U_LH;
32236
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32237
-
return OPCODE_AE_MULZSAFQ32SP16S_LL;
32238
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32239
-
return OPCODE_AE_MULZSSQ32SP16S_HH;
32240
-
break;
32241
-
case 11:
32242
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32243
-
return OPCODE_AE_MULZASFQ32SP16S_HH;
32244
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32245
-
return OPCODE_AE_MULZSAFQ32SP16U_LH;
32246
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32247
-
return OPCODE_AE_MULZSSQ32SP16S_LL;
32248
-
break;
32249
-
case 12:
32250
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32251
-
return OPCODE_AE_MULZAAQ32SP16U_LL;
32252
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32253
-
return OPCODE_AE_MULZSAFQ32SP16U_HH;
32254
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32255
-
return OPCODE_AE_MULZSSQ32SP16S_LH;
32256
-
break;
32257
-
case 13:
32258
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32259
-
return OPCODE_AE_MULZASFQ32SP16S_LH;
32260
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32261
-
return OPCODE_AE_MULZSAFQ32SP16U_LL;
32262
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32263
-
return OPCODE_AE_MULZSSQ32SP16U_HH;
32264
-
break;
32265
-
case 14:
32266
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32267
-
return OPCODE_AE_MULZASFQ32SP16S_LL;
32268
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32269
-
return OPCODE_AE_MULZSAQ32SP16S_HH;
32270
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32271
-
return OPCODE_AE_MULZSSQ32SP16U_LH;
32272
-
break;
32273
-
case 15:
32274
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
32275
-
return OPCODE_AE_MULZASFQ32SP16U_HH;
32276
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32277
-
return OPCODE_AE_MULZSAQ32SP16S_LH;
32278
-
if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32279
-
return OPCODE_AE_MULZSSQ32SP16U_LL;
32280
-
break;
32281
-
}
31862
+
if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31863
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31864
+
return OPCODE_AE_MULZAAFQ32SP16S_HH;
31865
+
if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31866
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31867
+
return OPCODE_AE_MULZASFQ32SP16U_LH;
31868
+
if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
31869
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31870
+
return OPCODE_AE_MULZSAQ32SP16S_LL;
31871
+
if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31872
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31873
+
return OPCODE_AE_MULZAAFQ32SP16S_LH;
31874
+
if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31875
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31876
+
return OPCODE_AE_MULZASFQ32SP16U_LL;
31877
+
if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
31878
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31879
+
return OPCODE_AE_MULZSAQ32SP16U_HH;
31880
+
if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31881
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31882
+
return OPCODE_AE_MULZAAFQ32SP16S_LL;
31883
+
if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31884
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31885
+
return OPCODE_AE_MULZASQ32SP16S_HH;
31886
+
if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
31887
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31888
+
return OPCODE_AE_MULZSAQ32SP16U_LH;
31889
+
if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31890
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31891
+
return OPCODE_AE_MULZAAFQ32SP16U_LL;
31892
+
if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31893
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31894
+
return OPCODE_AE_MULZASQ32SP16U_HH;
31895
+
if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
31896
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31897
+
return OPCODE_AE_MULZSSFQ32SP16S_LH;
31898
+
if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31899
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31900
+
return OPCODE_AE_MULZAAFQ32SP16U_HH;
31901
+
if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31902
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31903
+
return OPCODE_AE_MULZASQ32SP16S_LH;
31904
+
if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
31905
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31906
+
return OPCODE_AE_MULZSAQ32SP16U_LL;
31907
+
if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31908
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31909
+
return OPCODE_AE_MULZAAQ32SP16S_HH;
31910
+
if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31911
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31912
+
return OPCODE_AE_MULZASQ32SP16U_LH;
31913
+
if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
31914
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31915
+
return OPCODE_AE_MULZSSFQ32SP16S_LL;
31916
+
if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31917
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31918
+
return OPCODE_AE_MULZAAQ32SP16S_LH;
31919
+
if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31920
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31921
+
return OPCODE_AE_MULZASQ32SP16U_LL;
31922
+
if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
31923
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31924
+
return OPCODE_AE_MULZSSFQ32SP16U_HH;
31925
+
if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31926
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31927
+
return OPCODE_AE_MULZAAQ32SP16S_LL;
31928
+
if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31929
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31930
+
return OPCODE_AE_MULZSAFQ32SP16S_HH;
31931
+
if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
31932
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31933
+
return OPCODE_AE_MULZSSFQ32SP16U_LH;
31934
+
if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31935
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31936
+
return OPCODE_AE_MULZAAFQ32SP16U_LH;
31937
+
if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31938
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31939
+
return OPCODE_AE_MULZASQ32SP16S_LL;
31940
+
if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
31941
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31942
+
return OPCODE_AE_MULZSSFQ32SP16S_HH;
31943
+
if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31944
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31945
+
return OPCODE_AE_MULZAAQ32SP16U_HH;
31946
+
if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31947
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31948
+
return OPCODE_AE_MULZSAFQ32SP16S_LH;
31949
+
if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
31950
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31951
+
return OPCODE_AE_MULZSSFQ32SP16U_LL;
31952
+
if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31953
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31954
+
return OPCODE_AE_MULZAAQ32SP16U_LH;
31955
+
if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31956
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31957
+
return OPCODE_AE_MULZSAFQ32SP16S_LL;
31958
+
if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
31959
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31960
+
return OPCODE_AE_MULZSSQ32SP16S_HH;
31961
+
if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31962
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31963
+
return OPCODE_AE_MULZASFQ32SP16S_HH;
31964
+
if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31965
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31966
+
return OPCODE_AE_MULZSAFQ32SP16U_LH;
31967
+
if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
31968
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31969
+
return OPCODE_AE_MULZSSQ32SP16S_LL;
31970
+
if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31971
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31972
+
return OPCODE_AE_MULZAAQ32SP16U_LL;
31973
+
if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31974
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31975
+
return OPCODE_AE_MULZSAFQ32SP16U_HH;
31976
+
if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
31977
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31978
+
return OPCODE_AE_MULZSSQ32SP16S_LH;
31979
+
if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31980
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31981
+
return OPCODE_AE_MULZASFQ32SP16S_LH;
31982
+
if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31983
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31984
+
return OPCODE_AE_MULZSAFQ32SP16U_LL;
31985
+
if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
31986
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31987
+
return OPCODE_AE_MULZSSQ32SP16U_HH;
31988
+
if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31989
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31990
+
return OPCODE_AE_MULZASFQ32SP16S_LL;
31991
+
if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31992
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
31993
+
return OPCODE_AE_MULZSAQ32SP16S_HH;
31994
+
if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
31995
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
31996
+
return OPCODE_AE_MULZSSQ32SP16U_LH;
31997
+
if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
31998
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
31999
+
return OPCODE_AE_MULZASFQ32SP16U_HH;
32000
+
if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
32001
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
32002
+
return OPCODE_AE_MULZSAQ32SP16S_LH;
32003
+
if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
32004
+
Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
32005
+
return OPCODE_AE_MULZSSQ32SP16U_LL;
32282
32006
return XTENSA_UNDEFINED;
32283
32007
}
32284
32008
···
32418
32142
Field_ae_r20_Slot_inst_get,
32419
32143
Field_ae_r10_Slot_inst_get,
32420
32144
Field_ae_s20_Slot_inst_get,
32145
+
Field_ae_fld_ohba_Slot_inst_get,
32146
+
Field_ae_fld_ohba2_Slot_inst_get,
32421
32147
0,
32422
32148
Field_ftsf12_Slot_inst_get,
32423
32149
Field_ftsf13_Slot_inst_get,
···
32809
32535
Field_ae_r20_Slot_inst_set,
32810
32536
Field_ae_r10_Slot_inst_set,
32811
32537
Field_ae_s20_Slot_inst_set,
32538
+
Field_ae_fld_ohba_Slot_inst_set,
32539
+
Field_ae_fld_ohba2_Slot_inst_set,
32812
32540
0,
32813
32541
Field_ftsf12_Slot_inst_set,
32814
32542
Field_ftsf13_Slot_inst_set,
···
33190
32918
Field_t8_Slot_inst16a_get,
33191
32919
Field_s8_Slot_inst16a_get,
33192
32920
Field_r8_Slot_inst16a_get,
32921
+
0,
33193
32922
0,
33194
32923
0,
33195
32924
0,
···
33525
33254
0,
33526
33255
0,
33527
33256
0,
33257
+
0,
33528
33258
Implicit_Field_ar0_get,
33529
33259
Implicit_Field_ar4_get,
33530
33260
Implicit_Field_ar8_get,
···
33581
33311
Field_t8_Slot_inst16a_set,
33582
33312
Field_s8_Slot_inst16a_set,
33583
33313
Field_r8_Slot_inst16a_set,
33314
+
0,
33315
+
0,
33584
33316
0,
33585
33317
0,
33586
33318
0,
···
34307
34039
0,
34308
34040
0,
34309
34041
0,
34042
+
0,
34043
+
0,
34310
34044
Implicit_Field_ar0_get,
34311
34045
Implicit_Field_ar4_get,
34312
34046
Implicit_Field_ar8_get,
···
34363
34097
Field_t8_Slot_inst16b_set,
34364
34098
Field_s8_Slot_inst16b_set,
34365
34099
Field_r8_Slot_inst16b_set,
34100
+
0,
34366
34101
0,
34367
34102
0,
34368
34103
0,
···
34698
34433
0,
34699
34434
0,
34700
34435
0,
34436
+
0,
34701
34437
Implicit_Field_set,
34702
34438
Implicit_Field_set,
34703
34439
Implicit_Field_set,
···
34764
34500
Field_ae_r20_Slot_ae_slot1_get,
34765
34501
Field_ae_r10_Slot_ae_slot1_get,
34766
34502
Field_ae_s20_Slot_ae_slot1_get,
34503
+
0,
34504
+
0,
34767
34505
Field_op0_s3_Slot_ae_slot1_get,
34768
34506
Field_ftsf12_Slot_ae_slot1_get,
34769
34507
Field_ftsf13_Slot_ae_slot1_get,
···
35155
34893
Field_ae_r20_Slot_ae_slot1_set,
35156
34894
Field_ae_r10_Slot_ae_slot1_set,
35157
34895
Field_ae_s20_Slot_ae_slot1_set,
34896
+
0,
34897
+
0,
35158
34898
Field_op0_s3_Slot_ae_slot1_set,
35159
34899
Field_ftsf12_Slot_ae_slot1_set,
35160
34900
Field_ftsf13_Slot_ae_slot1_set,
···
35745
35485
0,
35746
35486
0,
35747
35487
0,
35488
+
0,
35489
+
0,
35748
35490
Field_op0_s4_Slot_ae_slot0_get,
35749
35491
Field_ftsf212ae_slot0_Slot_ae_slot0_get,
35750
35492
Field_ftsf213ae_slot0_Slot_ae_slot0_get,
···
35937
35679
Field_ae_r20_Slot_ae_slot0_set,
35938
35680
Field_ae_r10_Slot_ae_slot0_set,
35939
35681
Field_ae_s20_Slot_ae_slot0_set,
35682
+
0,
35683
+
0,
35940
35684
0,
35941
35685
0,
35942
35686
0,
···
36356
36100
return -1;
36357
36101
}
36358
36102
36359
-
static int length_table[16] = {
36103
+
static int length_table[256] = {
36104
+
3,
36105
+
3,
36106
+
3,
36107
+
3,
36108
+
3,
36109
+
3,
36110
+
3,
36111
+
3,
36112
+
2,
36113
+
2,
36114
+
2,
36115
+
2,
36116
+
2,
36117
+
2,
36118
+
-1,
36119
+
8,
36120
+
3,
36121
+
3,
36122
+
3,
36123
+
3,
36124
+
3,
36125
+
3,
36126
+
3,
36127
+
3,
36128
+
2,
36129
+
2,
36130
+
2,
36131
+
2,
36132
+
2,
36133
+
2,
36134
+
-1,
36135
+
8,
36136
+
3,
36137
+
3,
36138
+
3,
36139
+
3,
36140
+
3,
36141
+
3,
36142
+
3,
36143
+
3,
36144
+
2,
36145
+
2,
36146
+
2,
36147
+
2,
36148
+
2,
36149
+
2,
36150
+
-1,
36151
+
8,
36152
+
3,
36153
+
3,
36154
+
3,
36155
+
3,
36156
+
3,
36157
+
3,
36158
+
3,
36159
+
3,
36160
+
2,
36161
+
2,
36162
+
2,
36163
+
2,
36164
+
2,
36165
+
2,
36166
+
-1,
36167
+
8,
36168
+
3,
36169
+
3,
36170
+
3,
36171
+
3,
36172
+
3,
36173
+
3,
36174
+
3,
36175
+
3,
36176
+
2,
36177
+
2,
36178
+
2,
36179
+
2,
36180
+
2,
36181
+
2,
36182
+
-1,
36183
+
8,
36184
+
3,
36185
+
3,
36186
+
3,
36187
+
3,
36188
+
3,
36189
+
3,
36190
+
3,
36191
+
3,
36192
+
2,
36193
+
2,
36194
+
2,
36195
+
2,
36196
+
2,
36197
+
2,
36198
+
-1,
36199
+
8,
36200
+
3,
36201
+
3,
36202
+
3,
36203
+
3,
36204
+
3,
36205
+
3,
36206
+
3,
36207
+
3,
36208
+
2,
36209
+
2,
36210
+
2,
36211
+
2,
36212
+
2,
36213
+
2,
36214
+
-1,
36215
+
8,
36216
+
3,
36217
+
3,
36218
+
3,
36219
+
3,
36220
+
3,
36221
+
3,
36222
+
3,
36223
+
3,
36224
+
2,
36225
+
2,
36226
+
2,
36227
+
2,
36228
+
2,
36229
+
2,
36230
+
-1,
36231
+
8,
36232
+
3,
36233
+
3,
36234
+
3,
36235
+
3,
36236
+
3,
36237
+
3,
36238
+
3,
36239
+
3,
36240
+
2,
36241
+
2,
36242
+
2,
36243
+
2,
36244
+
2,
36245
+
2,
36246
+
-1,
36247
+
8,
36248
+
3,
36249
+
3,
36250
+
3,
36251
+
3,
36252
+
3,
36253
+
3,
36254
+
3,
36255
+
3,
36256
+
2,
36257
+
2,
36258
+
2,
36259
+
2,
36260
+
2,
36261
+
2,
36262
+
-1,
36263
+
8,
36264
+
3,
36265
+
3,
36266
+
3,
36267
+
3,
36268
+
3,
36269
+
3,
36270
+
3,
36271
+
3,
36272
+
2,
36273
+
2,
36274
+
2,
36275
+
2,
36276
+
2,
36277
+
2,
36278
+
-1,
36279
+
8,
36280
+
3,
36281
+
3,
36282
+
3,
36283
+
3,
36284
+
3,
36285
+
3,
36286
+
3,
36287
+
3,
36288
+
2,
36289
+
2,
36290
+
2,
36291
+
2,
36292
+
2,
36293
+
2,
36294
+
-1,
36295
+
8,
36296
+
3,
36297
+
3,
36298
+
3,
36299
+
3,
36300
+
3,
36301
+
3,
36302
+
3,
36303
+
3,
36304
+
2,
36305
+
2,
36306
+
2,
36307
+
2,
36308
+
2,
36309
+
2,
36310
+
-1,
36311
+
8,
36312
+
3,
36313
+
3,
36314
+
3,
36315
+
3,
36316
+
3,
36317
+
3,
36318
+
3,
36319
+
3,
36320
+
2,
36321
+
2,
36322
+
2,
36323
+
2,
36324
+
2,
36325
+
2,
36326
+
-1,
36327
+
8,
36328
+
3,
36329
+
3,
36330
+
3,
36331
+
3,
36332
+
3,
36333
+
3,
36334
+
3,
36335
+
3,
36336
+
2,
36337
+
2,
36338
+
2,
36339
+
2,
36340
+
2,
36341
+
2,
36342
+
-1,
36343
+
8,
36360
36344
3,
36361
36345
3,
36362
36346
3,
···
36378
36362
static int
36379
36363
length_decoder (const unsigned char *insn)
36380
36364
{
36381
-
int op0 = insn[0] & 0xf;
36382
-
return length_table[op0];
36365
+
int l = insn[0];
36366
+
return length_table[l];
36383
36367
}
36384
36368
36385
36369
···
36390
36374
8 /* insn_size */, 0,
36391
36375
4, formats, format_decoder, length_decoder,
36392
36376
5, slots,
36393
-
387 /* num_fields */,
36394
-
445, operands,
36377
+
389 /* num_fields */,
36378
+
454, operands,
36395
36379
588, iclasses,
36396
36380
656, opcodes, 0,
36397
36381
8, regfiles,