+4 -1

MAINTAINERS

··· 249 249 F: target/i386/ 250 250 F: hw/i386/ 251 251 F: disas/i386.c 252 252 + T: git git://github.com/ehabkost/qemu.git x86-next 252 253 253 254 Xtensa 254 255 M: Max Filippov <jcmvbkbc@gmail.com> ··· 858 859 F: hw/core/machine.c 859 860 F: hw/core/null-machine.c 860 861 F: include/hw/boards.h 862 862 + T: git git://github.com/ehabkost/qemu.git machine-next 861 863 862 864 Xtensa Machines 863 865 --------------- ··· 1385 1387 S: Maintained 1386 1388 F: numa.c 1387 1389 F: include/sysemu/numa.h 1388 1388 - T: git git://github.com/ehabkost/qemu.git numa 1390 1390 + T: git git://github.com/ehabkost/qemu.git machine-next 1389 1391 1390 1392 Host Memory Backends 1391 1393 M: Eduardo Habkost <ehabkost@redhat.com> ··· 1393 1395 S: Maintained 1394 1396 F: backends/hostmem*.c 1395 1397 F: include/sysemu/hostmem.h 1398 1398 + T: git git://github.com/ehabkost/qemu.git machine-next 1396 1399 1397 1400 Cryptodev Backends 1398 1401 M: Gonglei <arei.gonglei@huawei.com>

+29

backends/hostmem-file.c

··· 32 32 HostMemoryBackend parent_obj; 33 33 34 34 bool share; 35 35 + bool discard_data; 35 36 char *mem_path; 36 37 }; 37 38 ··· 103 104 fb->share = value; 104 105 } 105 106 107 107 + static bool file_memory_backend_get_discard_data(Object *o, Error **errp) 108 108 + { 109 109 + return MEMORY_BACKEND_FILE(o)->discard_data; 110 110 + } 111 111 + 112 112 + static void file_memory_backend_set_discard_data(Object *o, bool value, 113 113 + Error **errp) 114 114 + { 115 115 + MEMORY_BACKEND_FILE(o)->discard_data = value; 116 116 + } 117 117 + 118 118 + static void file_backend_unparent(Object *obj) 119 119 + { 120 120 + HostMemoryBackend *backend = MEMORY_BACKEND(obj); 121 121 + HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(obj); 122 122 + 123 123 + if (host_memory_backend_mr_inited(backend) && fb->discard_data) { 124 124 + void *ptr = memory_region_get_ram_ptr(&backend->mr); 125 125 + uint64_t sz = memory_region_size(&backend->mr); 126 126 + 127 127 + qemu_madvise(ptr, sz, QEMU_MADV_REMOVE); 128 128 + } 129 129 + } 130 130 + 106 131 static void 107 132 file_backend_class_init(ObjectClass *oc, void *data) 108 133 { 109 134 HostMemoryBackendClass *bc = MEMORY_BACKEND_CLASS(oc); 110 135 111 136 bc->alloc = file_backend_memory_alloc; 137 137 + oc->unparent = file_backend_unparent; 112 138 113 139 object_class_property_add_bool(oc, "share", 114 140 file_memory_backend_get_share, file_memory_backend_set_share, 141 141 + &error_abort); 142 142 + object_class_property_add_bool(oc, "discard-data", 143 143 + file_memory_backend_get_discard_data, file_memory_backend_set_discard_data, 115 144 &error_abort); 116 145 object_class_property_add_str(oc, "mem-path", 117 146 get_mem_path, set_mem_path,

-4

bsd-user/main.c

··· 902 902 /* NOTE: we need to init the CPU at this stage to get 903 903 qemu_host_page_size */ 904 904 cpu = cpu_init(cpu_model); 905 905 - if (!cpu) { 906 906 - fprintf(stderr, "Unable to find CPU definition\n"); 907 907 - exit(1); 908 908 - } 909 905 env = cpu->env_ptr; 910 906 #if defined(TARGET_SPARC) || defined(TARGET_PPC) 911 907 cpu_reset(cpu);

-4

hw/alpha/dp264.c

··· 68 68 memset(cpus, 0, sizeof(cpus)); 69 69 for (i = 0; i < smp_cpus; ++i) { 70 70 cpus[i] = ALPHA_CPU(cpu_generic_init(TYPE_ALPHA_CPU, cpu_model)); 71 71 - if (!cpus[i]) { 72 72 - error_report("Unable to find CPU definition"); 73 73 - exit(1); 74 74 - } 75 71 } 76 72 77 73 cpus[0]->env.trap_arg0 = ram_size;

+5 -35

hw/arm/armv7m.c

··· 151 151 SysBusDevice *sbd; 152 152 Error *err = NULL; 153 153 int i; 154 154 - char **cpustr; 155 155 - ObjectClass *oc; 156 156 - const char *typename; 157 157 - CPUClass *cc; 158 154 159 155 if (!s->board_memory) { 160 156 error_setg(errp, "memory property was not set"); ··· 163 159 164 160 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 165 161 166 166 - cpustr = g_strsplit(s->cpu_model, ",", 2); 167 167 - 168 168 - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 169 169 - if (!oc) { 170 170 - error_setg(errp, "Unknown CPU model %s", cpustr[0]); 171 171 - g_strfreev(cpustr); 172 172 - return; 173 173 - } 174 174 - 175 175 - cc = CPU_CLASS(oc); 176 176 - typename = object_class_get_name(oc); 177 177 - cc->parse_features(typename, cpustr[1], &err); 178 178 - g_strfreev(cpustr); 179 179 - if (err) { 180 180 - error_propagate(errp, err); 181 181 - return; 182 182 - } 183 183 - 184 184 - s->cpu = ARM_CPU(object_new(typename)); 185 185 - if (!s->cpu) { 186 186 - error_setg(errp, "Unknown CPU model %s", s->cpu_model); 187 187 - return; 188 188 - } 162 162 + s->cpu = ARM_CPU(object_new(s->cpu_type)); 189 163 190 164 object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", 191 165 &error_abort); ··· 241 215 } 242 216 243 217 static Property armv7m_properties[] = { 244 244 - DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model), 218 218 + DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type), 245 219 DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION, 246 220 MemoryRegion *), 247 221 DEFINE_PROP_END_OF_LIST(), ··· 275 249 Returns the ARMv7M device. */ 276 250 277 251 DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, 278 278 - const char *kernel_filename, const char *cpu_model) 252 252 + const char *kernel_filename, const char *cpu_type) 279 253 { 280 254 DeviceState *armv7m; 281 255 282 282 - if (cpu_model == NULL) { 283 283 - cpu_model = "cortex-m3"; 284 284 - } 285 285 - 286 256 armv7m = qdev_create(NULL, TYPE_ARMV7M); 287 257 qdev_prop_set_uint32(armv7m, "num-irq", num_irq); 288 288 - qdev_prop_set_string(armv7m, "cpu-model", cpu_model); 258 258 + qdev_prop_set_string(armv7m, "cpu-type", cpu_type); 289 259 object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()), 290 260 "memory", &error_abort); 291 291 - /* This will exit with an error if the user passed us a bad cpu_model */ 261 261 + /* This will exit with an error if the user passed us a bad cpu_type */ 292 262 qdev_init_nofail(armv7m); 293 263 294 264 armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);

+5 -8

hw/arm/aspeed_soc.c

··· 54 54 static const AspeedSoCInfo aspeed_socs[] = { 55 55 { 56 56 .name = "ast2400-a0", 57 57 - .cpu_model = "arm926", 57 57 + .cpu_type = ARM_CPU_TYPE_NAME("arm926"), 58 58 .silicon_rev = AST2400_A0_SILICON_REV, 59 59 .sdram_base = AST2400_SDRAM_BASE, 60 60 .sram_size = 0x8000, ··· 65 65 .wdts_num = 2, 66 66 }, { 67 67 .name = "ast2400-a1", 68 68 - .cpu_model = "arm926", 68 68 + .cpu_type = ARM_CPU_TYPE_NAME("arm926"), 69 69 .silicon_rev = AST2400_A1_SILICON_REV, 70 70 .sdram_base = AST2400_SDRAM_BASE, 71 71 .sram_size = 0x8000, ··· 76 76 .wdts_num = 2, 77 77 }, { 78 78 .name = "ast2400", 79 79 - .cpu_model = "arm926", 79 79 + .cpu_type = ARM_CPU_TYPE_NAME("arm926"), 80 80 .silicon_rev = AST2400_A0_SILICON_REV, 81 81 .sdram_base = AST2400_SDRAM_BASE, 82 82 .sram_size = 0x8000, ··· 87 87 .wdts_num = 2, 88 88 }, { 89 89 .name = "ast2500-a1", 90 90 - .cpu_model = "arm1176", 90 90 + .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), 91 91 .silicon_rev = AST2500_A1_SILICON_REV, 92 92 .sdram_base = AST2500_SDRAM_BASE, 93 93 .sram_size = 0x9000, ··· 128 128 { 129 129 AspeedSoCState *s = ASPEED_SOC(obj); 130 130 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 131 131 - char *cpu_typename; 132 131 int i; 133 132 134 134 - cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model); 135 135 - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename); 133 133 + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type); 136 134 object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); 137 137 - g_free(cpu_typename); 138 135 139 136 object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); 140 137 object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);

+3 -7

hw/arm/collie.c

··· 18 18 #include "hw/block/flash.h" 19 19 #include "sysemu/block-backend.h" 20 20 #include "exec/address-spaces.h" 21 21 - #include "qom/cpu.h" 21 21 + #include "cpu.h" 22 22 23 23 static struct arm_boot_info collie_binfo = { 24 24 .loader_start = SA_SDCS0, ··· 27 27 28 28 static void collie_init(MachineState *machine) 29 29 { 30 30 - const char *cpu_model = machine->cpu_model; 31 30 const char *kernel_filename = machine->kernel_filename; 32 31 const char *kernel_cmdline = machine->kernel_cmdline; 33 32 const char *initrd_filename = machine->initrd_filename; ··· 35 34 DriveInfo *dinfo; 36 35 MemoryRegion *sysmem = get_system_memory(); 37 36 38 38 - if (!cpu_model) { 39 39 - cpu_model = "sa1110"; 40 40 - } 41 41 - 42 42 - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model); 37 37 + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type); 43 38 44 39 dinfo = drive_get(IF_PFLASH, 0, 0); 45 40 pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000, ··· 65 60 mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)"; 66 61 mc->init = collie_init; 67 62 mc->ignore_memory_transaction_failures = true; 63 63 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110"); 68 64 } 69 65 70 66 DEFINE_MACHINE("collie", collie_machine_init)

+1 -5

hw/arm/exynos4210.c

··· 169 169 Exynos4210State *s = g_new(Exynos4210State, 1); 170 170 qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; 171 171 SysBusDevice *busdev; 172 172 - ObjectClass *cpu_oc; 173 172 DeviceState *dev; 174 173 int i, n; 175 174 176 176 - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); 177 177 - assert(cpu_oc); 178 178 - 179 175 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 180 180 - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 176 176 + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); 181 177 182 178 /* By default A9 CPUs have EL3 enabled. This board does not currently 183 179 * support EL3 so the CPU EL3 property is disabled before realization.

+3 -2

hw/arm/gumstix.c

··· 44 44 #include "sysemu/block-backend.h" 45 45 #include "exec/address-spaces.h" 46 46 #include "sysemu/qtest.h" 47 47 + #include "cpu.h" 47 48 48 49 static const int sector_len = 128 * 1024; 49 50 ··· 86 87 87 88 static void verdex_init(MachineState *machine) 88 89 { 89 89 - const char *cpu_model = machine->cpu_model; 90 90 PXA2xxState *cpu; 91 91 DriveInfo *dinfo; 92 92 int be; ··· 95 95 uint32_t verdex_rom = 0x02000000; 96 96 uint32_t verdex_ram = 0x10000000; 97 97 98 98 - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: "pxa270-c0"); 98 98 + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type); 99 99 100 100 dinfo = drive_get(IF_PFLASH, 0, 0); 101 101 if (!dinfo && !qtest_enabled()) { ··· 144 144 mc->desc = "Gumstix Verdex (PXA270)"; 145 145 mc->init = verdex_init; 146 146 mc->ignore_memory_transaction_failures = true; 147 147 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); 147 148 } 148 149 149 150 static const TypeInfo verdex_type = {

+5 -5

hw/arm/highbank.c

··· 222 222 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 223 223 { 224 224 ram_addr_t ram_size = machine->ram_size; 225 225 - const char *cpu_model = machine->cpu_model; 226 225 const char *kernel_filename = machine->kernel_filename; 227 226 const char *kernel_cmdline = machine->kernel_cmdline; 228 227 const char *initrd_filename = machine->initrd_filename; ··· 239 238 240 239 switch (machine_id) { 241 240 case CALXEDA_HIGHBANK: 242 242 - cpu_model = "cortex-a9"; 241 241 + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 243 242 break; 244 243 case CALXEDA_MIDWAY: 245 245 - cpu_model = "cortex-a15"; 244 244 + machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 246 245 break; 246 246 + default: 247 247 + assert(0); 247 248 } 248 249 249 250 for (n = 0; n < smp_cpus; n++) { 250 250 - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 251 251 Object *cpuobj; 252 252 ARMCPU *cpu; 253 253 254 254 - cpuobj = object_new(object_class_get_name(oc)); 254 254 + cpuobj = object_new(machine->cpu_type); 255 255 cpu = ARM_CPU(cpuobj); 256 256 257 257 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,

+2 -28

hw/arm/integratorcp.c

··· 572 572 static void integratorcp_init(MachineState *machine) 573 573 { 574 574 ram_addr_t ram_size = machine->ram_size; 575 575 - const char *cpu_model = machine->cpu_model; 576 575 const char *kernel_filename = machine->kernel_filename; 577 576 const char *kernel_cmdline = machine->kernel_cmdline; 578 577 const char *initrd_filename = machine->initrd_filename; 579 579 - char **cpustr; 580 580 - ObjectClass *cpu_oc; 581 581 - CPUClass *cc; 582 578 Object *cpuobj; 583 579 ARMCPU *cpu; 584 584 - const char *typename; 585 580 MemoryRegion *address_space_mem = get_system_memory(); 586 581 MemoryRegion *ram = g_new(MemoryRegion, 1); 587 582 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 588 583 qemu_irq pic[32]; 589 584 DeviceState *dev, *sic, *icp; 590 585 int i; 591 591 - Error *err = NULL; 592 586 593 593 - if (!cpu_model) { 594 594 - cpu_model = "arm926"; 595 595 - } 596 596 - 597 597 - cpustr = g_strsplit(cpu_model, ",", 2); 598 598 - 599 599 - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 600 600 - if (!cpu_oc) { 601 601 - fprintf(stderr, "Unable to find CPU definition\n"); 602 602 - exit(1); 603 603 - } 604 604 - typename = object_class_get_name(cpu_oc); 605 605 - 606 606 - cc = CPU_CLASS(cpu_oc); 607 607 - cc->parse_features(typename, cpustr[1], &err); 608 608 - g_strfreev(cpustr); 609 609 - if (err) { 610 610 - error_report_err(err); 611 611 - exit(1); 612 612 - } 613 613 - 614 614 - cpuobj = object_new(typename); 587 587 + cpuobj = object_new(machine->cpu_type); 615 588 616 589 /* By default ARM1176 CPUs have EL3 enabled. This board does not 617 590 * currently support EL3 so the CPU EL3 property is disabled before ··· 682 655 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 683 656 mc->init = integratorcp_init; 684 657 mc->ignore_memory_transaction_failures = true; 658 658 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 685 659 } 686 660 687 661 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)

+4 -5

hw/arm/mainstone.c

··· 24 24 #include "hw/sysbus.h" 25 25 #include "exec/address-spaces.h" 26 26 #include "sysemu/qtest.h" 27 27 + #include "cpu.h" 27 28 28 29 /* Device addresses */ 29 30 #define MST_FPGA_PHYS 0x08000000 ··· 121 122 int i; 122 123 int be; 123 124 MemoryRegion *rom = g_new(MemoryRegion, 1); 124 124 - const char *cpu_model = machine->cpu_model; 125 125 - 126 126 - if (!cpu_model) 127 127 - cpu_model = "pxa270-c5"; 128 125 129 126 /* Setup CPU & memory */ 130 130 - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model); 127 127 + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, 128 128 + machine->cpu_type); 131 129 memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM, 132 130 &error_fatal); 133 131 memory_region_set_readonly(rom, true); ··· 197 195 mc->desc = "Mainstone II (PXA27x)"; 198 196 mc->init = mainstone_init; 199 197 mc->ignore_memory_transaction_failures = true; 198 198 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); 200 199 } 201 200 202 201 DEFINE_MACHINE("mainstone", mainstone2_machine_init)

+7 -10

hw/arm/mps2.c

··· 46 46 typedef struct { 47 47 MachineClass parent; 48 48 MPS2FPGAType fpga_type; 49 49 - const char *cpu_model; 50 49 uint32_t scc_id; 51 50 } MPS2MachineClass; 52 51 ··· 107 106 MPS2MachineState *mms = MPS2_MACHINE(machine); 108 107 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); 109 108 MemoryRegion *system_memory = get_system_memory(); 109 109 + MachineClass *mc = MACHINE_GET_CLASS(machine); 110 110 DeviceState *armv7m, *sccdev; 111 111 112 112 - if (!machine->cpu_model) { 113 113 - machine->cpu_model = mmc->cpu_model; 114 114 - } 115 115 - 116 116 - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) { 117 117 - error_report("This board can only be used with CPU %s", mmc->cpu_model); 112 112 + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 113 113 + error_report("This board can only be used with CPU %s", 114 114 + mc->default_cpu_type); 118 115 exit(1); 119 116 } 120 117 ··· 188 185 default: 189 186 g_assert_not_reached(); 190 187 } 191 191 - qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model); 188 188 + qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); 192 189 object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), 193 190 "memory", &error_abort); 194 191 object_property_set_bool(OBJECT(&mms->armv7m), true, "realized", ··· 339 336 340 337 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; 341 338 mmc->fpga_type = FPGA_AN385; 342 342 - mmc->cpu_model = "cortex-m3"; 339 339 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 343 340 mmc->scc_id = 0x41040000 | (385 << 4); 344 341 } 345 342 ··· 350 347 351 348 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; 352 349 mmc->fpga_type = FPGA_AN511; 353 353 - mmc->cpu_model = "cortex-m3"; 350 350 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 354 351 mmc->scc_id = 0x4104000 | (511 << 4); 355 352 } 356 353

+2 -9

hw/arm/musicpal.c

··· 1570 1570 1571 1571 static void musicpal_init(MachineState *machine) 1572 1572 { 1573 1573 - const char *cpu_model = machine->cpu_model; 1574 1573 const char *kernel_filename = machine->kernel_filename; 1575 1574 const char *kernel_cmdline = machine->kernel_cmdline; 1576 1575 const char *initrd_filename = machine->initrd_filename; ··· 1590 1589 MemoryRegion *ram = g_new(MemoryRegion, 1); 1591 1590 MemoryRegion *sram = g_new(MemoryRegion, 1); 1592 1591 1593 1593 - if (!cpu_model) { 1594 1594 - cpu_model = "arm926"; 1595 1595 - } 1596 1596 - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); 1597 1597 - if (!cpu) { 1598 1598 - fprintf(stderr, "Unable to find CPU definition\n"); 1599 1599 - exit(1); 1600 1600 - } 1592 1592 + cpu = ARM_CPU(cpu_create(machine->cpu_type)); 1601 1593 1602 1594 /* For now we use a fixed - the original - RAM size */ 1603 1595 memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", ··· 1719 1711 mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; 1720 1712 mc->init = musicpal_init; 1721 1713 mc->ignore_memory_transaction_failures = true; 1714 1714 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 1722 1715 } 1723 1716 1724 1717 DEFINE_MACHINE("musicpal", musicpal_machine_init)

+1 -1

hw/arm/netduino2.c

··· 34 34 DeviceState *dev; 35 35 36 36 dev = qdev_create(NULL, TYPE_STM32F205_SOC); 37 37 - qdev_prop_set_string(dev, "cpu-model", "cortex-m3"); 37 37 + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); 38 38 object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); 39 39 40 40 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

+3 -1

hw/arm/nseries.c

··· 1310 1310 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); 1311 1311 int sdram_size = binfo->ram_size; 1312 1312 1313 1313 - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model); 1313 1313 + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type); 1314 1314 1315 1315 /* Setup peripherals 1316 1316 * ··· 1426 1426 mc->init = n800_init; 1427 1427 mc->default_boot_order = ""; 1428 1428 mc->ignore_memory_transaction_failures = true; 1429 1429 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1429 1430 } 1430 1431 1431 1432 static const TypeInfo n800_type = { ··· 1442 1443 mc->init = n810_init; 1443 1444 mc->default_boot_order = ""; 1444 1445 mc->ignore_memory_transaction_failures = true; 1446 1446 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1445 1447 } 1446 1448 1447 1449 static const TypeInfo n810_type = {

+2 -9

hw/arm/omap1.c

··· 3850 3850 3851 3851 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, 3852 3852 unsigned long sdram_size, 3853 3853 - const char *core) 3853 3853 + const char *cpu_type) 3854 3854 { 3855 3855 int i; 3856 3856 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); ··· 3858 3858 DriveInfo *dinfo; 3859 3859 SysBusDevice *busdev; 3860 3860 3861 3861 - if (!core) 3862 3862 - core = "ti925t"; 3863 3863 - 3864 3861 /* Core */ 3865 3862 s->mpu_model = omap310; 3866 3866 - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core)); 3867 3867 - if (s->cpu == NULL) { 3868 3868 - fprintf(stderr, "Unable to find CPU definition\n"); 3869 3869 - exit(1); 3870 3870 - } 3863 3863 + s->cpu = ARM_CPU(cpu_create(cpu_type)); 3871 3864 s->sdram_size = sdram_size; 3872 3865 s->sram_size = OMAP15XX_SRAM_SIZE; 3873 3866

+2 -6

hw/arm/omap2.c

··· 2250 2250 2251 2251 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, 2252 2252 unsigned long sdram_size, 2253 2253 - const char *core) 2253 2253 + const char *cpu_type) 2254 2254 { 2255 2255 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); 2256 2256 qemu_irq dma_irqs[4]; ··· 2261 2261 2262 2262 /* Core */ 2263 2263 s->mpu_model = omap2420; 2264 2264 - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: "arm1136-r2")); 2265 2265 - if (s->cpu == NULL) { 2266 2266 - fprintf(stderr, "Unable to find CPU definition\n"); 2267 2267 - exit(1); 2268 2268 - } 2264 2264 + s->cpu = ARM_CPU(cpu_create(cpu_type)); 2269 2265 s->sdram_size = sdram_size; 2270 2266 s->sram_size = OMAP242X_SRAM_SIZE; 2271 2267

+4 -1

hw/arm/omap_sx1.c

··· 36 36 #include "sysemu/block-backend.h" 37 37 #include "sysemu/qtest.h" 38 38 #include "exec/address-spaces.h" 39 39 + #include "cpu.h" 39 40 40 41 /*****************************************************************************/ 41 42 /* Siemens SX1 Cellphone V1 */ ··· 120 121 } 121 122 122 123 mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, 123 123 - machine->cpu_model); 124 124 + machine->cpu_type); 124 125 125 126 /* External Flash (EMIFS) */ 126 127 memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size, ··· 224 225 mc->desc = "Siemens SX1 (OMAP310) V2"; 225 226 mc->init = sx1_init_v2; 226 227 mc->ignore_memory_transaction_failures = true; 228 228 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 227 229 } 228 230 229 231 static const TypeInfo sx1_machine_v2_type = { ··· 239 241 mc->desc = "Siemens SX1 (OMAP310) V1"; 240 242 mc->init = sx1_init_v1; 241 243 mc->ignore_memory_transaction_failures = true; 244 244 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 242 245 } 243 246 244 247 static const TypeInfo sx1_machine_v1_type = {

+3 -2

hw/arm/palm.c

··· 29 29 #include "hw/devices.h" 30 30 #include "hw/loader.h" 31 31 #include "exec/address-spaces.h" 32 32 + #include "cpu.h" 32 33 33 34 static uint32_t static_readb(void *opaque, hwaddr offset) 34 35 { ··· 195 196 196 197 static void palmte_init(MachineState *machine) 197 198 { 198 198 - const char *cpu_model = machine->cpu_model; 199 199 const char *kernel_filename = machine->kernel_filename; 200 200 const char *kernel_cmdline = machine->kernel_cmdline; 201 201 const char *initrd_filename = machine->initrd_filename; ··· 211 211 MemoryRegion *flash = g_new(MemoryRegion, 1); 212 212 MemoryRegion *cs = g_new(MemoryRegion, 4); 213 213 214 214 - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model); 214 214 + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type); 215 215 216 216 /* External Flash (EMIFS) */ 217 217 memory_region_init_ram(flash, NULL, "palmte.flash", flash_size, ··· 275 275 mc->desc = "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; 276 276 mc->init = palmte_init; 277 277 mc->ignore_memory_transaction_failures = true; 278 278 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 278 279 } 279 280 280 281 DEFINE_MACHINE("cheetah", palmte_machine_init)

+4 -14

hw/arm/pxa2xx.c

··· 2052 2052 2053 2053 /* Initialise a PXA270 integrated chip (ARM based core). */ 2054 2054 PXA2xxState *pxa270_init(MemoryRegion *address_space, 2055 2055 - unsigned int sdram_size, const char *revision) 2055 2055 + unsigned int sdram_size, const char *cpu_type) 2056 2056 { 2057 2057 PXA2xxState *s; 2058 2058 int i; 2059 2059 DriveInfo *dinfo; 2060 2060 s = g_new0(PXA2xxState, 1); 2061 2061 2062 2062 - if (revision && strncmp(revision, "pxa27", 5)) { 2062 2062 + if (strncmp(cpu_type, "pxa27", 5)) { 2063 2063 fprintf(stderr, "Machine requires a PXA27x processor.\n"); 2064 2064 exit(1); 2065 2065 } 2066 2066 - if (!revision) 2067 2067 - revision = "pxa270"; 2068 2066 2069 2069 - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision)); 2070 2070 - if (s->cpu == NULL) { 2071 2071 - fprintf(stderr, "Unable to find CPU definition\n"); 2072 2072 - exit(1); 2073 2073 - } 2067 2067 + s->cpu = ARM_CPU(cpu_create(cpu_type)); 2074 2068 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2075 2069 2076 2070 /* SDRAM & Internal Memory Storage */ ··· 2196 2190 2197 2191 s = g_new0(PXA2xxState, 1); 2198 2192 2199 2199 - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, "pxa255")); 2200 2200 - if (s->cpu == NULL) { 2201 2201 - fprintf(stderr, "Unable to find CPU definition\n"); 2202 2202 - exit(1); 2203 2203 - } 2193 2193 + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); 2204 2194 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); 2205 2195 2206 2196 /* SDRAM & Internal Memory Storage */

+5 -20

hw/arm/realview.c

··· 57 57 { 58 58 ARMCPU *cpu = NULL; 59 59 CPUARMState *env; 60 60 - ObjectClass *cpu_oc; 61 60 MemoryRegion *sysmem = get_system_memory(); 62 61 MemoryRegion *ram_lo; 63 62 MemoryRegion *ram_hi = g_new(MemoryRegion, 1); ··· 98 97 break; 99 98 } 100 99 101 101 - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 102 102 - if (!cpu_oc) { 103 103 - fprintf(stderr, "Unable to find CPU definition\n"); 104 104 - exit(1); 105 105 - } 106 106 - 107 100 for (n = 0; n < smp_cpus; n++) { 108 108 - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 101 101 + Object *cpuobj = object_new(machine->cpu_type); 109 102 110 103 /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board 111 104 * does not currently support EL3 so the CPU EL3 property is disabled ··· 361 354 362 355 static void realview_eb_init(MachineState *machine) 363 356 { 364 364 - if (!machine->cpu_model) { 365 365 - machine->cpu_model = "arm926"; 366 366 - } 367 357 realview_init(machine, BOARD_EB); 368 358 } 369 359 370 360 static void realview_eb_mpcore_init(MachineState *machine) 371 361 { 372 372 - if (!machine->cpu_model) { 373 373 - machine->cpu_model = "arm11mpcore"; 374 374 - } 375 362 realview_init(machine, BOARD_EB_MPCORE); 376 363 } 377 364 378 365 static void realview_pb_a8_init(MachineState *machine) 379 366 { 380 380 - if (!machine->cpu_model) { 381 381 - machine->cpu_model = "cortex-a8"; 382 382 - } 383 367 realview_init(machine, BOARD_PB_A8); 384 368 } 385 369 386 370 static void realview_pbx_a9_init(MachineState *machine) 387 371 { 388 388 - if (!machine->cpu_model) { 389 389 - machine->cpu_model = "cortex-a9"; 390 390 - } 391 372 realview_init(machine, BOARD_PBX_A9); 392 373 } 393 374 ··· 399 380 mc->init = realview_eb_init; 400 381 mc->block_default_type = IF_SCSI; 401 382 mc->ignore_memory_transaction_failures = true; 383 383 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 402 384 } 403 385 404 386 static const TypeInfo realview_eb_type = { ··· 416 398 mc->block_default_type = IF_SCSI; 417 399 mc->max_cpus = 4; 418 400 mc->ignore_memory_transaction_failures = true; 401 401 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); 419 402 } 420 403 421 404 static const TypeInfo realview_eb_mpcore_type = { ··· 431 414 mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; 432 415 mc->init = realview_pb_a8_init; 433 416 mc->ignore_memory_transaction_failures = true; 417 417 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); 434 418 } 435 419 436 420 static const TypeInfo realview_pb_a8_type = { ··· 447 431 mc->init = realview_pbx_a9_init; 448 432 mc->max_cpus = 4; 449 433 mc->ignore_memory_transaction_failures = true; 434 434 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 450 435 } 451 436 452 437 static const TypeInfo realview_pbx_a9_type = {

+7 -5

hw/arm/spitz.c

··· 30 30 #include "hw/sysbus.h" 31 31 #include "exec/address-spaces.h" 32 32 #include "sysemu/sysemu.h" 33 33 + #include "cpu.h" 33 34 34 35 #undef REG_FMT 35 36 #define REG_FMT "0x%02lx" ··· 909 910 DeviceState *scp0, *scp1 = NULL; 910 911 MemoryRegion *address_space_mem = get_system_memory(); 911 912 MemoryRegion *rom = g_new(MemoryRegion, 1); 912 912 - const char *cpu_model = machine->cpu_model; 913 913 - 914 914 - if (!cpu_model) 915 915 - cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; 916 913 917 914 /* Setup CPU & memory */ 918 918 - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model); 915 915 + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, 916 916 + machine->cpu_type); 919 917 920 918 sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); 921 919 ··· 984 982 mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; 985 983 mc->init = akita_init; 986 984 mc->ignore_memory_transaction_failures = true; 985 985 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); 987 986 } 988 987 989 988 static const TypeInfo akitapda_type = { ··· 1000 999 mc->init = spitz_init; 1001 1000 mc->block_default_type = IF_IDE; 1002 1001 mc->ignore_memory_transaction_failures = true; 1002 1002 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); 1003 1003 } 1004 1004 1005 1005 static const TypeInfo spitzpda_type = { ··· 1016 1016 mc->init = borzoi_init; 1017 1017 mc->block_default_type = IF_IDE; 1018 1018 mc->ignore_memory_transaction_failures = true; 1019 1019 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); 1019 1020 } 1020 1021 1021 1022 static const TypeInfo borzoipda_type = { ··· 1032 1033 mc->init = terrier_init; 1033 1034 mc->block_default_type = IF_IDE; 1034 1035 mc->ignore_memory_transaction_failures = true; 1036 1036 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); 1035 1037 } 1036 1038 1037 1039 static const TypeInfo terrierpda_type = {

+7 -9

hw/arm/stellaris.c

··· 22 22 #include "sysemu/sysemu.h" 23 23 #include "hw/char/pl011.h" 24 24 #include "hw/misc/unimp.h" 25 25 + #include "cpu.h" 25 26 26 27 #define GPIO_A 0 27 28 #define GPIO_B 1 ··· 1225 1226 } 1226 1227 }; 1227 1228 1228 1228 - static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1229 1229 - stellaris_board_info *board) 1229 1229 + static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1230 1230 { 1231 1231 static const int uart_irq[] = {5, 6, 33, 34}; 1232 1232 static const int timer_irq[] = {19, 21, 23, 35}; ··· 1298 1298 memory_region_add_subregion(system_memory, 0x20000000, sram); 1299 1299 1300 1300 nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 1301 1301 - kernel_filename, cpu_model); 1301 1301 + ms->kernel_filename, ms->cpu_type); 1302 1302 1303 1303 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1304 1304 qemu_allocate_irq(&do_sys_reset, NULL, 0)); ··· 1435 1435 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1436 1436 static void lm3s811evb_init(MachineState *machine) 1437 1437 { 1438 1438 - const char *cpu_model = machine->cpu_model; 1439 1439 - const char *kernel_filename = machine->kernel_filename; 1440 1440 - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1438 1438 + stellaris_init(machine, &stellaris_boards[0]); 1441 1439 } 1442 1440 1443 1441 static void lm3s6965evb_init(MachineState *machine) 1444 1442 { 1445 1445 - const char *cpu_model = machine->cpu_model; 1446 1446 - const char *kernel_filename = machine->kernel_filename; 1447 1447 - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1443 1443 + stellaris_init(machine, &stellaris_boards[1]); 1448 1444 } 1449 1445 1450 1446 static void lm3s811evb_class_init(ObjectClass *oc, void *data) ··· 1454 1450 mc->desc = "Stellaris LM3S811EVB"; 1455 1451 mc->init = lm3s811evb_init; 1456 1452 mc->ignore_memory_transaction_failures = true; 1453 1453 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1457 1454 } 1458 1455 1459 1456 static const TypeInfo lm3s811evb_type = { ··· 1469 1466 mc->desc = "Stellaris LM3S6965EVB"; 1470 1467 mc->init = lm3s6965evb_init; 1471 1468 mc->ignore_memory_transaction_failures = true; 1469 1469 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1472 1470 } 1473 1471 1474 1472 static const TypeInfo lm3s6965evb_type = {

+2 -2

hw/arm/stm32f205_soc.c

··· 112 112 113 113 armv7m = DEVICE(&s->armv7m); 114 114 qdev_prop_set_uint32(armv7m, "num-irq", 96); 115 115 - qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model); 115 115 + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 116 116 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 117 117 "memory", &error_abort); 118 118 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); ··· 200 200 } 201 201 202 202 static Property stm32f205_soc_properties[] = { 203 203 - DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model), 203 203 + DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), 204 204 DEFINE_PROP_END_OF_LIST(), 205 205 }; 206 206

+3 -12

hw/arm/strongarm.c

··· 1581 1581 1582 1582 /* Main CPU functions */ 1583 1583 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1584 1584 - unsigned int sdram_size, const char *rev) 1584 1584 + unsigned int sdram_size, const char *cpu_type) 1585 1585 { 1586 1586 StrongARMState *s; 1587 1587 int i; 1588 1588 1589 1589 s = g_new0(StrongARMState, 1); 1590 1590 1591 1591 - if (!rev) { 1592 1592 - rev = "sa1110-b5"; 1593 1593 - } 1594 1594 - 1595 1595 - if (strncmp(rev, "sa1110", 6)) { 1591 1591 + if (strncmp(cpu_type, "sa1110", 6)) { 1596 1592 error_report("Machine requires a SA1110 processor."); 1597 1593 exit(1); 1598 1594 } 1599 1595 1600 1600 - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev)); 1601 1601 - 1602 1602 - if (!s->cpu) { 1603 1603 - error_report("Unable to find CPU definition"); 1604 1604 - exit(1); 1605 1605 - } 1596 1596 + s->cpu = ARM_CPU(cpu_create(cpu_type)); 1606 1597 1607 1598 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram", 1608 1599 sdram_size);

-4

hw/arm/tosa.c

··· 219 219 220 220 static void tosa_init(MachineState *machine) 221 221 { 222 222 - const char *cpu_model = machine->cpu_model; 223 222 const char *kernel_filename = machine->kernel_filename; 224 223 const char *kernel_cmdline = machine->kernel_cmdline; 225 224 const char *initrd_filename = machine->initrd_filename; ··· 228 227 PXA2xxState *mpu; 229 228 TC6393xbState *tmio; 230 229 DeviceState *scp0, *scp1; 231 231 - 232 232 - if (!cpu_model) 233 233 - cpu_model = "pxa255"; 234 230 235 231 mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size); 236 232

+3 -12

hw/arm/versatilepb.c

··· 181 181 182 182 static void versatile_init(MachineState *machine, int board_id) 183 183 { 184 184 - ObjectClass *cpu_oc; 185 184 Object *cpuobj; 186 185 ARMCPU *cpu; 187 186 MemoryRegion *sysmem = get_system_memory(); ··· 207 206 exit(1); 208 207 } 209 208 210 210 - if (!machine->cpu_model) { 211 211 - machine->cpu_model = "arm926"; 212 212 - } 213 213 - 214 214 - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 215 215 - if (!cpu_oc) { 216 216 - fprintf(stderr, "Unable to find CPU definition\n"); 217 217 - exit(1); 218 218 - } 219 219 - 220 220 - cpuobj = object_new(object_class_get_name(cpu_oc)); 209 209 + cpuobj = object_new(machine->cpu_type); 221 210 222 211 /* By default ARM1176 CPUs have EL3 enabled. This board does not 223 212 * currently support EL3 so the CPU EL3 property is disabled before ··· 404 393 mc->init = vpb_init; 405 394 mc->block_default_type = IF_SCSI; 406 395 mc->ignore_memory_transaction_failures = true; 396 396 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 407 397 } 408 398 409 399 static const TypeInfo versatilepb_type = { ··· 420 410 mc->init = vab_init; 421 411 mc->block_default_type = IF_SCSI; 422 412 mc->ignore_memory_transaction_failures = true; 413 413 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 423 414 } 424 415 425 416 static const TypeInfo versatileab_type = {

+10 -22

hw/arm/vexpress.c

··· 186 186 187 187 typedef void DBoardInitFn(const VexpressMachineState *machine, 188 188 ram_addr_t ram_size, 189 189 - const char *cpu_model, 189 189 + const char *cpu_type, 190 190 qemu_irq *pic); 191 191 192 192 struct VEDBoardInfo { ··· 202 202 DBoardInitFn *init; 203 203 }; 204 204 205 205 - static void init_cpus(const char *cpu_model, const char *privdev, 205 205 + static void init_cpus(const char *cpu_type, const char *privdev, 206 206 hwaddr periphbase, qemu_irq *pic, bool secure) 207 207 { 208 208 - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 209 208 DeviceState *dev; 210 209 SysBusDevice *busdev; 211 210 int n; 212 211 213 213 - if (!cpu_oc) { 214 214 - fprintf(stderr, "Unable to find CPU definition\n"); 215 215 - exit(1); 216 216 - } 217 217 - 218 212 /* Create the actual CPUs */ 219 213 for (n = 0; n < smp_cpus; n++) { 220 220 - Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 214 214 + Object *cpuobj = object_new(cpu_type); 221 215 222 216 if (!secure) { 223 217 object_property_set_bool(cpuobj, false, "has_el3", NULL); ··· 262 256 263 257 static void a9_daughterboard_init(const VexpressMachineState *vms, 264 258 ram_addr_t ram_size, 265 265 - const char *cpu_model, 259 259 + const char *cpu_type, 266 260 qemu_irq *pic) 267 261 { 268 262 MemoryRegion *sysmem = get_system_memory(); ··· 270 264 MemoryRegion *lowram = g_new(MemoryRegion, 1); 271 265 ram_addr_t low_ram_size; 272 266 273 273 - if (!cpu_model) { 274 274 - cpu_model = "cortex-a9"; 275 275 - } 276 276 - 277 267 if (ram_size > 0x40000000) { 278 268 /* 1GB is the maximum the address space permits */ 279 269 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); ··· 295 285 memory_region_add_subregion(sysmem, 0x60000000, ram); 296 286 297 287 /* 0x1e000000 A9MPCore (SCU) private memory region */ 298 298 - init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); 288 288 + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); 299 289 300 290 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 301 291 ··· 351 341 352 342 static void a15_daughterboard_init(const VexpressMachineState *vms, 353 343 ram_addr_t ram_size, 354 354 - const char *cpu_model, 344 344 + const char *cpu_type, 355 345 qemu_irq *pic) 356 346 { 357 347 MemoryRegion *sysmem = get_system_memory(); 358 348 MemoryRegion *ram = g_new(MemoryRegion, 1); 359 349 MemoryRegion *sram = g_new(MemoryRegion, 1); 360 350 361 361 - if (!cpu_model) { 362 362 - cpu_model = "cortex-a15"; 363 363 - } 364 364 - 365 351 { 366 352 /* We have to use a separate 64 bit variable here to avoid the gcc 367 353 * "comparison is always false due to limited range of data type" ··· 380 366 memory_region_add_subregion(sysmem, 0x80000000, ram); 381 367 382 368 /* 0x2c000000 A15MPCore private memory region (GIC) */ 383 383 - init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); 369 369 + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); 384 370 385 371 /* A15 daughterboard peripherals: */ 386 372 ··· 560 546 const hwaddr *map = daughterboard->motherboard_map; 561 547 int i; 562 548 563 563 - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic); 549 549 + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 564 550 565 551 /* 566 552 * If a bios file was provided, attempt to map it into memory ··· 761 747 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 762 748 763 749 mc->desc = "ARM Versatile Express for Cortex-A9"; 750 750 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 764 751 765 752 vmc->daughterboard = &a9_daughterboard; 766 753 } ··· 771 758 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 772 759 773 760 mc->desc = "ARM Versatile Express for Cortex-A15"; 761 761 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 774 762 775 763 vmc->daughterboard = &a15_daughterboard; 776 764 }

+15 -45

hw/arm/virt.c

··· 163 163 }; 164 164 165 165 static const char *valid_cpus[] = { 166 166 - "cortex-a15", 167 167 - "cortex-a53", 168 168 - "cortex-a57", 169 169 - "host", 166 166 + ARM_CPU_TYPE_NAME("cortex-a15"), 167 167 + ARM_CPU_TYPE_NAME("cortex-a53"), 168 168 + ARM_CPU_TYPE_NAME("cortex-a57"), 169 169 + ARM_CPU_TYPE_NAME("host"), 170 170 }; 171 171 172 172 - static bool cpuname_valid(const char *cpu) 172 172 + static bool cpu_type_valid(const char *cpu) 173 173 { 174 174 int i; 175 175 ··· 1259 1259 MemoryRegion *secure_sysmem = NULL; 1260 1260 int n, virt_max_cpus; 1261 1261 MemoryRegion *ram = g_new(MemoryRegion, 1); 1262 1262 - const char *cpu_model = machine->cpu_model; 1263 1263 - char **cpustr; 1264 1264 - ObjectClass *oc; 1265 1265 - const char *typename; 1266 1266 - CPUClass *cc; 1267 1267 - Error *err = NULL; 1268 1262 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); 1269 1269 - 1270 1270 - if (!cpu_model) { 1271 1271 - cpu_model = "cortex-a15"; 1272 1272 - } 1273 1263 1274 1264 /* We can probe only here because during property set 1275 1265 * KVM is not available yet ··· 1287 1277 } 1288 1278 } 1289 1279 1290 1290 - /* Separate the actual CPU model name from any appended features */ 1291 1291 - cpustr = g_strsplit(cpu_model, ",", 2); 1292 1292 - 1293 1293 - if (!cpuname_valid(cpustr[0])) { 1294 1294 - error_report("mach-virt: CPU %s not supported", cpustr[0]); 1280 1280 + if (!cpu_type_valid(machine->cpu_type)) { 1281 1281 + error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 1295 1282 exit(1); 1296 1283 } 1297 1284 ··· 1361 1348 1362 1349 create_fdt(vms); 1363 1350 1364 1364 - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); 1365 1365 - if (!oc) { 1366 1366 - error_report("Unable to find CPU definition"); 1367 1367 - exit(1); 1368 1368 - } 1369 1369 - typename = object_class_get_name(oc); 1370 1370 - 1371 1371 - /* convert -smp CPU options specified by the user into global props */ 1372 1372 - cc = CPU_CLASS(oc); 1373 1373 - cc->parse_features(typename, cpustr[1], &err); 1374 1374 - g_strfreev(cpustr); 1375 1375 - if (err) { 1376 1376 - error_report_err(err); 1377 1377 - exit(1); 1378 1378 - } 1379 1379 - 1380 1351 possible_cpus = mc->possible_cpu_arch_ids(machine); 1381 1352 for (n = 0; n < possible_cpus->len; n++) { 1382 1353 Object *cpuobj; ··· 1386 1357 break; 1387 1358 } 1388 1359 1389 1389 - cpuobj = object_new(typename); 1360 1360 + cpuobj = object_new(machine->cpu_type); 1390 1361 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1391 1362 "mp-affinity", NULL); 1392 1363 ··· 1583 1554 return possible_cpus->cpus[cpu_index].props; 1584 1555 } 1585 1556 1557 1557 + static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1558 1558 + { 1559 1559 + return idx % nb_numa_nodes; 1560 1560 + } 1561 1561 + 1586 1562 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1587 1563 { 1588 1564 int n; ··· 1601 1577 virt_cpu_mp_affinity(vms, n); 1602 1578 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1603 1579 ms->possible_cpus->cpus[n].props.thread_id = n; 1604 1604 - 1605 1605 - /* default distribution of CPUs over NUMA nodes */ 1606 1606 - if (nb_numa_nodes) { 1607 1607 - /* preset values but do not enable them i.e. 'has_node_id = false', 1608 1608 - * numa init code will enable them later if manual mapping wasn't 1609 1609 - * present on CLI */ 1610 1610 - ms->possible_cpus->cpus[n].props.node_id = n % nb_numa_nodes; 1611 1611 - } 1612 1580 } 1613 1581 return ms->possible_cpus; 1614 1582 } ··· 1631 1599 mc->minimum_page_bits = 12; 1632 1600 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1633 1601 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1602 1602 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 1603 1603 + mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1634 1604 } 1635 1605 1636 1606 static const TypeInfo virt_machine_info = {

+2 -8

hw/arm/xilinx_zynq.c

··· 158 158 static void zynq_init(MachineState *machine) 159 159 { 160 160 ram_addr_t ram_size = machine->ram_size; 161 161 - const char *cpu_model = machine->cpu_model; 162 161 const char *kernel_filename = machine->kernel_filename; 163 162 const char *kernel_cmdline = machine->kernel_cmdline; 164 163 const char *initrd_filename = machine->initrd_filename; 165 165 - ObjectClass *cpu_oc; 166 164 ARMCPU *cpu; 167 165 MemoryRegion *address_space_mem = get_system_memory(); 168 166 MemoryRegion *ext_ram = g_new(MemoryRegion, 1); ··· 174 172 qemu_irq pic[64]; 175 173 int n; 176 174 177 177 - if (!cpu_model) { 178 178 - cpu_model = "cortex-a9"; 179 179 - } 180 180 - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 181 181 - 182 182 - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); 175 175 + cpu = ARM_CPU(object_new(machine->cpu_type)); 183 176 184 177 /* By default A9 CPUs have EL3 enabled. This board does not 185 178 * currently support EL3 so the CPU EL3 property is disabled before ··· 327 320 mc->max_cpus = 1; 328 321 mc->no_sdcard = 1; 329 322 mc->ignore_memory_transaction_failures = true; 323 323 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 330 324 } 331 325 332 326 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)

+3 -6

hw/arm/z2.c

··· 26 26 #include "audio/audio.h" 27 27 #include "exec/address-spaces.h" 28 28 #include "sysemu/qtest.h" 29 29 + #include "cpu.h" 29 30 30 31 #ifdef DEBUG_Z2 31 32 #define DPRINTF(fmt, ...) \ ··· 296 297 297 298 static void z2_init(MachineState *machine) 298 299 { 299 299 - const char *cpu_model = machine->cpu_model; 300 300 const char *kernel_filename = machine->kernel_filename; 301 301 const char *kernel_cmdline = machine->kernel_cmdline; 302 302 const char *initrd_filename = machine->initrd_filename; ··· 309 309 I2CBus *bus; 310 310 DeviceState *wm; 311 311 312 312 - if (!cpu_model) { 313 313 - cpu_model = "pxa270-c5"; 314 314 - } 315 315 - 316 312 /* Setup CPU & memory */ 317 317 - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model); 313 313 + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); 318 314 319 315 #ifdef TARGET_WORDS_BIGENDIAN 320 316 be = 1; ··· 371 367 mc->desc = "Zipit Z2 (PXA27x)"; 372 368 mc->init = z2_init; 373 369 mc->ignore_memory_transaction_failures = true; 370 370 + mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); 374 371 } 375 372 376 373 DEFINE_MACHINE("z2", z2_machine_init)

+1

hw/core/machine.c

··· 724 724 /* fetch default mapping from board and enable it */ 725 725 CpuInstanceProperties props = cpu_slot->props; 726 726 727 727 + props.node_id = mc->get_default_cpu_node_id(machine, i); 727 728 if (!default_mapping) { 728 729 /* record slots with not set mapping, 729 730 * TODO: make it hard error in future */

+22 -6

hw/i386/acpi-build.c

··· 2288 2288 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2289 2289 } 2290 2290 2291 2291 + #define HOLE_640K_START (640 * 1024) 2292 2292 + #define HOLE_640K_END (1024 * 1024) 2293 2293 + 2291 2294 static void 2292 2295 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2293 2296 { ··· 2343 2346 next_base = 0; 2344 2347 numa_start = table_data->len; 2345 2348 2346 2346 - numamem = acpi_data_push(table_data, sizeof *numamem); 2347 2347 - build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED); 2348 2348 - next_base = 1024 * 1024; 2349 2349 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2350 2350 mem_base = next_base; 2351 2351 mem_len = pcms->node_mem[i - 1]; 2352 2352 - if (i == 1) { 2353 2353 - mem_len -= 1024 * 1024; 2352 2352 + next_base = mem_base + mem_len; 2353 2353 + 2354 2354 + /* Cut out the 640K hole */ 2355 2355 + if (mem_base <= HOLE_640K_START && 2356 2356 + next_base > HOLE_640K_START) { 2357 2357 + mem_len -= next_base - HOLE_640K_START; 2358 2358 + if (mem_len > 0) { 2359 2359 + numamem = acpi_data_push(table_data, sizeof *numamem); 2360 2360 + build_srat_memory(numamem, mem_base, mem_len, i - 1, 2361 2361 + MEM_AFFINITY_ENABLED); 2362 2362 + } 2363 2363 + 2364 2364 + /* Check for the rare case: 640K < RAM < 1M */ 2365 2365 + if (next_base <= HOLE_640K_END) { 2366 2366 + next_base = HOLE_640K_END; 2367 2367 + continue; 2368 2368 + } 2369 2369 + mem_base = HOLE_640K_END; 2370 2370 + mem_len = next_base - HOLE_640K_END; 2354 2371 } 2355 2355 - next_base = mem_base + mem_len; 2356 2372 2357 2373 /* Cut out the ACPI_PCI hole */ 2358 2374 if (mem_base <= pcms->below_4g_mem_size &&

+16 -45

hw/i386/pc.c

··· 1107 1107 1108 1108 void pc_hot_add_cpu(const int64_t id, Error **errp) 1109 1109 { 1110 1110 - ObjectClass *oc; 1111 1110 MachineState *ms = MACHINE(qdev_get_machine()); 1112 1111 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1113 1112 Error *local_err = NULL; ··· 1124 1123 return; 1125 1124 } 1126 1125 1127 1127 - assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */ 1128 1128 - oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu)); 1129 1129 - pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); 1126 1126 + pc_new_cpu(ms->cpu_type, apic_id, &local_err); 1130 1127 if (local_err) { 1131 1128 error_propagate(errp, local_err); 1132 1129 return; ··· 1136 1133 void pc_cpus_init(PCMachineState *pcms) 1137 1134 { 1138 1135 int i; 1139 1139 - CPUClass *cc; 1140 1140 - ObjectClass *oc; 1141 1141 - const char *typename; 1142 1142 - gchar **model_pieces; 1143 1136 const CPUArchIdList *possible_cpus; 1144 1144 - MachineState *machine = MACHINE(pcms); 1137 1137 + MachineState *ms = MACHINE(pcms); 1145 1138 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1146 1139 1147 1147 - /* init CPUs */ 1148 1148 - if (machine->cpu_model == NULL) { 1149 1149 - #ifdef TARGET_X86_64 1150 1150 - machine->cpu_model = "qemu64"; 1151 1151 - #else 1152 1152 - machine->cpu_model = "qemu32"; 1153 1153 - #endif 1154 1154 - } 1155 1155 - 1156 1156 - model_pieces = g_strsplit(machine->cpu_model, ",", 2); 1157 1157 - if (!model_pieces[0]) { 1158 1158 - error_report("Invalid/empty CPU model name"); 1159 1159 - exit(1); 1160 1160 - } 1161 1161 - 1162 1162 - oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); 1163 1163 - if (oc == NULL) { 1164 1164 - error_report("Unable to find CPU definition: %s", model_pieces[0]); 1165 1165 - exit(1); 1166 1166 - } 1167 1167 - typename = object_class_get_name(oc); 1168 1168 - cc = CPU_CLASS(oc); 1169 1169 - cc->parse_features(typename, model_pieces[1], &error_fatal); 1170 1170 - g_strfreev(model_pieces); 1171 1171 - 1172 1140 /* Calculates the limit to CPU APIC ID values 1173 1141 * 1174 1142 * Limit for the APIC ID value, so that all ··· 1177 1145 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1178 1146 */ 1179 1147 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1180 1180 - possible_cpus = mc->possible_cpu_arch_ids(machine); 1148 1148 + possible_cpus = mc->possible_cpu_arch_ids(ms); 1181 1149 for (i = 0; i < smp_cpus; i++) { 1182 1182 - pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal); 1150 1150 + pc_new_cpu(ms->cpu_type, possible_cpus->cpus[i].arch_id, &error_fatal); 1183 1151 } 1184 1152 } 1185 1153 ··· 2265 2233 return possible_cpus->cpus[cpu_index].props; 2266 2234 } 2267 2235 2236 2236 + static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2237 2237 + { 2238 2238 + X86CPUTopoInfo topo; 2239 2239 + 2240 2240 + assert(idx < ms->possible_cpus->len); 2241 2241 + x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2242 2242 + smp_cores, smp_threads, &topo); 2243 2243 + return topo.pkg_id % nb_numa_nodes; 2244 2244 + } 2245 2245 + 2268 2246 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2269 2247 { 2270 2248 int i; ··· 2294 2272 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2295 2273 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2296 2274 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2297 2297 - 2298 2298 - /* default distribution of CPUs over NUMA nodes */ 2299 2299 - if (nb_numa_nodes) { 2300 2300 - /* preset values but do not enable them i.e. 'has_node_id = false', 2301 2301 - * numa init code will enable them later if manual mapping wasn't 2302 2302 - * present on CLI */ 2303 2303 - ms->possible_cpus->cpus[i].props.node_id = 2304 2304 - topo.pkg_id % nb_numa_nodes; 2305 2305 - } 2306 2275 } 2307 2276 return ms->possible_cpus; 2308 2277 } ··· 2347 2316 pcmc->linuxboot_dma_enabled = true; 2348 2317 mc->get_hotplug_handler = pc_get_hotpug_handler; 2349 2318 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2319 2319 + mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2350 2320 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2351 2321 mc->has_hotpluggable_cpus = true; 2352 2322 mc->default_boot_order = "cad"; ··· 2359 2329 hc->unplug_request = pc_machine_device_unplug_request_cb; 2360 2330 hc->unplug = pc_machine_device_unplug_cb; 2361 2331 nc->nmi_monitor_handler = x86_nmi; 2332 2332 + mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2362 2333 2363 2334 object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", 2364 2335 pc_machine_get_hotplug_memory_region_size, NULL,

+1 -3

hw/i386/pc_piix.c

··· 378 378 379 379 static void pc_init_isa(MachineState *machine) 380 380 { 381 381 - if (!machine->cpu_model) { 382 382 - machine->cpu_model = "486"; 383 383 - } 384 381 x86_cpu_change_kvm_default("kvm-pv-eoi", NULL); 385 382 enable_compat_apic_id_mode(); 386 383 pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, TYPE_I440FX_PCI_DEVICE); ··· 1113 1110 pcmc->gigabyte_align = false; 1114 1111 pcmc->smbios_legacy_mode = true; 1115 1112 pcmc->has_reserved_memory = false; 1113 1113 + m->default_cpu_type = X86_CPU_TYPE_NAME("486"); 1116 1114 } 1117 1115 1118 1116 DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa,

-8

hw/lm32/lm32_boards.c

··· 105 105 cpu_model = "lm32-full"; 106 106 } 107 107 cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); 108 108 - if (cpu == NULL) { 109 109 - fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model); 110 110 - exit(1); 111 111 - } 112 108 113 109 env = &cpu->env; 114 110 reset_info->cpu = cpu; ··· 206 202 cpu_model = "lm32-full"; 207 203 } 208 204 cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); 209 209 - if (cpu == NULL) { 210 210 - fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model); 211 211 - exit(1); 212 212 - } 213 205 214 206 env = &cpu->env; 215 207 reset_info->cpu = cpu;

-4

hw/lm32/milkymist.c

··· 112 112 cpu_model = "lm32-full"; 113 113 } 114 114 cpu = LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); 115 115 - if (cpu == NULL) { 116 116 - fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model); 117 117 - exit(1); 118 118 - } 119 115 120 116 env = &cpu->env; 121 117 reset_info->cpu = cpu;

-4

hw/m68k/an5206.c

··· 43 43 cpu_model = "m5206"; 44 44 } 45 45 cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model)); 46 46 - if (!cpu) { 47 47 - error_report("Unable to find m68k CPU definition"); 48 48 - exit(1); 49 49 - } 50 46 env = &cpu->env; 51 47 52 48 /* Initialize CPU registers. */

-4

hw/m68k/mcf5208.c

··· 233 233 cpu_model = "m5208"; 234 234 } 235 235 cpu = M68K_CPU(cpu_generic_init(TYPE_M68K_CPU, cpu_model)); 236 236 - if (!cpu) { 237 237 - fprintf(stderr, "Unable to find m68k CPU definition\n"); 238 238 - exit(1); 239 239 - } 240 236 env = &cpu->env; 241 237 242 238 /* Initialize CPU registers. */

-4

hw/mips/cps.c

··· 72 72 73 73 for (i = 0; i < s->num_vp; i++) { 74 74 cpu = cpu_mips_init(s->cpu_model); 75 75 - if (cpu == NULL) { 76 76 - error_setg(errp, "%s: CPU initialization failed", __func__); 77 77 - return; 78 78 - } 79 75 80 76 /* Init internal devices */ 81 77 cpu_mips_irq_init_cpu(cpu);

-4

hw/mips/mips_fulong2e.c

··· 281 281 cpu_model = "Loongson-2E"; 282 282 } 283 283 cpu = cpu_mips_init(cpu_model); 284 284 - if (cpu == NULL) { 285 285 - fprintf(stderr, "Unable to find CPU definition\n"); 286 286 - exit(1); 287 287 - } 288 284 env = &cpu->env; 289 285 290 286 qemu_register_reset(main_cpu_reset, cpu);

-4

hw/mips/mips_jazz.c

··· 152 152 cpu_model = "R4000"; 153 153 } 154 154 cpu = cpu_mips_init(cpu_model); 155 155 - if (cpu == NULL) { 156 156 - fprintf(stderr, "Unable to find CPU definition\n"); 157 157 - exit(1); 158 158 - } 159 155 env = &cpu->env; 160 156 qemu_register_reset(main_cpu_reset, cpu); 161 157

-4

hw/mips/mips_malta.c

··· 932 932 933 933 for (i = 0; i < smp_cpus; i++) { 934 934 cpu = cpu_mips_init(cpu_model); 935 935 - if (cpu == NULL) { 936 936 - fprintf(stderr, "Unable to find CPU definition\n"); 937 937 - exit(1); 938 938 - } 939 935 940 936 /* Init internal devices */ 941 937 cpu_mips_irq_init_cpu(cpu);

-4

hw/mips/mips_mipssim.c

··· 164 164 #endif 165 165 } 166 166 cpu = cpu_mips_init(cpu_model); 167 167 - if (cpu == NULL) { 168 168 - fprintf(stderr, "Unable to find CPU definition\n"); 169 169 - exit(1); 170 170 - } 171 167 env = &cpu->env; 172 168 173 169 reset_info = g_malloc0(sizeof(ResetData));

-4

hw/mips/mips_r4k.c

··· 194 194 #endif 195 195 } 196 196 cpu = cpu_mips_init(cpu_model); 197 197 - if (cpu == NULL) { 198 198 - fprintf(stderr, "Unable to find CPU definition\n"); 199 199 - exit(1); 200 200 - } 201 197 env = &cpu->env; 202 198 203 199 reset_info = g_malloc0(sizeof(ResetData));

-4

hw/moxie/moxiesim.c

··· 119 119 cpu_model = "MoxieLite-moxie-cpu"; 120 120 } 121 121 cpu = MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)); 122 122 - if (!cpu) { 123 123 - fprintf(stderr, "Unable to find CPU definition\n"); 124 124 - exit(1); 125 125 - } 126 122 env = &cpu->env; 127 123 128 124 qemu_register_reset(main_cpu_reset, cpu);

-4

hw/openrisc/openrisc_sim.c

··· 110 110 111 111 for (n = 0; n < smp_cpus; n++) { 112 112 cpu = OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); 113 113 - if (cpu == NULL) { 114 114 - fprintf(stderr, "Unable to find CPU definition!\n"); 115 115 - exit(1); 116 116 - } 117 113 qemu_register_reset(main_cpu_reset, cpu); 118 114 main_cpu_reset(cpu); 119 115 }

-4

hw/ppc/e500.c

··· 817 817 818 818 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 819 819 machine->cpu_model)); 820 820 - if (cpu == NULL) { 821 821 - fprintf(stderr, "Unable to initialize CPU!\n"); 822 822 - exit(1); 823 823 - } 824 820 env = &cpu->env; 825 821 cs = CPU(cpu); 826 822

-4

hw/ppc/mac_newworld.c

··· 189 189 for (i = 0; i < smp_cpus; i++) { 190 190 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 191 191 machine->cpu_model)); 192 192 - if (cpu == NULL) { 193 193 - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 194 194 - exit(1); 195 195 - } 196 192 env = &cpu->env; 197 193 198 194 /* Set time-base frequency to 100 Mhz */

-4

hw/ppc/mac_oldworld.c

··· 118 118 for (i = 0; i < smp_cpus; i++) { 119 119 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 120 120 machine->cpu_model)); 121 121 - if (cpu == NULL) { 122 122 - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 123 123 - exit(1); 124 124 - } 125 121 env = &cpu->env; 126 122 127 123 /* Set time-base frequency to 16.6 Mhz */

-4

hw/ppc/ppc440_bamboo.c

··· 187 187 machine->cpu_model = "440EP"; 188 188 } 189 189 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); 190 190 - if (cpu == NULL) { 191 191 - fprintf(stderr, "Unable to initialize CPU!\n"); 192 192 - exit(1); 193 193 - } 194 190 env = &cpu->env; 195 191 196 192 if (env->mmu_model != POWERPC_MMU_BOOKE) {

-5

hw/ppc/ppc4xx_devs.c

··· 57 57 58 58 /* init CPUs */ 59 59 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); 60 60 - if (cpu == NULL) { 61 61 - fprintf(stderr, "Unable to find PowerPC %s CPU definition\n", 62 62 - cpu_model); 63 63 - exit(1); 64 64 - } 65 60 env = &cpu->env; 66 61 67 62 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */

-9

hw/ppc/prep.c

··· 522 522 for (i = 0; i < smp_cpus; i++) { 523 523 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 524 524 machine->cpu_model)); 525 525 - if (cpu == NULL) { 526 526 - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 527 527 - exit(1); 528 528 - } 529 525 env = &cpu->env; 530 526 531 527 if (env->flags & POWERPC_FLAG_RTC_CLK) { ··· 726 722 machine->cpu_model = "604"; 727 723 } 728 724 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, machine->cpu_model)); 729 729 - if (!cpu) { 730 730 - error_report("could not initialize CPU '%s'", 731 731 - machine->cpu_model); 732 732 - exit(1); 733 733 - } 734 725 env = &cpu->env; 735 726 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 736 727 error_report("only 6xx bus is supported on this machine");

+6 -9

hw/ppc/spapr.c

··· 3404 3404 return core_slot->props; 3405 3405 } 3406 3406 3407 3407 + static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3408 3408 + { 3409 3409 + return idx / smp_cores % nb_numa_nodes; 3410 3410 + } 3411 3411 + 3407 3412 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3408 3413 { 3409 3414 int i; ··· 3428 3433 machine->possible_cpus->cpus[i].arch_id = core_id; 3429 3434 machine->possible_cpus->cpus[i].props.has_core_id = true; 3430 3435 machine->possible_cpus->cpus[i].props.core_id = core_id; 3431 3431 - 3432 3432 - /* default distribution of CPUs over NUMA nodes */ 3433 3433 - if (nb_numa_nodes) { 3434 3434 - /* preset values but do not enable them i.e. 'has_node_id = false', 3435 3435 - * numa init code will enable them later if manual mapping wasn't 3436 3436 - * present on CLI */ 3437 3437 - machine->possible_cpus->cpus[i].props.node_id = 3438 3438 - core_id / smp_threads / smp_cores % nb_numa_nodes; 3439 3439 - } 3440 3436 } 3441 3437 return machine->possible_cpus; 3442 3438 } ··· 3587 3583 hc->pre_plug = spapr_machine_device_pre_plug; 3588 3584 hc->plug = spapr_machine_device_plug; 3589 3585 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3586 3586 + mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3590 3587 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3591 3588 hc->unplug_request = spapr_machine_device_unplug_request; 3592 3589

-4

hw/ppc/virtex_ml507.c

··· 97 97 qemu_irq *irqs; 98 98 99 99 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); 100 100 - if (cpu == NULL) { 101 101 - fprintf(stderr, "Unable to initialize CPU!\n"); 102 102 - exit(1); 103 103 - } 104 100 env = &cpu->env; 105 101 106 102 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);

-4

hw/sh4/r2d.c

··· 247 247 } 248 248 249 249 cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); 250 250 - if (cpu == NULL) { 251 251 - fprintf(stderr, "Unable to find CPU definition\n"); 252 252 - exit(1); 253 253 - } 254 250 env = &cpu->env; 255 251 256 252 reset_info = g_malloc0(sizeof(ResetData));

-4

hw/sh4/shix.c

··· 57 57 cpu_model = "any"; 58 58 59 59 cpu = SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); 60 60 - if (cpu == NULL) { 61 61 - fprintf(stderr, "Unable to find CPU definition\n"); 62 62 - exit(1); 63 63 - } 64 60 65 61 /* Allocate memory space */ 66 62 memory_region_init_ram(rom, NULL, "shix.rom", 0x4000, &error_fatal);

-4

hw/sparc/leon3.c

··· 127 127 } 128 128 129 129 cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); 130 130 - if (cpu == NULL) { 131 131 - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 132 132 - exit(1); 133 133 - } 134 130 env = &cpu->env; 135 131 136 132 cpu_sparc_set_id(env, 0);

-4

hw/sparc/sun4m.c

··· 798 798 CPUSPARCState *env; 799 799 800 800 cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); 801 801 - if (cpu == NULL) { 802 802 - fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 803 803 - exit(1); 804 804 - } 805 801 env = &cpu->env; 806 802 807 803 cpu_sparc_set_id(env, id);

-4

hw/sparc64/sparc64.c

··· 354 354 cpu_model = default_cpu_model; 355 355 } 356 356 cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); 357 357 - if (cpu == NULL) { 358 358 - fprintf(stderr, "Unable to find Sparc CPU definition\n"); 359 359 - exit(1); 360 360 - } 361 357 env = &cpu->env; 362 358 363 359 env->tick = cpu_timer_create("tick", cpu, tick_irq,

-4

hw/tricore/tricore_testboard.c

··· 75 75 machine->cpu_model = "tc1796"; 76 76 } 77 77 cpu = TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, machine->cpu_model)); 78 78 - if (!cpu) { 79 79 - error_report("Unable to find CPU definition"); 80 80 - exit(1); 81 81 - } 82 78 env = &cpu->env; 83 79 memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", 84 80 2 * 1024 * 1024, &error_fatal);

-4

hw/unicore32/puv3.c

··· 128 128 } 129 129 130 130 cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); 131 131 - if (!cpu) { 132 132 - error_report("Unable to find CPU definition"); 133 133 - exit(1); 134 134 - } 135 131 env = &cpu->env; 136 132 137 133 puv3_soc_init(env);

-5

hw/xtensa/sim.c

··· 85 85 86 86 for (n = 0; n < smp_cpus; n++) { 87 87 cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)); 88 88 - if (cpu == NULL) { 89 89 - error_report("unable to find CPU definition '%s'", 90 90 - cpu_model); 91 91 - exit(EXIT_FAILURE); 92 92 - } 93 88 env = &cpu->env; 94 89 95 90 env->sregs[PRID] = n;

-5

hw/xtensa/xtfpga.c

··· 233 233 234 234 for (n = 0; n < smp_cpus; n++) { 235 235 cpu = XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)); 236 236 - if (cpu == NULL) { 237 237 - error_report("unable to find CPU definition '%s'", 238 238 - cpu_model); 239 239 - exit(EXIT_FAILURE); 240 240 - } 241 236 env = &cpu->env; 242 237 243 238 env->sregs[PRID] = n;

+2 -2

include/hw/arm/armv7m.h

··· 35 35 /* ARMv7M container object. 36 36 * + Unnamed GPIO input lines: external IRQ lines for the NVIC 37 37 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ 38 38 - * + Property "cpu-model": CPU model to instantiate 38 38 + * + Property "cpu-type": CPU type to instantiate 39 39 * + Property "num-irq": number of external IRQ lines 40 40 * + Property "memory": MemoryRegion defining the physical address space 41 41 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal ··· 55 55 MemoryRegion container; 56 56 57 57 /* Properties */ 58 58 - char *cpu_model; 58 58 + char *cpu_type; 59 59 /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ 60 60 MemoryRegion *board_memory; 61 61 } ARMv7MState;

+1 -1

include/hw/arm/aspeed_soc.h

··· 49 49 50 50 typedef struct AspeedSoCInfo { 51 51 const char *name; 52 52 - const char *cpu_model; 52 52 + const char *cpu_type; 53 53 uint32_t silicon_rev; 54 54 hwaddr sdram_base; 55 55 uint64_t sram_size;

+1 -1

include/hw/arm/stm32f205_soc.h

··· 52 52 SysBusDevice parent_obj; 53 53 /*< public >*/ 54 54 55 55 - char *cpu_model; 55 55 + char *cpu_type; 56 56 57 57 ARMv7MState armv7m; 58 58

+10

include/hw/boards.h

··· 123 123 * Returns an array of @CPUArchId architecture-dependent CPU IDs 124 124 * which includes CPU IDs for present and possible to hotplug CPUs. 125 125 * Caller is responsible for freeing returned list. 126 126 + * @get_default_cpu_node_id: 127 127 + * returns default board specific node_id value for CPU slot specified by 128 128 + * index @idx in @ms->possible_cpus[] 126 129 * @has_hotpluggable_cpus: 127 130 * If true, board supports CPUs creation with -device/device_add. 131 131 + * @default_cpu_type: 132 132 + * specifies default CPU_TYPE, which will be used for parsing target 133 133 + * specific features and for creating CPUs if CPU name wasn't provided 134 134 + * explicitly at CLI 128 135 * @minimum_page_bits: 129 136 * If non-zero, the board promises never to create a CPU with a page size 130 137 * smaller than this, so QEMU can use a more efficient larger page ··· 177 184 GArray *compat_props; 178 185 const char *hw_version; 179 186 ram_addr_t default_ram_size; 187 187 + const char *default_cpu_type; 180 188 bool option_rom_has_mr; 181 189 bool rom_file_has_mr; 182 190 int minimum_page_bits; ··· 191 199 CpuInstanceProperties (*cpu_index_to_instance_props)(MachineState *machine, 192 200 unsigned cpu_index); 193 201 const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine); 202 202 + int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx); 194 203 }; 195 204 196 205 /** ··· 231 240 char *kernel_cmdline; 232 241 char *initrd_filename; 233 242 const char *cpu_model; 243 243 + const char *cpu_type; 234 244 AccelState *accelerator; 235 245 CPUArchIdList *possible_cpus; 236 246 };

+7

include/qemu/osdep.h

··· 273 273 #else 274 274 #define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID 275 275 #endif 276 276 + #ifdef MADV_REMOVE 277 277 + #define QEMU_MADV_REMOVE MADV_REMOVE 278 278 + #else 279 279 + #define QEMU_MADV_REMOVE QEMU_MADV_INVALID 280 280 + #endif 276 281 277 282 #elif defined(CONFIG_POSIX_MADVISE) 278 283 ··· 285 290 #define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID 286 291 #define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID 287 292 #define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID 293 293 + #define QEMU_MADV_REMOVE QEMU_MADV_INVALID 288 294 289 295 #else /* no-op */ 290 296 ··· 297 303 #define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID 298 304 #define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID 299 305 #define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID 306 306 + #define QEMU_MADV_REMOVE QEMU_MADV_INVALID 300 307 301 308 #endif 302 309

+22

include/qom/cpu.h

··· 645 645 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); 646 646 647 647 /** 648 648 + * cpu_create: 649 649 + * @typename: The CPU type. 650 650 + * 651 651 + * Instantiates a CPU and realizes the CPU. 652 652 + * 653 653 + * Returns: A #CPUState or %NULL if an error occurred. 654 654 + */ 655 655 + CPUState *cpu_create(const char *typename); 656 656 + 657 657 + /** 658 658 + * cpu_parse_cpu_model: 659 659 + * @typename: The CPU base type or CPU type. 660 660 + * @cpu_model: The model string including optional parameters. 661 661 + * 662 662 + * processes optional parameters and registers them as global properties 663 663 + * 664 664 + * Returns: type of CPU to create or prints error and terminates process 665 665 + * if an error occurred. 666 666 + */ 667 667 + const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model); 668 668 + 669 669 + /** 648 670 * cpu_generic_init: 649 671 * @typename: The CPU base type. 650 672 * @cpu_model: The model string including optional parameters.

+8

include/qom/object_interfaces.h

··· 147 147 */ 148 148 void user_creatable_del(const char *id, Error **errp); 149 149 150 150 + /** 151 151 + * user_creatable_cleanup: 152 152 + * 153 153 + * Delete all user-creatable objects and the user-creatable 154 154 + * objects container. 155 155 + */ 156 156 + void user_creatable_cleanup(void); 157 157 + 150 158 #endif

-4

linux-user/main.c

··· 4323 4323 /* NOTE: we need to init the CPU at this stage to get 4324 4324 qemu_host_page_size */ 4325 4325 cpu = cpu_init(cpu_model); 4326 4326 - if (!cpu) { 4327 4327 - fprintf(stderr, "Unable to find CPU definition\n"); 4328 4328 - exit(EXIT_FAILURE); 4329 4329 - } 4330 4326 env = cpu->env_ptr; 4331 4327 cpu_reset(cpu); 4332 4328

+1 -1

numa.c

··· 567 567 } 568 568 569 569 memory_region_init(mr, owner, name, ram_size); 570 570 - for (i = 0; i < MAX_NODES; i++) { 570 570 + for (i = 0; i < nb_numa_nodes; i++) { 571 571 uint64_t size = numa_info[i].node_mem; 572 572 HostMemoryBackend *backend = numa_info[i].node_memdev; 573 573 if (!backend) {

+7 -1

qemu-options.hx

··· 4182 4182 4183 4183 @table @option 4184 4184 4185 4185 - @item -object memory-backend-file,id=@var{id},size=@var{size},mem-path=@var{dir},share=@var{on|off} 4185 4185 + @item -object memory-backend-file,id=@var{id},size=@var{size},mem-path=@var{dir},share=@var{on|off},discard-data=@var{on|off} 4186 4186 4187 4187 Creates a memory file backend object, which can be used to back 4188 4188 the guest RAM with huge pages. The @option{id} parameter is a ··· 4194 4194 The @option{share} boolean option determines whether the memory 4195 4195 region is marked as private to QEMU, or shared. The latter allows 4196 4196 a co-operating external process to access the QEMU memory region. 4197 4197 + Setting the @option{discard-data} boolean option to @var{on} 4198 4198 + indicates that file contents can be destroyed when QEMU exits, 4199 4199 + to avoid unnecessarily flushing data to the backing file. Note 4200 4200 + that @option{discard-data} is only an optimization, and QEMU 4201 4201 + might not discard file contents if it aborts unexpectedly or is 4202 4202 + terminated using SIGKILL. 4197 4203 4198 4204 @item -object rng-random,id=@var{id},filename=@var{/dev/random} 4199 4205

+27 -22

qom/cpu.c

··· 54 54 return !!cpu_by_arch_id(id); 55 55 } 56 56 57 57 - CPUState *cpu_generic_init(const char *typename, const char *cpu_model) 57 57 + CPUState *cpu_create(const char *typename) 58 58 + { 59 59 + Error *err = NULL; 60 60 + CPUState *cpu = CPU(object_new(typename)); 61 61 + object_property_set_bool(OBJECT(cpu), true, "realized", &err); 62 62 + if (err != NULL) { 63 63 + error_report_err(err); 64 64 + object_unref(OBJECT(cpu)); 65 65 + exit(EXIT_FAILURE); 66 66 + } 67 67 + return cpu; 68 68 + } 69 69 + 70 70 + const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model) 58 71 { 59 59 - CPUState *cpu = NULL; 60 72 ObjectClass *oc; 61 73 CPUClass *cc; 62 62 - Error *err = NULL; 63 74 gchar **model_pieces; 75 75 + const char *cpu_type; 64 76 65 77 model_pieces = g_strsplit(cpu_model, ",", 2); 66 78 67 79 oc = cpu_class_by_name(typename, model_pieces[0]); 68 80 if (oc == NULL) { 81 81 + error_report("unable to find CPU model '%s'", model_pieces[0]); 69 82 g_strfreev(model_pieces); 70 70 - return NULL; 83 83 + exit(EXIT_FAILURE); 71 84 } 72 85 86 86 + cpu_type = object_class_get_name(oc); 73 87 cc = CPU_CLASS(oc); 88 88 + cc->parse_features(cpu_type, model_pieces[1], &error_fatal); 89 89 + g_strfreev(model_pieces); 90 90 + return cpu_type; 91 91 + } 92 92 + 93 93 + CPUState *cpu_generic_init(const char *typename, const char *cpu_model) 94 94 + { 74 95 /* TODO: all callers of cpu_generic_init() need to be converted to 75 75 - * call parse_features() only once, before calling cpu_generic_init(). 96 96 + * call cpu_parse_features() only once, before calling cpu_generic_init(). 76 97 */ 77 77 - cc->parse_features(object_class_get_name(oc), model_pieces[1], &err); 78 78 - g_strfreev(model_pieces); 79 79 - if (err != NULL) { 80 80 - goto out; 81 81 - } 82 82 - 83 83 - cpu = CPU(object_new(object_class_get_name(oc))); 84 84 - object_property_set_bool(OBJECT(cpu), true, "realized", &err); 85 85 - 86 86 - out: 87 87 - if (err != NULL) { 88 88 - error_report_err(err); 89 89 - object_unref(OBJECT(cpu)); 90 90 - return NULL; 91 91 - } 92 92 - 93 93 - return cpu; 98 98 + return cpu_create(cpu_parse_cpu_model(typename, cpu_model)); 94 99 } 95 100 96 101 bool cpu_paging_enabled(const CPUState *cpu)

+5

qom/object_interfaces.c

··· 193 193 object_unparent(obj); 194 194 } 195 195 196 196 + void user_creatable_cleanup(void) 197 197 + { 198 198 + object_unparent(object_get_objects_root()); 199 199 + } 200 200 + 196 201 static void register_types(void) 197 202 { 198 203 static const TypeInfo uc_interface_info = {

+1 -1

target/arm/cpu.c

··· 911 911 } 912 912 913 913 cpuname = g_strsplit(cpu_model, ",", 1); 914 914 - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 914 914 + typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 915 915 oc = object_class_by_name(typename); 916 916 g_strfreev(cpuname); 917 917 g_free(typename);

+3

target/arm/cpu.h

··· 2091 2091 2092 2092 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model) 2093 2093 2094 2094 + #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2095 2095 + #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2096 2096 + 2094 2097 #define cpu_signal_handler cpu_arm_signal_handler 2095 2098 #define cpu_list arm_cpu_list 2096 2099

-3

target/i386/cpu.c

··· 705 705 706 706 /* CPU class name definitions: */ 707 707 708 708 - #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 709 709 - #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 710 710 - 711 708 /* Return type name for a given CPU model name 712 709 * Caller is responsible for freeing the returned string. 713 710 */

+9

target/i386/cpu.h

··· 1510 1510 1511 1511 #define cpu_init(cpu_model) cpu_generic_init(TYPE_X86_CPU, cpu_model) 1512 1512 1513 1513 + #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU 1514 1514 + #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) 1515 1515 + 1516 1516 + #ifdef TARGET_X86_64 1517 1517 + #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") 1518 1518 + #else 1519 1519 + #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") 1520 1520 + #endif 1521 1521 + 1513 1522 #define cpu_signal_handler cpu_x86_signal_handler 1514 1523 #define cpu_list x86_cpu_list 1515 1524

+11

vl.c

··· 4716 4716 current_machine->boot_order = boot_order; 4717 4717 current_machine->cpu_model = cpu_model; 4718 4718 4719 4719 + 4720 4720 + /* parse features once if machine provides default cpu_type */ 4721 4721 + if (machine_class->default_cpu_type) { 4722 4722 + current_machine->cpu_type = machine_class->default_cpu_type; 4723 4723 + if (cpu_model) { 4724 4724 + current_machine->cpu_type = 4725 4725 + cpu_parse_cpu_model(machine_class->default_cpu_type, cpu_model); 4726 4726 + } 4727 4727 + } 4728 4728 + 4719 4729 machine_run_board_init(current_machine); 4720 4730 4721 4731 realtime_init(); ··· 4887 4897 audio_cleanup(); 4888 4898 monitor_cleanup(); 4889 4899 qemu_chr_cleanup(); 4900 4900 + user_creatable_cleanup(); 4890 4901 /* TODO: unref root container, check all devices are ok */ 4891 4902 4892 4903 return 0;