jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/i386/pc: Extract the port92 device
This device is only used by the PC machines. The pc.c file is
already big enough, with 2255 lines. By removing 113 lines of
it, we reduced it by 5%. It is now a bit easier to navigate
the file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
authored by
Philippe Mathieu-Daudé
and committed by
Paolo Bonzini
d3e07dc8
1820b70e
+131
-114
+1
hw/i386/Makefile.objs
+1
hw/i386/Makefile.objs
-113
hw/i386/pc.c
-113
hw/i386/pc.c
···
673
673
qemu_register_reset(pc_cmos_init_late, &arg);
674
674
}
675
675
676
-
#define TYPE_PORT92 "port92"
677
-
#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
678
-
679
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/* port 92 stuff: could be split off */
680
-
typedef struct Port92State {
681
-
ISADevice parent_obj;
682
-
683
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MemoryRegion io;
684
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uint8_t outport;
685
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qemu_irq a20_out;
686
-
} Port92State;
687
-
688
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static void port92_write(void *opaque, hwaddr addr, uint64_t val,
689
-
unsigned size)
690
-
{
691
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Port92State *s = opaque;
692
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int oldval = s->outport;
693
-
694
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trace_port92_write(val);
695
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s->outport = val;
696
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qemu_set_irq(s->a20_out, (val >> 1) & 1);
697
-
if ((val & 1) && !(oldval & 1)) {
698
-
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
699
-
}
700
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}
701
-
702
-
static uint64_t port92_read(void *opaque, hwaddr addr,
703
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unsigned size)
704
-
{
705
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Port92State *s = opaque;
706
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uint32_t ret;
707
-
708
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ret = s->outport;
709
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trace_port92_read(ret);
710
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return ret;
711
-
}
712
-
713
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static const VMStateDescription vmstate_port92_isa = {
714
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.name = "port92",
715
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.version_id = 1,
716
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.minimum_version_id = 1,
717
-
.fields = (VMStateField[]) {
718
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VMSTATE_UINT8(outport, Port92State),
719
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VMSTATE_END_OF_LIST()
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}
721
-
};
722
-
723
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static void port92_reset(DeviceState *d)
724
-
{
725
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Port92State *s = PORT92(d);
726
-
727
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s->outport &= ~1;
728
-
}
729
-
730
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static const MemoryRegionOps port92_ops = {
731
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.read = port92_read,
732
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.write = port92_write,
733
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.impl = {
734
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.min_access_size = 1,
735
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.max_access_size = 1,
736
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},
737
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.endianness = DEVICE_LITTLE_ENDIAN,
738
-
};
739
-
740
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static void port92_initfn(Object *obj)
741
-
{
742
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Port92State *s = PORT92(obj);
743
-
744
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memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
745
-
746
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s->outport = 0;
747
-
748
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qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
749
-
}
750
-
751
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static void port92_realizefn(DeviceState *dev, Error **errp)
752
-
{
753
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ISADevice *isadev = ISA_DEVICE(dev);
754
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Port92State *s = PORT92(dev);
755
-
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isa_register_ioport(isadev, &s->io, 0x92);
757
-
}
758
-
759
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static void port92_class_initfn(ObjectClass *klass, void *data)
760
-
{
761
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DeviceClass *dc = DEVICE_CLASS(klass);
762
-
763
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dc->realize = port92_realizefn;
764
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dc->reset = port92_reset;
765
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dc->vmsd = &vmstate_port92_isa;
766
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/*
767
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* Reason: unlike ordinary ISA devices, this one needs additional
768
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* wiring: its A20 output line needs to be wired up with
769
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* qdev_connect_gpio_out_named().
770
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*/
771
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dc->user_creatable = false;
772
-
}
773
-
774
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static const TypeInfo port92_info = {
775
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.name = TYPE_PORT92,
776
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.parent = TYPE_ISA_DEVICE,
777
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.instance_size = sizeof(Port92State),
778
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.instance_init = port92_initfn,
779
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.class_init = port92_class_initfn,
780
-
};
781
-
782
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static void port92_register_types(void)
783
-
{
784
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type_register_static(&port92_info);
785
-
}
786
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787
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type_init(port92_register_types)
788
-
789
676
static void handle_a20_line_change(void *opaque, int irq, int level)
790
677
{
791
678
X86CPU *cpu = opaque;
+126
hw/i386/port92.c
+126
hw/i386/port92.c
···
1
+
/*
2
+
* QEMU I/O port 0x92 (System Control Port A, to handle Fast Gate A20)
3
+
*
4
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* Copyright (c) 2003-2004 Fabrice Bellard
5
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*
6
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* SPDX-License-Identifier: MIT
7
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*/
8
+
9
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#include "qemu/osdep.h"
10
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#include "sysemu/runstate.h"
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+
#include "migration/vmstate.h"
12
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#include "hw/irq.h"
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#include "hw/i386/pc.h"
14
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#include "trace.h"
15
+
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#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
17
+
18
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typedef struct Port92State {
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ISADevice parent_obj;
20
+
21
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MemoryRegion io;
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uint8_t outport;
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qemu_irq a20_out;
24
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} Port92State;
25
+
26
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static void port92_write(void *opaque, hwaddr addr, uint64_t val,
27
+
unsigned size)
28
+
{
29
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Port92State *s = opaque;
30
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int oldval = s->outport;
31
+
32
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trace_port92_write(val);
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s->outport = val;
34
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qemu_set_irq(s->a20_out, (val >> 1) & 1);
35
+
if ((val & 1) && !(oldval & 1)) {
36
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
37
+
}
38
+
}
39
+
40
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static uint64_t port92_read(void *opaque, hwaddr addr,
41
+
unsigned size)
42
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{
43
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Port92State *s = opaque;
44
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uint32_t ret;
45
+
46
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ret = s->outport;
47
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trace_port92_read(ret);
48
+
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return ret;
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}
51
+
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static const VMStateDescription vmstate_port92_isa = {
53
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.name = "port92",
54
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.version_id = 1,
55
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.minimum_version_id = 1,
56
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.fields = (VMStateField[]) {
57
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VMSTATE_UINT8(outport, Port92State),
58
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VMSTATE_END_OF_LIST()
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+
}
60
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};
61
+
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static void port92_reset(DeviceState *d)
63
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{
64
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Port92State *s = PORT92(d);
65
+
66
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s->outport &= ~1;
67
+
}
68
+
69
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static const MemoryRegionOps port92_ops = {
70
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.read = port92_read,
71
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.write = port92_write,
72
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.impl = {
73
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.min_access_size = 1,
74
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.max_access_size = 1,
75
+
},
76
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.endianness = DEVICE_LITTLE_ENDIAN,
77
+
};
78
+
79
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static void port92_initfn(Object *obj)
80
+
{
81
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Port92State *s = PORT92(obj);
82
+
83
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memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
84
+
85
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s->outport = 0;
86
+
87
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qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
88
+
}
89
+
90
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static void port92_realizefn(DeviceState *dev, Error **errp)
91
+
{
92
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ISADevice *isadev = ISA_DEVICE(dev);
93
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Port92State *s = PORT92(dev);
94
+
95
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isa_register_ioport(isadev, &s->io, 0x92);
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}
97
+
98
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static void port92_class_initfn(ObjectClass *klass, void *data)
99
+
{
100
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DeviceClass *dc = DEVICE_CLASS(klass);
101
+
102
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dc->realize = port92_realizefn;
103
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dc->reset = port92_reset;
104
+
dc->vmsd = &vmstate_port92_isa;
105
+
/*
106
+
* Reason: unlike ordinary ISA devices, this one needs additional
107
+
* wiring: its A20 output line needs to be wired up with
108
+
* qdev_connect_gpio_out_named().
109
+
*/
110
+
dc->user_creatable = false;
111
+
}
112
+
113
+
static const TypeInfo port92_info = {
114
+
.name = TYPE_PORT92,
115
+
.parent = TYPE_ISA_DEVICE,
116
+
.instance_size = sizeof(Port92State),
117
+
.instance_init = port92_initfn,
118
+
.class_init = port92_class_initfn,
119
+
};
120
+
121
+
static void port92_register_types(void)
122
+
{
123
+
type_register_static(&port92_info);
124
+
}
125
+
126
+
type_init(port92_register_types)
+1
-1
hw/i386/trace-events
+1
-1
hw/i386/trace-events
···
116
116
x86_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d"
117
117
x86_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d"
118
118
119
-
# pc.c
119
+
# port92.c
120
120
port92_read(uint8_t val) "port92: read 0x%02x"
121
121
port92_write(uint8_t val) "port92: write 0x%02x"
+3
include/hw/i386/pc.h
+3
include/hw/i386/pc.h